NXP Semiconductors UDA1352TS, Datasheet

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2002 Nov 22 6
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
7 PINNING
Note
1. See Table 1.
SYMBOL PIN TYPE
(1)
DESCRIPTION
PCMDET 1 DO PCM detection indicator output
TEST1 2 DO test pin 1; must be left open-circuit in application
V
DDD
3 DS digital supply voltage
SELIIC 4 DID I
2
C-bus or L3-bus mode selection input
RESET 5 DID reset input
V
DDD(C)
6 DS digital supply voltage for core
V
SSD
7 DGND digital ground
L3DATA 8 IIC L3-bus or I
2
C-bus interface data input and output
L3CLOCK 9 DIS L3-bus or I
2
C-bus interface clock input
L3MODE 10 DIS L3 interface mode input
MUTE 11 DID mute control input
V
SSD(C)
12 DGND digital ground for core
SPDIF 13 AIO IEC 60958 channel input
V
DDA(DAC)
14 AS analog supply voltage for DAC
VOUTL 15 AIO DAC left channel analog output
LOCK 16 DO SPDIF and PLL lock indicator output
VOUTR 17 AIO DAC right channel analog output
TEST2 18 DID test pin 2; must be connected to digital ground (V
SSD
) in application
V
ref
19 AIO DAC reference voltage
V
SSA(DAC)
20 AGND analog ground for DAC
n.c. 21
−
not connected
n.c. 22
−
not connected
V
SSA(PLL)
23 AGND analog ground for PLL
V
DDA(PLL)
24 AS analog supply voltage for PLL
DA1 25 DISU A1 device address selection input
SELSTATIC 26 DIU static pin control selection input
n.c. 27
−
not connected (reserved)
DA0 28 DID A0 device address selection input