NXP Semiconductors UDA1352TS, Datasheet

Page: 40 / 52

2002 Nov 22 40
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
12.11 FPLL status (read-out)
Table 56 Register address 68H
Table 57 Description of register bits
Table 58 Lock status indicators of the FPLL
BIT 15 14 13 12 11 10 9 8
Symbol
− − − − − − −
FPLL_
LOCK
BIT 7 6 5 4 3 2 1 0
Symbol
− − −
VCO_
TIMEOUT
− − − −
BIT SYMBOL DESCRIPTION
15 to 9
−
reserved
8 FPLL_LOCK FPLL lock. A 1-bit value that indicates the FPLL status together with bit 4; see Table 58.
7 to 5
−
reserved
4 VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8;
see Table 58.
3 to 0
−
reserved
FPLL_LOCK VCO_TIMEOUT FUNCTION
0 0 FPLL out-of-lock
0 1 FPLL time-out
1 0 FPLL in lock
1 1 FPLL time-out