NXP Semiconductors UDA1352TS, Datasheet

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2002 Nov 22 25
NXP Semiconductors Preliminary specification
48 kHz IEC 60958 audio DAC UDA1352TS
12.1 SPDIF mute setting (write)
Table 19 Register address 01H
Table 20 Description of register bits
BIT 15 14 13 12 11 10 9 8
Symbol
− − − − − − −
MUTEBP
Default
− − − − − − −
0
BIT 7 6 5 4 3 2 1 0
Symbol
− − − − − − − −
Default
− − − − −
0 0 0
BIT SYMBOL DESCRIPTION
15 to 9
−
reserved
8 MUTEBP Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute
bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected,
the output data will not be suppressed. If this bit is logic 0, then the output will be muted in
out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock
situations. Default value 0.
7 to 3
−
reserved
2 to 0
−
When writing new settings via the L3-bus or I
2
C-bus interface, these bits should always
remain at logic 0 (default value) to guarantee correct operation.