NXP Semiconductors UDA1352TS Datasheet Download Page 7

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2002 Nov 22

NXP Semiconductors

Preliminary specification

48 kHz IEC 60958 audio DAC

UDA1352TS

Table 1

Pin types

TYPE

DESCRIPTION

digital supply

DGND

digital ground

analog supply

AGND

analog ground

digital input

DIS

digital Schmitt-triggered input

DID

digital input with internal pull-down resistor

DISD

digital Schmitt-triggered input with internal pull-down resistor

DIU

digital input with internal pull-up resistor

DISU

digital Schmitt-triggered input with internal pull-up resistor

digital output

DIO

digital input and output

DIOS

digital Schmitt-triggered input and output

IIC

input and open-drain output for I

C-bus

AIO

analog input and output

handbook, halfpage

UDA1352TS

MGU654

PCMDET

TEST1

VDDD

SELIIC

RESET

VDDD(C)

VSSD

L3DATA

L3CLOCK

L3MODE

MUTE

VSSD(C)

SPDIF

VDDA(DAC)

DA0

n.c.

SELSTATIC

DA1

VDDA(PLL)

VSSA(PLL)

n.c.

VSSA(DAC)

Vref

TEST2

VOUTR

LOCK

VOUTL

Fig.2 Pin configuration.

Summary of Contents for UDA1352TS

Page 1: ...DATA SHEET Preliminary specification Supersedes data of 2002 May 22 2002 Nov 22 INTEGRATED CIRCUITS UDA1352TS 48 kHz IEC 60958 audio DAC...

Page 2: ...read data 10 10 Write cycle 10 11 Read cycle 11 SPDIF SIGNAL FORMAT 11 1 SPDIF channel encoding 11 2 SPDIF hierarchical layers for audio data 11 3 SPDIF hierarchical layers for digital data 11 4 Timin...

Page 3: ...erface Left and right independent dB linear volume control with 0 25 dB steps from 0 to 50 dB 1 dB steps to 60 66 and dB Bass boost and treble control in L3 bus or I2C bus mode Interpolating filter fs...

Page 4: ...wer on 3 3 mA power down clock off 35 A IDDA PLL analog supply current of PLL 0 3 mA IDDD C digital supply current of core 9 mA IDDD digital supply current 0 3 mA P power dissipation DAC in playback m...

Page 5: ...T 1 LOCK 16 n c 21 22 27 DAC VOUTL 15 DAC VDDA DAC 14 VSSA DAC 20 Vref 19 TEST1 2 TEST2 18 AUDIO FEATURE PROCESSOR INTERPOLATOR NOISE SHAPER IEC 60958 DECODER SLICER L3 BUS OR I2C BUS INTERFACE NON PC...

Page 6: ...DIS L3 interface mode input MUTE 11 DID mute control input VSSD C 12 DGND digital ground for core SPDIF 13 AIO IEC 60958 channel input VDDA DAC 14 AS analog supply voltage for DAC VOUTL 15 AIO DAC lef...

Page 7: ...tal input with internal pull up resistor DISU digital Schmitt triggered input with internal pull up resistor DO digital output DIO digital input and output DIOS digital Schmitt triggered input and out...

Page 8: ...t out of band noise from becoming audible when the PLL runs at its minimum frequency e g when there is no SPDIF input signal The UDA1352TS has a dedicated pin PCMDET to indicate whether valid PCM data...

Page 9: ...UDIO FEATURE PROCESSOR The audio feature processor automatically provides de emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start up in the L3 bus or I2C bus...

Page 10: ...ELSTATIC and SELIIC are LOW For optimum use of the features of the UDA1352TS the L3 bus or I2C bus mode is recommended since only basic functions are available in the static pin control mode It should...

Page 11: ...elect L3 bus mode or I2C bus mode must be connected to VSSD 4 SELIIC 0 select L3 bus mode must be connected to VSSD 1 select I2C bus mode must be connected to VDDD Input pins 5 RESET 0 normal operatio...

Page 12: ...tion data transfer from the device Remark when the device is powered up at least one L3CLOCK pulse must be given to the L3 bus interface to wake up the interface before starting sending to the device...

Page 13: ...after power up device address DOM bits register address data byte 1 data byte 2 1 0 Fig 5 Data write mode for L3 bus version 2 MBL565 L3CLOCK L3MODE L3DATA 0 read valid invalid device address prepare...

Page 14: ...action from the register followed by seven bits for the source register address in binary format with A6 being the MSB and A0 being the LSB 3 One byte with the device address preceded by 11 is sent t...

Page 15: ...or 2 way 2 line communication between different ICs or modules The two lines are a serial data line SDA and a serial clock line SCL Both lines must be connected to the VDD via a pull up resistor when...

Page 16: ...on the I2C bus 10 6 Acknowledgment The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited Each byte of eight bits is followed by one...

Page 17: ...by pin DA0 and pin DA1 The UDA1352TS acts as a slave receiver or a slave transmitter Therefore the clock signal SCL is only an input signal The data signal SDA is a bidirectional line The UDA1352TS de...

Page 18: ...egister address ADDR where the writing of the register content of the UDA1352TS must start 5 The UDA1352TS acknowledges this register address A 6 The microcontroller sends 2 bytes data with the Most S...

Page 19: ...device address 1001 110 again but this time followed by a logic 1 read of the R W bit An acknowledge is followed from the UDA1352TS 8 The UDA1352TS sends 2 bytes data with the Most Significant MS byt...

Page 20: ...or this particular sub frame see Fig 12 The data bits from 4 to 31 in each sub frame will be modulated using a BMC scheme The sync preamble actually contains a violation of the BMC scheme and conseque...

Page 21: ...frame Fig 11 SPDIF block format handbook full pagewidth sync preamble auxiliary 0 3 4 7 8 27 28 31 L S B L S B M S B P audio sample word C U V validity flag user data channel status parity bit MGU608...

Page 22: ...nc word 1 F872 hex Pb 16 bits sync word 2 4E1F hex Pc 16 bits burst information see Table 16 Pd 16 bits length code number of bits BITS OF Pc VALUE CONTENTS REFERENCE POINT R REPETITION TIME OF DATA B...

Page 23: ...ree levels of clock accuracy being Level I high accuracy tolerance of transmitting sampling frequency shall be within 50 10 6 Level II normal accuracy all receivers should receive a signal of 1000 10...

Page 24: ...volume control left and right 12H sound feature mode treble and bass boost 13H mute 14H polarity SPDIF input settings 30H SPDIF input settings Software reset 7FH restore L3 bus default values REGISTE...

Page 25: ...etting A 1 bit value to disable the mute bypass setting When this mute bypass setting is enabled then even in out of lock situations or non PCM data detected the output data will not be suppressed If...

Page 26: ...then the power is off If this bit is logic 1 then the power is on Default value 1 3 to 2 When writing new settings via the L3 bus or I2C bus interface these bits should always remain at logic 0 defaul...

Page 27: ...lue to program the left channel volume attenuation The range is 0 to 50 dB in steps of 0 25 dB to 60 dB in steps of 1 dB 66 dB and dB Default value 0000 0000 see Table 25 7 to 0 VCR_ 7 0 Volume settin...

Page 28: ...o 14 M 1 0 Sound feature mode A 2 bit value to program the sound processing filter sets modes of bass boost and treble Default value 00 see Table 28 13 to 12 TR 1 0 Treble settings A 2 bit value to pr...

Page 29: ...t settings BB3 BB2 BB1 BB0 FLAT SET dB MINIMUM SET dB MAXIMUM SET dB 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 0 1 1 0 0 12 12 0 1 1 1 0 14 14 1 0 0 0 0 16...

Page 30: ...it is logic 1 then the quick mute mode is selected Default value 0 14 MT Mute A 1 bit value to set the mute function If this bit is logic 0 then the audio output is not muted unless pin MUTE is logic...

Page 31: ...is bit is logic 0 then the DAC output is not inverted If this bit is logic 1 then the DAC output is inverted Default value 0 14 When writing new settings via the L3 bus or I2C bus interface this bit s...

Page 32: ...CM detection status to the lock indicator If this bit is logic 0 then the lock indicator does not contain PCM detection status If this bit is logic 1 then the PCM detection status is combined with the...

Page 33: ...register bits BIT 15 14 13 12 11 10 9 8 Symbol BIT 7 6 5 4 3 2 1 0 Symbol MUTE_ STATE BIT SYMBOL DESCRIPTION 15 to 3 reserved 2 MUTE_STAT E Mute status bit A 1 bit value to indicate the status of the...

Page 34: ...rds are detected in the SPDIF stream or not If this bit is logic 0 then no preamble words are detected If this bit is logic 1 then burst payload is detected 1 B_ERR Bit error detection A 1 bit value t...

Page 35: ...0 Symbol SPDI_ BIT7 SPDI_ BIT6 SPDI_ BIT5 SPDI_ BIT4 SPDI_ BIT3 SPDI_ BIT2 SPDI_ BIT1 SPDI_ BIT0 BIT 15 14 13 12 11 10 9 8 Symbol SPDI_ BIT31 SPDI_ BIT30 SPDI_ BIT29 SPDI_ BIT28 SPDI_ BIT27 SPDI_ BIT2...

Page 36: ...en the maximum length is 24 bits 31 to 30 SPDI_BIT 31 30 reserved 29 to 28 SPDI_BIT 29 28 Clock accuracy A 2 bit value indicating the clock accuracy see Table 49 27 to 24 SPDI_BIT 27 24 Sample frequen...

Page 37: ...1 reserved reserved 1 0 0 19 bits 23 bits 1 0 1 20 bits 24 bits 1 1 0 17 bits 21 bits 1 1 1 reserved reserved SPDI_BIT29 SPDI_BIT28 CLOCK ACCURACY 0 0 level II 0 1 level I 1 0 level III 1 1 reserved...

Page 38: ...0 L 1 1 0 1 M 1 1 1 0 N 1 1 1 1 O SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 SOURCE NUMBER 0 0 0 0 don t care 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9...

Page 39: ...rmation 011 00xxL analog to digital converters for analog signals without copyright information 011 01xxL analog to digital converters for analog signals which include copyright information in the for...

Page 40: ...11 10 9 8 Symbol FPLL_ LOCK BIT 7 6 5 4 3 2 1 0 Symbol VCO_ TIMEOUT BIT SYMBOL DESCRIPTION 15 to 9 reserved 8 FPLL_LOCK FPLL lock A 1 bit value that indicates the FPLL status together with bit 4 see...

Page 41: ...te 2 2000 2000 V Machine Model MM note 3 200 200 V Ilu prot latch up protection current Tamb 125 C VDD 3 6 V 200 mA Isc DAC short circuit current of DAC Tamb 0 C VDD 3 V note 4 output short circuited...

Page 42: ...int internal pull down resistance 16 33 78 k Digital outputs VOH HIGH level output voltage IOH 2 mA 0 85VDDD V VOL LOW level output voltage IOL 2 mA 0 4 V IO max maximum output current 3 mA Digital t...

Page 43: ...d time in address mode 190 ns tsu L3 D L3MODE set up time in data transfer mode 190 ns th L3 D L3MODE hold time in data transfer mode 190 ns t stp L3 L3MODE stop time in data transfer mode 190 ns tsu...

Page 44: ...0 ns tHD DAT data hold time 0 s tSP pulse width of spikes to be suppressed by the input filter 0 50 ns Cb capacitive load for each bus line 400 pF SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT handbook...

Page 45: ...th L3 DA tsu L3 DA th L3 D Tcy CLK L3 BIT 0 L3MODE L3CLOCK L3DATA read L3DATA write BIT 7 MBL566 tCLK L3 H tCLK L3 L td L3 R tdis L3 R Fig 16 Timing for data transfer mode handbook full pagewidth MSC6...

Page 46: ...6 SELSTATIC S2 VDDD no mute mute 2 3 1 11 MUTE DA1 C18 47 F 16 V X3 R8 10 k R7 100 15 19 VOUTL Vref left_out C17 47 F 16 V X2 R6 10 k R5 100 RESET 18 24 23 TEST2 C15 100 nF 50 V C14 10 F 16 V C20 100...

Page 47: ...1 65 0 38 0 25 0 20 0 09 10 4 10 0 5 4 5 2 0 65 1 25 7 9 7 6 0 9 0 7 1 1 0 7 8 0 o o 0 13 0 1 0 2 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 2 mm maximum per si...

Page 48: ...wetting can present major problems To overcome these problems the double wave soldering method was specifically developed If wave soldering is used the following conditions must be observed for optim...

Page 49: ...ottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 4 If wave...

Page 50: ...ifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors...

Page 51: ...or intellectual property rights Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from nation...

Page 52: ...document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence o...

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