20
02
N
o
v
2
2
1
9
NXP Semiconductors
Preli
m
inary specification
48 kHz IEC 60958 audio DAC
U
DA1352TS
10.11 Read cycle
The read cycle is used to read the data values from the internal registers. The I
2
C-bus configuration for a read cycle is shown in Table 12.
The format of the read cycle is as follows:
1.
The microcontroller starts with a start condition (S).
2.
The first byte (8 bits) contains the device address ‘1001 110’ and a logic 0 (write) for the R/W bit.
3.
This is followed by an acknowledge (A) from the UDA1352TS.
4.
After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1352TS must start.
5.
The UDA1352TS acknowledges this register address.
6.
Then the microcontroller generates a repeated start (Sr).
7.
Then the microcontroller generates the device address ‘1001 110’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge
is followed from the UDA1352TS.
8.
The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an
acknowledge is followed from the microcontroller.
9.
If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the
microcontroller.
10. The microcontroller stops this cycle by generating a negative acknowledge (NA).
11. Finally, the UDA1352TS frees the I
2
C-bus and the microcontroller can generate a stop condition (P).
Table 12
Master transmitter reads from the UDA1352TS registers in the I
2
C-bus mode.
Note
1.
Auto increment of register address.
DEVICE
ADDRESS
R/W
REGISTER
ADDRESS
DEVICE
ADDRESS
R/W
DATA 1
DATA 2
DATA n
S
1001 110
0
A
ADDR
A
Sr
1001 110
1
A
MS1
A
LS1
A
MS2
A
LS2
A
MSn
A
LSn
NA
P
acknowledge from UDA1352TS
acknowledge from master
