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NEC V850E/IA1 mPD703116, User Manual


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CHAPTER  9   TIMER/COUNTER  FUNCTION  (REAL-TIME  PULSE  UNIT)

237

User’s Manual  U14492EJ3V0UD

(3/4)

Bit Position

Bit Name

Function

Specifies transfer of data from BFCMn3 register to CM0n3 register.

0:  Transfer disabled
1:  Transfer enabled

The transfer timing from the BFCMn3 register to the CM0n3 register is as follows.

BFTE3

TM0n Operation Mode

BFCMn3 

→

 CM0n3 Transfer

Timing

0

All modes

Don’t transfer

1

PWM mode 0 (symmetric
triangular wave)

INTTM0n

1

PWM mode 1 (asymmetric
triangular wave)

INTTM0n

1

PWM mode 2 (sawtooth wave)

INTCM0n3

4

BFTE3

When the BFTE3 bit = 1, the value of the BFCMn3 register is transferred to the
CM0n3 register upon occurrence of an INTTM0n or INTCM0n3 interrupt.

Specifies transfer of data from BFCMn0 to BFCMn2 registers to CM0n0 to CM0n2
registers.

0:  Transfer disabled
1:  Transfer enabled

BFTEN

TM0n Operation Mode

BFCMn0 to BFCMn2 

→

 CM0n0 to

CM0n2 Transfer Timing

0

All modes

Don’t transfer

1

PWM mode 0 (symmetric
triangular wave)

INTTM0n

1

PWM mode 1 (asymmetric
triangular wave)

INTTM0n, INTCM0n3

1

PWM mode 2 (sawtooth wave)

INTCM0n3

3

BFTEN

When the BFTEN bit = 1, the values of the BFCMn0 to BFCMn2 registers are
transferred to the CM0n0 to CM0n2 registers upon occurrence of an INTTM0n or
INTCM0n3 interrupt.

When culling of INTTM0n and INTCM0n3 interrupts is set with the CUL02 to CUL00
bits, specifies whether enable or disable the BFTE3 and BFTEN bit settings upon
occurrence of an interrupt for culling.

0:

Disable the set values of BFTE3, BFTEN bits upon occurrence of a culling
interrupt

1:

Enable the set values of BFTE3, BFTEN bits upon occurrence of a culling
interrupt

The various combinations are as follows.

Operation upon Occurrence of Interrupt for Culling

MBFTE

0

1

0

BFCMn0 to BFCMn2 

→

CM0n0 to CM0n2 transfer
disabled

BFCMn0 to BFCMn2 

→

 CM0n0

to CM0n2 transfer disabled

BFTEN

1

BFCMn0 to BFCMn2 

→

CM0n0 to CM0n2 transfer
disabled

BFCMn0 to BFCMn2 

→

 CM0n0

to CM0n2 transfer enabled

0

BFCMn3 

→

 CM0n3

transfer disabled

BFCMn3 

→

 CM0n3 transfer

disabled

BFTE3

1

BFCMn3 

→

 CM0n3

transfer disabled

BFCMn3 

→

 CM0n3 transfer

enabled

2

MBFTE

.

Remark

n = 0, 1

Summary of Contents for V850E/IA1 mPD703116

Page 1: ...Document No U14492EJ3V0UD00 3rd edition Date Published February 2003 N CP K V850E IA1 TM 32 Bit Single Chip Microcontrollers Hardware User s Manual PD703116 PD703116 A PD703116 A1 PD70F3116 PD70F3116...

Page 2: ...2 User s Manual U14492EJ3V0UD MEMO...

Page 3: ...pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices...

Page 4: ...ety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death...

Page 5: ...6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 NEC...

Page 6: ...ition of description to 6 3 8 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 p 158 Modification of description in Table 6 1 Relationship Between Transfer Type and Transfer Object p 158 Modificatio...

Page 7: ...ine operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers Cautions 1 The ap...

Page 8: ...lower address on the bottom Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx...

Page 9: ...ger Operation WindowsTM Based U15181E SM850 Ver 2 40 System Simulator Operation Windows Based U15182E SM850 Ver 2 00 or Later System Simulator External Part User Open Interface Specifications U14873E...

Page 10: ...res 62 3 2 CPU Register Set 63 3 2 1 Program register set 64 3 2 2 System register set 65 3 3 Operation Modes 67 3 3 1 Operation modes 67 3 3 2 Operation mode specification 68 3 4 Address Space 69 3 4...

Page 11: ...5 MEMORY ACCESS CONTROL FUNCTION 132 5 1 SRAM External ROM External I O Interface 132 5 1 1 Features 132 5 1 2 SRAM external ROM external I O access 133 CHAPTER 6 DMA FUNCTIONS DMA CONTROLLER 138 6 1...

Page 12: ...e Interrupts 172 7 3 1 Operation 172 7 3 2 Restore 174 7 3 3 Priorities of maskable interrupts 175 7 3 4 Interrupt control register xxICn 179 7 3 5 Interrupt mask registers 0 to 3 IMR0 to IMR3 182 7 3...

Page 13: ...1 6 Operation timing 289 9 2 Timer 1 298 9 2 1 Features timer 1 298 9 2 2 Function overview timer 1 298 9 2 3 Basic configuration 300 9 2 4 Control registers 307 9 2 5 Operation 318 9 2 6 Supplementa...

Page 14: ...tion 459 10 3 6 Synchronous mode 469 10 3 7 Dedicated baud rate generators 1 2 BRG1 BRG2 474 10 4 Clocked Serial Interfaces 0 1 CSI0 CSI1 482 10 4 1 Features 482 10 4 2 Configuration 483 10 4 3 Contro...

Page 15: ...ut Down FCAN Controller 625 11 17 Cautions on Use 626 CHAPTER 12 NBD FUNCTION PD70F3116 627 12 1 Overview 627 12 2 NBD Function Register Map 628 12 3 NBD Function Protocol 629 12 4 NBD Function 632 12...

Page 16: ...tch interrupt in timer trigger mode 672 13 10 6 Timing that makes the A D conversion result undefined 672 13 11 How to Read A D Converter Characteristics Table 673 CHAPTER 14 PORT FUNCTIONS 677 14 1 F...

Page 17: ...6 Self programming function number 744 16 7 7 Calling parameters 745 16 7 8 Contents of RAM parameters 746 16 7 9 Errors during self programming 747 16 7 10 Flash information 747 16 7 11 Area number...

Page 18: ...18 User s Manual U14492EJ3V0UD APPENDIX C INSTRUCTION SET LIST 805 C 1 Functions 805 C 2 Instruction Set Alphabetical Order 808 APPENDIX D INDEX 814 APPENDIX E REVISION HISTORY 823...

Page 19: ...60 7 1 Servicing Configuration of Non Maskable Interrupt 168 7 2 Acknowledging Non Maskable Interrupt Request 169 7 3 RETI Instruction Processing 170 7 4 Servicing Configuration of Maskable Interrupt...

Page 20: ...Timing in PWM Mode 0 Symmetric Triangular Wave BFCMnx 0000H 265 9 19 Change Timing from 100 Duty State PWM Mode 0 266 9 20 Operation Timing in PWM Mode 1 Asymmetric Triangular Wave 270 9 21 Overall O...

Page 21: ...TM1n Operation When Interval Operation and Transfer Operation Are Combined 327 9 55 Example of TM1n Operation in UDC Mode 329 9 56 Clear Operation upon Match with CM1n0 During TM1n Up Count Operation...

Page 22: ...E0 Register s ODLEn2 to ODLEn0 Bits 0 374 9 79 Signal Output Operation Toggle Mode 2 and Toggle Mode 3 When OCTLE0 Register s SWFEn Bit 0 and ODELE0 Register s ODLEn2 to ODLEn0 Bits 0 375 9 80 Signal...

Page 23: ...ous Mode 469 10 21 Transmission Reception Timing Chart for Synchronous Mode 470 10 22 Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception 473 10 23 B...

Page 24: ...1SYNC Settings 604 11 32 CAN1 Interrupt Enable Register C1IE Settings 605 11 33 CAN1 Definition Register C1DEF Settings 606 11 34 CAN1 Control Register C1CTRL Settings 607 11 35 CAN1 Address Mask a Re...

Page 25: ...Conversion Result Read Timing When Conversion Result Is Undefined 672 13 15 Conversion Result Read Timing When Conversion Result Is Normal 672 13 16 Overall Error 673 13 17 Quantization Error 674 13...

Page 26: ...16 14 Example of Self Programming Circuit Configuration 741 16 15 Timing to Apply Voltage to VPP Pin 742 16 16 Area Configuration 748 16 17 Erasing Flash Memory Flow 754 16 18 Continuous Writing Flow...

Page 27: ...t Request 221 8 6 Operation Status in Software STOP Mode 222 8 7 Operation After Software STOP Mode Is Released by Interrupt Request 223 8 8 Counting Time Examples fXX 10 fX 225 9 1 Timer 0 Operation...

Page 28: ...11 13 Error Counter 543 11 14 Addresses of M_DLCn n 00 to 31 551 11 15 Addresses of M_CTRLn n 00 to 31 554 11 16 Addresses of M_TIMEn n 00 to 31 555 11 17 Addresses of M_DATAnx n 00 to 31 x 0 to 7 557...

Page 29: ...ion of V850E IA1 Flash Programming Adapter FA 144GJ 8EU 730 16 2 Pins Used by Each Serial Interface 733 16 3 List of Communication Mode 737 16 4 Commands for Controlling Flash Memory 738 16 5 Response...

Page 30: ...luding processing by the on chip interrupt controller also is fast this CPU is suited to the realm of advanced real time control 2 External bus interface function As the external bus interface there i...

Page 31: ...ided Provided pins also used with CSI1 UART2 Provided Not provided CSI0 Provided Provided CSI1 Provided Provided pins also used with UART1 Serial interface FCAN Provided Not provided Debug support fun...

Page 32: ...ons Signed load instructions Memory space 256 MB linear address space shared by program and data Chip select output function 8 spaces Memory block division function 2 4 or 8 MB block Programmable wait...

Page 33: ...channel Serial interface SIO Asynchronous serial interface UART 3 channels Clocked serial interface CSI 2 channels FCAN Full Controller Area Network 1 channel NBD Non Break Debug function 1 channel PD...

Page 34: ...A1 UEN 144 pin plastic LQFP fine pitch 20 20 Special Remark xxx ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Electronics Corporatio...

Page 35: ...6 PDL6 AD7 PDL7 AD8 PDL8 AD9 PDL9 AD10 PDL10 AD11 PDL11 AD12 PDL12 AD13 PDL13 AD14 PDL14 AD15 PDL15 ANI06 ANI05 ANI04 ANI03 ANI02 ANI01 ANI00 AV REF0 AV SS AV DD TO015 TO014 TO013 TO012 TO011 TO010 V...

Page 36: ...ontroller area network Clock generator power supply Clock generator ground Emergency shut off Hold acknowledge Hold request Internally connected Interrupt request from peripherals Lower write strobe M...

Page 37: ...rrel shifter Multiplier 32 32 64 CPU ROM RAM BCU ALU MEMC HLDRQ HLDAK CS0 to CS7 CKSEL CLKOUT X1 X2 CVDD CVSS PDL0 to PDL15 PDH0 to PDH7 PCS0 to PCS7 PCT0 to PCT7 PCM0 to PCM4 P40 to P47 P30 to P37 P2...

Page 38: ...le step transfer and block transfer 5 ROM There is on chip flash memory 256 KB in the PD70F3116 and mask ROM 256 KB in the PD703116 On an instruction fetch the ROM can be accessed by the CPU in one cl...

Page 39: ...NBD on chip as a debugging interface PD70F3116 only 12 A D converter ADC Two units of a high speed high resolution 10 bit A D converter having eight analog input pins are implemented The ADC converts...

Page 40: ...3_DBG SYNC CLK_DBG Flash memory programming pin Not provided IC5 Provided VPP Flash memory programming mode Not provided Provided MODE0 H L MODE1 H MODE2 L VPP 7 8 V Quality grade Standard grade Speci...

Page 41: ...ort 0 8 bit input only port INTP6 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 I O Port 1 6 bit I O port Input or output can be specified in 1 bit units...

Page 42: ...Port CM 5 bit I O port Input or output can be specified in 1 bit units PCT0 LWR PCT1 UWR PCT2 PCT3 PCT4 RD PCT5 PCT6 ASTB PCT7 I O Port CT 8 bit I O port Input or output can be specified in 1 bit unit...

Page 43: ...e I O Function Alternate Function PDL0 AD0 PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL5 AD5 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 PDL15 I O Port DL 16...

Page 44: ...1 ESO0 P01 INTP0 ESO1 I Timer 00 or 01 output stop signal input P02 INTP1 TIUD10 P10 TO10 TIUD11 I External count clock input to up down counter timer 10 or 11 P13 TO11 TCUD10 P11 INTP100 TCUD11 I Cou...

Page 45: ...41 SO1 O Serial transmit data output 3 wire of CSI0 and CSI1 P44 SI0 P40 SI1 I Serial receive data input 3 wire of CSI0 and CSI1 P43 SCK0 P42 SCK1 I O Serial clock I O 3 wire of CSI0 and CSI1 P45 TXD0...

Page 46: ...m clock generation Input to X1 pin when providing clocks from outside CLKOUT O System clock output PCM1 CKSEL I Input specifying clock generator operation mode AVREF0 I Reference voltage input for A D...

Page 47: ...Z Hi Z Hi Z Operating Hi Z AD0 to AD15 PDL0 to PDL15 Hi Z Hi Z Hi Z Operating Hi Z CS0 to CS7 PCS0 to PCS7 Hi Z Hi Z H Operating Hi Z LWR UWR PCT0 PCT1 Hi Z Hi Z H Operating Hi Z RD PCT4 Hi Z Hi Z H...

Page 48: ...re the input port cannot be switched with the NMI input pin RPU output stop signal input pin external interrupt request input pin and A D converter ADC external trigger input pin Read the status of ea...

Page 49: ...PMC1 i TO10 TO11 Timer output Output These pins output timer 10 and timer 11 pulse signals ii TIUD10 TIUD11 Timer count pulse input Input These are external count clock input pins to the up down count...

Page 50: ...ol mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 i TO21 to TO24 Timer output Output These pins output a timer 2 pulse signal ii TO3 Timer output Output This pin outputs...

Page 51: ...bit and specified by the port 3 mode control register PMC3 a Port mode P30 to P37 can be set to input or output in 1 bit units using the port 3 mode register PM3 b Control mode P30 to P37 can be set...

Page 52: ...o P47 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P47 can be set to port or control mode in 1 bit units using PMC4 i SO0 SO1 Serial output Out...

Page 53: ...clock output pin In single chip mode 1 and ROMless mode 0 or 1 output is not performed by the CLKOUT pin because it is in port mode during the reset period To perform CLKOUT output set this pin to co...

Page 54: ...the bus cycle is a lower memory write it becomes active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a T2 state CLKOUT signal ii UWR Upper byte write str...

Page 55: ...l peripheral I O The signal CSn is assigned to memory block n n 0 to 7 This is active for the period during which a bus cycle that accesses the corresponding memory block is activated It is inactive i...

Page 56: ...DL0 to PDL15 can be used as AD0 to AD15 by using PMCDL i AD0 to AD15 Address data bus I O This is a multiplexed bus for an address or data on an external access When used for an address T1 state they...

Page 57: ...ode 0 V L L L ROMless mode 0 0 V L L H ROMless mode 1 0 V L H L Single chip mode 0 0 V L H H Normal operation mode Single chip mode 1 7 8 V L H Flash memory programming mode Other than above Setting p...

Page 58: ...3 3 V interface 25 SYNC Debug synchronization Input This is the command synchronization input pin for debugging 3 3 V interface 26 AD0_DBG to AD3_DBG Debug address data bus I O These are command inter...

Page 59: ...o P07 INTP6 2 Connect directly to VSS5 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25...

Page 60: ...to AD3_DBGNote 1 5 AC Independently connect to CVDD or CVSS via a resistor TRIG_DBGNote 1 3 Leave open low level output CLK_DBGNote 1 Independently connect to CVSS via a resistor SYNCNote 1 2 Independ...

Page 61: ...istics IN Type 3 P ch OUT VDD N ch Type 4 Push pull output with possible high impedance output P ch N ch both off Data Output disable P ch OUT VDD N ch Type 5 Data Output disable P ch IN OUT VDD N ch...

Page 62: ...ion execution time 20 ns internal 50 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pi...

Page 63: ...26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR In...

Page 64: ...ters Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating address r2 Address data variable register when not being used by the real time...

Page 65: ...gister during CALLT execution CTPSW 18 Status saving register during exception debug trap DBPC Note 2 19 Status saving register during exception debug trap DBPSW Note 2 20 CALLT base pointer CTBP 21 t...

Page 66: ...rated To clear 0 this bit load the data in PSW Note that in a general arithmetic operation this bit is neither set 1 nor cleared 0 0 Not saturated 1 Saturated 3 CY This flag is set if carry or borrow...

Page 67: ...ernal device s memory reset entry address and instruction processing starts The internal ROM area is mapped from address 100000H b ROMless modes 0 1 After the system reset is cleared each pin related...

Page 68: ...bus L H L Single chip mode 0 Internal ROM area is allocated from address 000000H L H H Normal operation mode Single chip mode 1 Internal ROM area is allocated from address 100000H Other than above Set...

Page 69: ...to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 1...

Page 70: ...ws the image of the virtual addressing space Physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 10000000H address 20000000H address E0000000H or add...

Page 71: ...come contiguous Caution The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to 0FFFFFFFH No instruction can be fetched from this area because this area is defined as on chip p...

Page 72: ...a On chip peripheral I O area Internal RAM area Access prohibitedNote External memory area Internal ROM area External memory area Internal ROM area External memory area Single chip mode 0 Single chip...

Page 73: ...sh memory area Single chip mode 0 Single chip mode 1 0FFFFFH 040000H 000000H 03FFFFH 1FFFFFH 140000H 100000H 13FFFFH b Interrupt exception table The V850E IA1 increases the interrupt response speed by...

Page 74: ...1 000000B0H INTP3 00000280H INTCM4 000000C0H INTP4 00000290H INTDMA0 000000D0H INTP5 000002A0H INTDMA1 000000E0H INTP6 000002B0H INTDMA2 000000F0H INTDET0 000002C0H INTDMA3 00000100H INTDET1 000002D0H...

Page 75: ...ROM Area in Single Chip Mode 1 Internal ROM area External memory area 200000H 1FFFFFH 100000H 0FFFFFH 000000H Block 0 Note Note See 4 3 Memory Block Function 2 Internal RAM area 12 KB of memory addre...

Page 76: ...f the hardware specification 2 In the V850E IA1 no registers exist that are capable of word access but if a register is word accessed halfword access is performed twice in the order of lower address t...

Page 77: ...n in single chip mode 1 x0000000H to x00FFFFFH x0200000H to xFFFBFFFH When in ROMless modes 0 and 1 x0000000H to xFFFBFFFH Access to the external memory area uses the chip select signal assigned to ea...

Page 78: ...anges to the port n mode control register PMCn the external data bus width is 16 bits b In the case of ROMless mode 1 Because each pin of ports DH DL CS CT and CM enters control mode following a reset...

Page 79: ...om address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources that make use of the wrap around feature of the data space the c...

Page 80: ...x00FFFFFH x0040000H x003FFFFH x0000000H xFFFFA78H xFFFFA77H Data space Program space On chip peripheral I O On chip peripheral I O Internal RAM Internal RAM External memory Internal ROM External memor...

Page 81: ...FF046H Port DH mode control register PMCDH R W 00H FFH FFFFF048H Port CS mode control register PMCCS R W 00H FFH FFFFF04AH Port CT mode control register PMCCT R W 00H 53H FFFFF04CH Port CM mode contro...

Page 82: ...ster 3 DADC3 R W 0000H FFFFF0E0H DMA channel control register 0 DCHC0 R W 00H FFFFF0E2H DMA channel control register 1 DCHC1 R W 00H FFFFF0E4H DMA channel control register 2 DCHC2 R W 00H FFFFF0E6H DM...

Page 83: ...7H FFFFF138H Interrupt control register CM11IC1 R W 47H FFFFF13AH Interrupt control register TM2IC0 R W 47H FFFFF13CH Interrupt control register TM2IC1 R W 47H FFFFF13EH Interrupt control register CC2...

Page 84: ...DSCM00H R W 00H FFFFF202H A D scan mode register 01 ADSCM01 R W 0000H FFFFF202H A D scan mode register 01L ADSCM01L R 00H FFFFF203H A D scan mode register 01H ADSCM01H R W 00H FFFFF204H A D voltage de...

Page 85: ...t 1 P1 R W Undefined FFFFF404H Port 2 P2 R W Undefined FFFFF406H Port 3 P3 R W Undefined FFFFF408H Port 4 P4 R W Undefined FFFFF422H Port 1 mode register PM1 R W FFH FFFFF424H Port 2 mode register PM2...

Page 86: ...B6H Buffer register CM12 BFCM12 R W FFFFH FFFFF5B8H Buffer register CM13 BFCM13 R W FFFFH FFFFF5BAH Timer control register 01 TMC01 R W 0508H FFFFF5BAH Timer control register 01L TMC01L R W 08H FFFFF5...

Page 87: ...FFF618H Timer 11 noise elimination time selection register NRC11 R W 00H FFFFF620H Timer connection selection register 0 TMIC0 R W 00H FFFFF630H Timer 2 input filter mode register 0 FEM0 R W 00H FFFFF...

Page 88: ...nnel 1 main capture compare register CVPE10 R 0000H FFFFF654H Timer 2 sub channel 2 sub capture compare register CVSE20 R W 0000H FFFFF656H Timer 2 sub channel 2 main capture compare register CVPE20 R...

Page 89: ...H FFFFF812H DMA trigger factor register 1 DTFR1 R W 00H FFFFF814H DMA trigger factor register 2 DTFR2 R W 00H FFFFF816H DMA trigger factor register 3 DTFR3 R W 00H FFFFF820H Power save mode register P...

Page 90: ...R 0000H FFFFF916H Clocked serial interface read only reception buffer register L1 SIRBEL1 R 00H FFFFF918H Clocked serial interface initial transmission buffer register 1 SOTBF1 R W 0000H FFFFF918H Cl...

Page 91: ...ister L2 TXSL2 W Undefined FFFFFA48H Asynchronous serial interface mode register 20 ASIM20 R W 81H FFFFFA4AH Asynchronous serial interface mode register 21 ASIM21 R W 00H FFFFFA4CH Asynchronous serial...

Page 92: ...this area the written contents are reflected on the on chip peripheral I O area Therefore access to this area is prohibited To access the on chip peripheral I O area be sure to specify addresses FFFF0...

Page 93: ...4 PA03 PA02 PA01 PA00 FFFFF064H 0000H Bit Position Bit Name Function Enables disables usage of programmable peripheral I O area PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of progr...

Page 94: ...et clear register 00 SC_STAT00 W 0000H xxxxn824H CAN message data length register 01 M_DLC01 R W Undefined xxxxn825H CAN message control register 01 M_CTRL01 R W Undefined xxxxn826H CAN message time s...

Page 95: ...e data register 030 M_DATA030 R W Undefined xxxxn869H CAN message data register 031 M_DATA031 R W Undefined xxxxn86AH CAN message data register 032 M_DATA032 R W Undefined xxxxn86BH CAN message data r...

Page 96: ...age data register 054 M_DATA054 R W Undefined xxxxn8ADH CAN message data register 055 M_DATA055 R W Undefined xxxxn8AEH CAN message data register 056 M_DATA056 R W Undefined xxxxn8AFH CAN message data...

Page 97: ...essage ID register L07 M_IDL07 R W Undefined xxxxn8F2H CAN message ID register H07 M_IDH07 R W Undefined xxxxn8F4H CAN message configuration register 07 M_CONF07 R W Undefined xxxxn8F5H CAN message st...

Page 98: ...et clear register 09 SC_STAT09 W 0000H xxxxn944H CAN message data length register 10 M_DLC10 R W Undefined xxxxn945H CAN message control register 10 M_CTRL10 R W Undefined xxxxn946H CAN message time s...

Page 99: ...e data register 120 M_DATA120 R W Undefined xxxxn989H CAN message data register 121 M_DATA121 R W Undefined xxxxn98AH CAN message data register 122 M_DATA122 R W Undefined xxxxn98BH CAN message data r...

Page 100: ...age data register 144 M_DATA144 R W Undefined xxxxn9CDH CAN message data register 145 M_DATA145 R W Undefined xxxxn9CEH CAN message data register 146 M_DATA146 R W Undefined xxxxn9CFH CAN message data...

Page 101: ...essage ID register L16 M_IDL16 R W Undefined xxxxnA12H CAN message ID register H16 M_IDH16 R W Undefined xxxxnA14H CAN message configuration register 16 M_CONF16 R W Undefined xxxxnA15H CAN message st...

Page 102: ...set clear register 18 SC_STAT18 W 0000H xxxxnA64H CAN message data length register 19 M_DLC19 R W Undefined xxxxnA65H CAN message control register 19 M_CTRL19 R W Undefined xxxxnA66H CAN message time...

Page 103: ...ge data register 210 M_DATA210 R W Undefined xxxxnAA9H CAN message data register 211 M_DATA211 R W Undefined xxxxnAAAH CAN message data register 212 M_DATA212 R W Undefined xxxxnAABH CAN message data...

Page 104: ...sage data register 234 M_DATA234 R W Undefined xxxxnAEDH CAN message data register 235 M_DATA235 R W Undefined xxxxnAEEH CAN message data register 236 M_DATA236 R W Undefined xxxxnAEFH CAN message dat...

Page 105: ...message ID register L25 M_IDL25 R W Undefined xxxxnB32H CAN message ID register H25 M_IDH25 R W Undefined xxxxnB34H CAN message configuration register 25 M_CONF25 R W Undefined xxxxnB35H CAN message s...

Page 106: ...set clear register 27 SC_STAT27 W 0000H xxxxnB84H CAN message data length register 28 M_DLC28 R W Undefined xxxxnB85H CAN message control register 28 M_CTRL28 R W Undefined xxxxnB86H CAN message time...

Page 107: ...ge data register 300 M_DATA300 R W Undefined xxxxnBC9H CAN message data register 301 M_DATA301 R W Undefined xxxxnBCAH CAN message data register 302 M_DATA302 R W Undefined xxxxnBCBH CAN message data...

Page 108: ...in clock selection register CGCS R W 7F05H xxxxnC18H CAN time stamp count register CGTSC R 0000H CAN message search start register CGMSS W 0000H xxxxnC1AH CAN message search result register CGMSR R 00...

Page 109: ...8 bit units address FFFFF06EH initial value 77H Remark If the timing of changing the flag or count value conflicts with the timing of accessing a register when a register including a status flag that...

Page 110: ...ess data bus AD0 to AD15 PDL0 to PDL15 Port DL PMCDL Address bus A16 to A23 PDH0 to PDH7 Port DH PMCDH Chip select CS0 to CS7 PCS0 to PCS7 Port CS PMCCS Read write control LWR UWR RD ASTB PCT0 PCT1 PC...

Page 111: ...FFFFFFH 8000000H 7FFFFFFH 4000000H 3FFFFFFH 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 MB Block 0 2 MB Block 2 2 MB Block 3 2 MB 64 MB 64 MB Block 5 2 M...

Page 112: ...1 Chip area selection control registers 0 1 CSC0 CSC1 These registers can be read written in 16 bit units and become valid by setting each bit to 1 If different chip select signal outputs are set to...

Page 113: ...ss CS22 CS2 output during block 2 access CS23 CS2 output during block 3 access CS30 to CS33 Note 2 CS40 to CS43 Note 3 CS50 CS5 output during block 7 access CS51 CS5 output during block 6 access CS52...

Page 114: ...ince CS0 has priority over CS2 CS0 is output if the addresses of block 0 and block 1 are accessed If the address of block 3 is accessed both the CS03 and CS23 bits of the CSC0 register are 0 and CS1 i...

Page 115: ...n external memory area other than the one for this initialization routine until the initial setting of the BCT0 and BCT1 registers is complete However it is possible to access external memory areas wh...

Page 116: ...Status Resource Bus Width Instruction Fetch Operand Data Access Internal ROM 32 bits 1Note 1 5 Internal RAM 32 bits 1Note 2 1 On chip peripheral I O 16 bits 5Note 3 Programmable peripheral I O 5Note 3...

Page 117: ...emory areas whose initial settings are complete 2 When the data bus width is specified as 8 bits only the signals shown below become active LWR When accessing SRAM external ROM or external I O write c...

Page 118: ...rting from the lower side 1 Byte access 8 bits a When the data bus width is 16 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n A...

Page 119: ...word data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 2n b When the data bus width is 8 bits little endian 1 Access to even address 2n 2 Acc...

Page 120: ...8 External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 7 0 7 0 Word...

Page 121: ...data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 7 0 7 0 Word data 15...

Page 122: ...Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 2 Access to address 4n 1 1st access 2nd acc...

Page 123: ...3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 4 Access to address 4n 3 1st access 2nd a...

Page 124: ...ipheral function only 2 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than the one for this initialization rou...

Page 125: ...CS4 CS0 AWC CSn signal 15 AHW7 14 ASW7 13 AHW6 12 ASW6 11 AHW5 10 ASW5 9 AHW4 8 ASW4 7 AHW3 6 ASW3 5 AHW2 4 ASW2 3 AHW1 2 ASW1 1 AHW0 0 ASW0 Address FFFFF488H Initial value 0000H CS7 CS6 CS5 CS3 CS2...

Page 126: ...time in the sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as the...

Page 127: ...ystem reset 1 Bus cycle control register BCC This register can be read written in 16 bit units Cautions 1 Idle states cannot be inserted in internal ROM internal RAM on chip peripheral I O or programm...

Page 128: ...al operations of the V850E IA1 continue until the external memory or on chip peripheral I O register is accessed The bus hold state can be known by the HLDAK pin becoming active low level The period f...

Page 129: ...DRQ pin becomes active and the bus hold state is set When the HLDRQ pin becomes inactive after that the HLDAK pin also becomes inactive As a result the bus hold state is cleared and the HALT mode is s...

Page 130: ...cycle operand data access and instruction fetch in that order An instruction fetch may be inserted between a read access and write access during a read modify write access Also an instruction fetch ma...

Page 131: ...ch is valid only in the external memory area In memory block 7 it is terminated when the internal address count value has reached the upper limit of the external memory area 4 10 2 Data space The V850...

Page 132: ...mum of 2 states A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings Data waits can be controlled by WAIT pin input An idle state 1 state can be in...

Page 133: ...5 1 SRAM External ROM External I O Access Timing 1 5 a On a read 1 wait insertion T1 T2 TW T3 Address Data H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Output CSn Ou...

Page 134: ...g 2 5 b On a read 0 wait address setup wait address hold wait state insertion TASW T1 TAHW Address Address T2 T3 Data H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Ou...

Page 135: ...Note H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input Address Note AD0 to AD7 output invalid data when accessed to odd numbered address byte...

Page 136: ...8 bit data bus T1 T2 T3 Address Address Address H CLKOUT Output A16 to A23 Output AD8 to AD15 I O AD0 to AD7 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input DataNote Note AD0 to AD7 ou...

Page 137: ...ed Note 2 Address Undefined T3 TH TH TH TH TI T1 CLKOUT Output A16 to A23 Output AD0 to AD15 I O HLDAK Output ASTB Output RD Output UWR LWR Output CSn Output HLDRQ Input WAIT Input Undefined Notes 1 O...

Page 138: ...ulse unit and A D converter or software triggers memory refers to internal RAM or external memory 6 1 Features 4 independent DMA channels Transfer units 8 16 bits Maximum transfer count 65 536 2 16 Tr...

Page 139: ...ontrol Channel control DMAC V850E IA1 Bus interface External bus External RAM External ROM External I O DMA source address register DSAnH DSAnL DMA transfer count register DBCn DMA channel control reg...

Page 140: ...ource address registers 0H to 3H DSA0H to DSA3H These registers can be read written in 16 bit units Be sure to set bits 12 to 14 to 0 If they are set to 1 the operation is not guaranteed Caution When...

Page 141: ...7 6 SA6 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0 SA15 DSA1L FFFFF088H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA2L FFFFF090H Undefined SA14 SA13 SA12 SA11 SA10 SA9...

Page 142: ...s registers 0H to 3H DDA0H to DDA3H These registers can be read written in 16 bit units Be sure to set bits 12 to 14 to 0 If they are set to 1 the operation is not guaranteed Caution When setting an a...

Page 143: ...6 DA6 5 DA5 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0 DA15 DDA1L FFFFF08CH Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA2L FFFFF094H Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA...

Page 144: ...ransfer Transfer is terminated if a borrow occurs These registers can be read written in 16 bit units Remark If the DBCn register is read after a terminal count has occurred during DMA transfer withou...

Page 145: ...f the following periods the operation is not guaranteed if set at another timing Time from system reset to the start of the first DMA transfer Time from DMA transfer end after terminal count to the st...

Page 146: ...0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 7 6 SAD1 SAD0 Sets the count direction of the destination address for DMA channel n n 0 to 3 DAD1 DAD0 Count Direction 0 0 Increment 0 1 Decrement 1 0 Fi...

Page 147: ...guaranteed if set at another timing Time from system reset to the start of the first DMA transfer Time from DMA transfer end after terminal count to the start of the next DMA transfer Time from the fo...

Page 148: ...DMA transfer request can be accepted even when the TCn bit is not read When the next DMA transfer request is the setting of the STGn bit to 1 software DMA the DMA transfer request can be accepted by r...

Page 149: ...xt forcible interruption by NMI input or until the system is reset 6 3 7 DMA restart register DRST The ENn bit of the DRST register and the Enn bit of the DCHCn register are linked to each other n 0 t...

Page 150: ...FC12 IFC11 IFC10 FFFFF812H 00H 7 DTFR2 6 5 4 3 2 1 0 DF2 0 IFC25 IFC24 IFC23 IFC22 IFC21 IFC20 FFFFF814H 00H 7 DTFR3 6 5 4 3 2 1 0 DF3 0 IFC35 IFC34 IFC33 IFC32 IFC31 IFC30 FFFFF816H 00H Bit Position...

Page 151: ...CC20 0 1 1 0 0 1 INTP21 INTCC21 0 1 1 0 1 0 INTP22 INTCC22 0 1 1 0 1 1 INTP23 INTCC23 0 1 1 1 0 0 INTP24 INTCC24 0 1 1 1 0 1 INTP25 INTCC25 0 1 1 1 1 0 INTTM3 0 1 1 1 1 1 INTP30 INTCC30 1 0 0 0 0 0 IN...

Page 152: ...responds to the last state of a read operation in the two cycle transfer mode or to a wait state In the last T2R state read data is sampled After entering the last T2R state the bus invariably enters...

Page 153: ...are initialized n 0 to 3 After entering the TE state the bus invariably enters the TI state 6 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA...

Page 154: ...leased for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figures 6 2 to 6 5 show examples of single transfer Figure 6 2 Single Transfer Example 1 CPU DMA3 CPU...

Page 155: ...Note Note Internal signal Internal signal Note The bus is always released Figure 6 5 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within...

Page 156: ...used for the single step transfer Figure 6 6 Single Step Transfer Example 1 DMA1 CPU CPU CPU CPU CPU CPU CPU CPU DMA1 CPU CPU DMA1 DMA1 CPU DMARQ1 CPU CPU DMA channel 1 terminal count Note Note Note...

Page 157: ...les a read cycle source to DMAC and a write cycle DMAC to destination In the first cycle the source address is output and reading is performed from the source to the DMAC In the second cycle the desti...

Page 158: ...r if the data bus width of the transfer source and that of the transfer destination are different the operation becomes as follows If the object of the DMA transfer is an on chip peripheral I O regist...

Page 159: ...the higher priority DMA transfer request is acknowledged Caution Do not start more than one DMA channel using the same start factor If more than one DMA channel is started a lower priority DMA channel...

Page 160: ...DMA transfer The settings made are incorporated in only the master register and not in the slave register the slave register maintains the value set for the next DMA transfer However the contents of t...

Page 161: ...interrupt request is issued from the on chip peripheral I O that is set in the DTFRn register DMA transfer starts n 0 to 3 Enn bit 1 TCn bit 0 6 11 Forcible Interruption DMA transfer can be forcibly i...

Page 162: ...s 1 Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects external memory internal RAM or on chip peripheral I O during DMA...

Page 163: ...DMA transfer for the internal RAM Execution of a bit manipulation instruction SET1 CLR1 or NOT1 allocated to the internal RAM or data access instruction to a misaligned address Prevent deadlock using...

Page 164: ...opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servicing starts after no fewer than 4 system clocks 100 ns 50 MHz followi...

Page 165: ...120H nextPC Interrupt INTTM01 TM0IC1 TM01 underflow RPU 11 0130H 00000130H nextPC Interrupt INTCM013 CM03IC1 CM013 match RPU 12 0140H 00000140H nextPC Interrupt INTP100 INTCC100 CC10IC0 INTP100 pin CC...

Page 166: ...nterrupt INTCSI1 CSIIC1 CSI1 transmission reception complete SIO 42 0320H 00000320H nextPC Interrupt INTSR0 SRIC0 UART0 reception complete SIO 43 0330H 00000330H nextPC Interrupt INTST0 STIC0 UART0 tr...

Page 167: ...external interrupt mode register 0 INTM0 is detected on the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed PSW NP 1 the acknowledgement of anot...

Page 168: ...alfword FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The serv...

Page 169: ...est PSW NP 1 NMI request held pending regardless of the value of the NP bit of the PSW Pending NMI request processed b If a new NMI request is generated twice while an NMI service program is being exe...

Page 170: ...s 1 2 Transfers control back to the address of the restored PC and PSW Figure 7 3 illustrates how the RETI instruction is processed Figure 7 3 RETI Instruction Processing PSW EP RETI instruction PSW N...

Page 171: ...0 0 0 0 0 0 Bit Position Bit Name Function 7 NP Indicates whether NMI interrupt servicing is in progress 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 7 2 4 Edge detection fun...

Page 172: ...a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the sam...

Page 173: ...hat of other interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID Corresponding bit of ISPRNote PC restored PC PSW exception code 0...

Page 174: ...nd PSW Figure 7 5 illustrates the processing of the RETI instruction Figure 7 5 RETI Instruction Processing Note For the ISPR register see 7 3 6 In service priority register ISPR Caution When the PSW...

Page 175: ...ority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level b...

Page 176: ...pt request d is higher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e...

Page 177: ...Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending b...

Page 178: ...ervicing of interrupt request a Interrupt requests b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first according to the...

Page 179: ...Name Function 7 xxIFn This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxlFn is reset automatically by the hardware if an interrupt request is ackn...

Page 180: ...FFFFF134H CC11IC1 CC11IF1 CC11MK1 0 0 0 CC11PR12 CC11PR11 CC11PR10 FFFFF136H CM11IC0 CM11IF0 CM11MK0 0 0 0 CM11PR02 CM11PR01 CM11PR00 FFFFF138H CM11IC1 CM11IF1 CM11MK1 0 0 0 CM11PR12 CM11PR11 CM11PR10...

Page 181: ...K0 0 0 0 SRPR02 SRPR01 SRPR00 FFFFF168H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF16AH SEIC0 SEIF0 SEMK0 0 0 0 SEPR02 SEPR01 SEPR00 FFFFF16CH SRIC1 SRIF1 SRMK1 0 0 0 SRPR12 SRPR11 SRPR10 FFFFF...

Page 182: ...15 CM10MK0 7 DETMK0 IMR0 14 CC10MK1 6 P0MK6 13 CC10MK0 5 P0MK5 12 CM03MK1 4 P0MK4 11 TM0MK1 3 P0MK3 10 CM03MK0 2 P0MK2 9 TM0MK0 1 P0MK1 8 DETMK1 0 P0MK0 Address FFFFF100H Initial value FFFFH 15 CC3MK1...

Page 183: ...ned from non maskable interrupt servicing or exception processing This register is read only in 8 bit or 1 bit units Caution In the interrupt enabled EI state if an interrupt is acknowledged during th...

Page 184: ...rrupt servicing is enabled or disabled 0 Maskable interrupt request acknowledgement enabled 1 Maskable interrupt request acknowledgement disabled pending This bit is set to 1 by the DI instruction and...

Page 185: ...ection register SESC and TM2 input filter mode registers 0 to 5 FEM0 to FEM5 1 External interrupt mode registers 1 2 INTM1 INTM2 These registers specify the valid edge for external interrupt requests...

Page 186: ...DTRG1 INTP2 ADTRG0 INTP1 INTP0 7 0 INTM2 6 0 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 Address FFFFF884H Initial value 00H INTP6 INTP5 INTP4 Bit Position Bit Name Function Specifies the valid edge of...

Page 187: ...ntly for each pin rising edge falling edge or both rising and falling edges These registers can be read written in 8 bit or 1 bit units Cautions 1 The bits of the SESA1n register cannot be changed dur...

Page 188: ...id only in UDC mode ANote 1 and UDC mode BNote 1 2 If TM1n operation has been specified in mode 4Note 2 the valid edge specification TESUDn1 and TESUDn0 bits for the TIUD1n and TCUD1n pins is invalid...

Page 189: ...of the CSL1n register INTP1n1 INTP1n0 IES1n11 IES1n10 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 3 2 IES1n11 IES1n10 Specifies the valid edge...

Page 190: ...INTP30 and TO3 INTP31 pins as INTP30 and INTP31 even if not using timer 3 2 Before setting the INTP30 INTP31 TCLR3 and TI3 pins to the trigger mode set the PMC2 register If the PMC2 register is set a...

Page 191: ...edge can be specified independently for each pin rising edge falling edge or both rising and falling edges These registers can be read written in 8 bit or 1 bit units Cautions 1 The STFTE bit of time...

Page 192: ...4 1 TMS014 0 TMS004 Address FFFFF634H Initial value 00H INTP24 7 DFEN05 FEM5 6 0 5 0 4 0 3 EDGE015 2 EDGE005 1 TMS015 0 TMS005 Address FFFFF635H Initial value 00H INTP25 Bit Position Bit Name Function...

Page 193: ...Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers Set the TMS01m and TMS00m bits of the FEMm register to 00B or 01B All other settings are p...

Page 194: ...terrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 8 illustrates the...

Page 195: ...o the address of the restored PC and PSW Figure 7 9 illustrates the processing of the RETI instruction Figure 7 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original...

Page 196: ...to indicate that exception processing is in progress It is set when an exception occurs 31 0 PSW Initial value 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 197: ...on trap is generated when an instruction applicable to this illegal instruction is executed 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to Arbitrary Caution Since it is possible to...

Page 198: ...ion trap is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and...

Page 199: ...erforms the following processing 1 Operation 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding...

Page 200: ...the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restor...

Page 201: ...rvicing control is executed when interrupts are enabled ID 0 Thus if multiple interrupts are executed it is necessary for interrupts to be enabled ID 0 even during an interrupt servicing routine If a...

Page 202: ...upt request After system reset an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits The priority order of maskable interrupts is as fol...

Page 203: ...100 INTP30 INTP101 INTP31 INTP110 INTP111 Condition Mini mum 4 4 analog delay time 4 digital noise filter 4 Note 1 digital noise filter Maxi mum 7Note 2 7 analog delay time 7 digital noise filter 7 No...

Page 204: ...uction and the next instruction interrupt is held pending The interrupt request non sampling instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The load store...

Page 205: ...iplier function using a phase locked loop PLL synthesizer Clock sources Oscillation by connecting a resonator External clock Power saving modes HALT mode IDLE mode Software STOP mode Internal system c...

Page 206: ...ct mode an external clock must be input an external resonator should not be connected 8 3 2 PLL mode In PLL mode an external resonator is connected or external clock is input and multiplied by the PLL...

Page 207: ...ters that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution This register can be written only in 8 bit units when it is r...

Page 208: ...X1 and X2 pins 0 A resonator is connected to the X1 and X2 pins 1 An external clock is connected to the X1 pin When CESEL 1 the oscillator feedback loop is disconnected to prevent current leak in sof...

Page 209: ...to PSW rY Value returned to PSW No special sequence is required to read the specific register Cautions 1 If an interrupt is acknowledged between the issuing of data to the PHCMD 3 and writing to the...

Page 210: ...7 6 5 4 3 2 1 0 Address Initial value PHS 0 0 0 0 0 0 0 PRERR FFFFF802H 00H Bit Position Bit Name Function 0 PRERR Protection error 0 Protection error does not occur 1 Protection error occurs The oper...

Page 211: ...me Function 0 LOCK This is a read only flag that indicates the PLL state This flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset 0 Indicates that t...

Page 212: ...TOP mode and HALT mode in relation to the clock stabilization time and current consumption It is used for situations in which a low current consumption mode is to be used and the clock stabilization t...

Page 213: ...d use Figure 8 1 Power Save Mode State Transition Diagram Note INTPn n 0 to 6 20 to 25 However when a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25 the s...

Page 214: ...Mode Oscillator PLL Synthesizer Clock Supply to Peripheral I O Clock Supply to CPU Normal operation HALT mode IDLE mode Oscillation with resonator Software STOP mode Normal operation HALT mode IDLE mo...

Page 215: ...OP mode 2 Command register PRCMD This is an 8 bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application system is n...

Page 216: ...maskable interrupt INTPn n 0 to 6 20 to 25 30 31 100 101 110 111 0 Enables maskable interrupt cancellation 1 Disables maskable interrupt cancellation 1 STB Indicates the standby mode status If 1 is w...

Page 217: ...ot acknowledge interrupts This coding is made on assumption that 3 and 4 above are executed by the program with consecutive store instructions If another instruction is set between 3 and 4 the above s...

Page 218: ...nts of all registers internal RAM and ports are maintained in the state they were in immediately before HALT mode began Also operation continues for all on chip peripheral I O units other than ports t...

Page 219: ...r priority than that of the interrupt request that is currently being serviced HALT mode is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pen...

Page 220: ...ode program execution is stopped and the contents of all registers internal RAM and ports are maintained in the state they were in immediately before execution stopped The operation of on chip periphe...

Page 221: ...maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently being serviced IDLE mode is released and the newly generated interrupt request is...

Page 222: ...e STOP mode the contents of all registers internal RAM and ports are maintained in the state they were in immediately before software STOP mode began The operation of all on chip peripheral I O units...

Page 223: ...e is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt request including non maskable interrupt requests is generated...

Page 224: ...rocessing branches to the NMI interrupt or maskable interrupt INTPn handler address Oscillation waveform X2 Set software STOP mode Oscillator is stopped CLKOUT output Internal main clock STOP state NM...

Page 225: ...llation stabilization time secured by RESET RESET input Undefined CLKOUT output Undefined 8 6 2 Time base counter TBC The time base counter TBC is used to secure the oscillator s oscillation stabiliza...

Page 226: ...riangular wave PWM mode 2 sawtooth wave Interrupt culling function Culling ratios 1 1 1 2 1 4 1 8 1 16 Forcible 3 phase PWM output stop function 3 phase PWM output can be forcibly stopped by inputting...

Page 227: ...K 2 types set fCLK to 40 MHz or less fXX and fXX 2 can be selected Prescaler division ratio The following division ratios can be selected according to the base clock fCLK Base Clock fCLK Division Rati...

Page 228: ...DTRRn 6 TO0n0 U phase TO0n1 U phase TO0n2 V phase TO0n3 V phase TO0n4 W phase TO0n5 W phase Selector Output control by external input ESOn TM0n timer operation Underflow Underflow Underflow ALVUB ALVV...

Page 229: ...4 W phase TO0n5 W phase Underflow Underflow Underflow fXX 2 Selector Clear Output control by external input ESOn TM0n timer operation fCLK R S R S R S R S R S R S ALVUB ALVVB ALVWB ALVTO fXX Remarks 1...

Page 230: ...0n3 CM0n3 match PWM mode 2 sawtooth wave only Immediately after overflow or underflow The TM0n timer has 3 operation modes shown in Table 9 1 The operation mode is selected with timer control registe...

Page 231: ...timer count operation disabled an inverted signal without dead time is output to TO0n0 and TO0n1 TO0n2 and TO0n3 and TO0n4 and TO0n5 3 Dead time timer reload registers 0 1 DTRR0 DTRR1 DTRRn register...

Page 232: ...esponding to each buffer register when an interrupt signal INTCM0n3 INTTM0n is generated BFCMn0 to BFCMn2 can be read written in 16 bit units Caution The set values of the BFCMn0 to BFCMn2 registers a...

Page 233: ...to the CM0n3 register in the following timing n 0 1 When TM0CEn bit of TMC0n register 0 Transfer at next operation timing after writing to BFCMn3 register When TM0CEn bit of TMC0n register 1 Value of...

Page 234: ...bit units Caution Always set this register before using the timer 7 0 PRM01 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM1 Address FFFFF5D0H Initial value 00H Bit Position Bit Name Function 0 PRM1 Specifies the base...

Page 235: ...0 15 TM0CE1 1 MOD01 0 MOD00 TMC01 Address FFFFF5BAH Initial value 0508H Bit Position Bit Name Function 15 TM0CEn Specifies the operation of TM0n 0 Count disabled stops after all count values are clear...

Page 236: ...e see Figure 9 5 Specifies the count clock for TM0n PRM02 PRM01 PRM00 Count Clock 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 16 1 0 1 fCLK 32 Other than above Setting prohibited 10 t...

Page 237: ...triangular wave INTTM0n 1 PWM mode 1 asymmetric triangular wave INTTM0n INTCM0n3 1 PWM mode 2 sawtooth wave INTCM0n3 3 BFTEN When the BFTEN bit 1 the values of the BFCMn0 to BFCMn2 registers are tran...

Page 238: ...mode 2 sawtooth wave Up INTCM0n3 INTCM0n3 INTCM0n3 1 1 Setting prohibited 1 0 MOD01 MOD00 Caution Changing the value of the MOD01 MOD00 bits during TM0n operation TM0CEn bit 1 is prohibited Remark n 0...

Page 239: ...b PWM mode 1 asymmetric triangular wave CM0n3 TM0n count value 0000H CUL02 to CUL00 INTTM0n occurrence INTCM0n3 occurrence Interrupt request INTCM0n3 occurrence INTCM0n3 occurrence INTCM0n3 occurrence...

Page 240: ...INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 001 010 000 Interrupt culling 1 2 cycle Interrupt culling 1 4 cycle Interrupt culling 1 1 cycle TM0CEn bit TM0n count value CUL02 to CUL00 bits STINTn 1 INT...

Page 241: ...n bit Cautions 1 If the level is set for the ESOn pin input level TOMR register TOEDG1 bit 1 TOEDG0 bit 0 or 1 the output disabled state is not released TOSTAn bit 1 even if 1 is written to the TORSn...

Page 242: ...using the internal bus during servicing of these interrupts Add one of the following processing items during the TOMRn register write routine Prior to write access to the TOMRn register disable acknow...

Page 243: ...pin output stop through ESOn pin input 0 Enables ESOn pin input 1 Disables ESOn pin input Cautions 1 The output stop status can be released by writing 1 to the TORSn bit of the TUC0n register The oper...

Page 244: ...n PWM mode 0 symmetric triangular waves are shown below Figure 9 7 Output Waveforms of TO000 and TO001 in PWM Mode 0 Symmetric Triangular Waves Without Dead Time TM0CED0 Bit 1 a TOMR0 register value 8...

Page 245: ...0CED0 Bit 0 a TOMR0 register value 80H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period b TOMR0 register value 00H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time perio...

Page 246: ...tructions Bit manipulation instruction SET1 CLR1 NOT1 instructions Description example 1 MOV 0x04 r10 2 ST B r10 SPECn r0 3 ST B r10 TOMRn r0 Remark n 0 1 To read the TOMRn register no special sequenc...

Page 247: ...O0n4 output status is high impedance 1 TO0n4 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin 3 OE11n Specifies output status of TO0n3 pin 0 TO...

Page 248: ...during TM0n operation TM0CEn bit 1 INTTM0n and INTCM0n3 interrupts Continue occurring at each timing in accordance with timer and compare operations TO0n0 to TO0n5 outputs Software output has priority...

Page 249: ...he same way as during normal timer operation 1 VPORTn Specifies the TO0n2 V phase TO0n3 V phase pin output value Caution If the VPORTn bit setting value is changed when TORTOn 1 the dead time setting...

Page 250: ...0CEn 1 timer operation enabled TORTOn 1 software output enabled to TM0CEn 1 timer operation enabled TORTOn 0 software output disabled the TO0n0 to TO0n5 pins continue to perform software output until...

Page 251: ...Note 2 Note 2 Note 1 Note 4 Notes 1 F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0...

Page 252: ...h during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 1 to 0 whi...

Page 253: ...3 Notes 1 F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the...

Page 254: ...oftware Output Waveforms of TO000 and TO001 Without Dead Time TM0CED0 1 a TOMR0 register value 80H UPORT0 1 TO000 TO001 UPORT0 0 b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 c TOMR0 regist...

Page 255: ...0 a TOMR0 register value 80H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period c TOMR0 register...

Page 256: ...ORT0 1 UPORT0 0 UPORT0 1 TO000 TO001 Dead time period Dead time period The following table shows the output status of external pulse output in the case of TO0n0 Table 9 2 Output Status of External Pul...

Page 257: ...diately after write to the SPECn register any data can be written write processing to the TOMRn register is not performed normally Normally 0000H is read The SPECn register can be read written in 16 b...

Page 258: ...match interrupt INTCM0n3 is generated The count clock to TM0n can be selected from among 6 internal clocks with the TMC0n register If the TM0n has been set as an up down timer an underflow interrupt...

Page 259: ...lock is set with the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set reset timing of the F F used in the PWM cycle in BFCMn0 to BFCMn2 d...

Page 260: ...ation of the INTTM0n interrupt Furthermore software processing is started up and calculation performed and set reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and t...

Page 261: ...nXup Set value of CM0n0 to CM0n2 while TM0n is counting up CM0nXdown Set value of CM0n0 to CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance...

Page 262: ...O0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx Interrupt request 0000H Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1 and...

Page 263: ...Symmetric Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 o...

Page 264: ...n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins...

Page 265: ...O0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high...

Page 266: ...O0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 0000H 0000H b c a 0000H 0000H Note b CM0n3 CM0n3 a a CM0nx match CM0nx match CM0nx match CM0n3 b b t t t t t t INTTM0n INTTM0n INTTM0n INTTM0n CM0nx m...

Page 267: ...ck is set with the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set timing of the F F used in the PWM cycle in BFCMn0 to BFCMn2 d Clear 0...

Page 268: ...the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set CM0n0 to CM0n2 match detection during TM0n up count operation Reset CM0n0 to CM...

Page 269: ...o CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until...

Page 270: ...n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1...

Page 271: ...Asymmetric Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 o...

Page 272: ...LK Base clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase si...

Page 273: ...2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outp...

Page 274: ...st Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b b b b b c d e Note CM0n3 CM0n3 a CM0nx match CM0n3 c d CM0nx match CM0nx match a b b b b b c d e t t t t INTTM0n INTCM0n3 INTCM0n...

Page 275: ...ative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b 0000H 0000H 0000H a b a 0000H 0000H 0000H INTCM0n3 INTCM0n3 INTTM0n Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK...

Page 276: ...O0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b c d e Note CM0n3 CM0n3 a c CM0nx match CM0n3 d b CM0nx match CM0nx match 0000H 0000H 0000H 0000H d e t t t t t t INTTM0n INTCM0n3 INTCM0n3 INTTM0n INTTM0n...

Page 277: ...0000H 0000H INTCM0n3 INTCM0n3 Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case Since TM0n CM0nx 0000H match is detected during up cou...

Page 278: ...ase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b c d Note CM0n3 CM0n3 a CM0nx match CM0n3 b c CM0nx match CM0nx match a 0000H 0000H 0000H 0000H 0000H b d t t t t INTTM0n INTCM0n3 INTCM0n3 INTC...

Page 279: ...4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case Since TM0n and CM0nx match is detected during count down of TM0n when BFCMnx CM0n3 has been set the F F remains...

Page 280: ...h bit BFTEN c Set the initial values i Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register ii Set the cycle width of the PWM cycle in BFCMn3 PWM cycle BFCMn3 value 1 TM0...

Page 281: ...calculation performed and reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of...

Page 282: ...0n0 to TO0n5 pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until the TM0n is started TO0n0 TO0n2 TO0n4 When low active High le...

Page 283: ...n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TM...

Page 284: ...TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n1 CM0n0 CM0n3 CM0n2 CM0n1 CM0n0 Without dead time With...

Page 285: ...clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0...

Page 286: ...O0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 a b b c d a b b c Note CM0n3 CM0n3 a c CM0nx match CM0nx match CM0n3 t t t t t INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Note F F is reset upon occurrence o...

Page 287: ...n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit a Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead tim...

Page 288: ...ue Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H Note INTCM0n3 INTCM0n3 INTCM0n3 a Note Set by rising edge of TM0CEn bit Remarks 1 n...

Page 289: ...6 shows the timing from write of the TM0CEn bit of the TMC0n register until the TM0n timer starts operating Figure 9 36 TM0CEn Bit Write and TM0n Timer Operation Timing Register write timing 0000H 000...

Page 290: ...clock fCLK 0002H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H CM0n3 TM0n INTCM0n3 INTTM0n fCLK b When count clock fCLK 4 000...

Page 291: ...00H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H CM0n3 TM0n INTCM0n3 fCLK b When count clock fCLK 4 0002H 0000H 0001H 0002H 0000H 0001H CM0n3 TM0n INTCM0n3 fCLK Cautions 1 INTCM0n...

Page 292: ...other than 1 1 and count operation is started the interrupt output order differs according to the setting of the STINTn bit when counting starts Figure 9 39 Interrupt Generation Timing in PWM Mode 0...

Page 293: ...ng Ratio of 1 2 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 INTTM0n...

Page 294: ...1 1 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1...

Page 295: ...1 2 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1...

Page 296: ...0008H 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0002H FFFFH FFFFH FFFFH 0001H 0000H 0002H 0001H 0000H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0nx TM0n DTMnx Mat...

Page 297: ...0000H FFFFH FFFFH 0001H 0000H 0002H 0001H 0000H 0002H FFFFH 0001H 0000H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H CM0nx TM0n DTMnx Match signal F F TO0n0 TO0n2 TO0n4 TO0...

Page 298: ...2 types 2 channels Compare match interrupt request 2 types 2 channels Capture request signal 2 types 2 channels The TM1n value can be latched using the valid edge of the INTP1n0 INTP1n1 pins correspo...

Page 299: ...of the pulses PWM output function In the general purpose timer mode 16 bit resolution PWM output can be output from the TO1n pin Timer clear The following timer clear operations are performed accordin...

Page 300: ...write INTCM101 CC100 Read write INTCC100 INTP100 CC101 Read write INTCC101 INTP100 or INTP101 TM11 Read write CM110 Read write INTCM110 CM111 Read write INTCM111 CC110 Read write INTCC110 INTP110 Time...

Page 301: ...TM1n TM10 clear controller CC1n1 CC1n0 MSEL CMD TM1UBDn ENMD ALVT10 RLEN TM1UDFn TM1OVFn Clear TCLR SELCLK fCLK Internal bus Internal bus TCLR1n INTP1n1 TCUD1n INTP1n0 TIUD1n fXX 4 fXX 2 INTP1n0 INTC...

Page 302: ...ion Correct usage example Incorrect usage example TM10 read TM10 read TM11 read TM10 read TM10 read TM11 read TM11 read TM11 read 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 TM10 Address FFFFF5E0H Initial v...

Page 303: ...ral purpose mode and it counts up down when the operation mode is the UDC mode The conditions for clearing the TM1n are classified as follows depending on the operation mode Table 9 5 Timer 1 TM1n Cle...

Page 304: ...9 10 11 15 1 0 CM100 Address FFFFF5E2H Initial value 0000H 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CM110 Address FFFFF602H Initial value 0000H 3 Compare registers 101 111 CM101 CM111 CM1n1 is a 16 bit...

Page 305: ...rst and the second read operation Correct usage example Incorrect usage example CC100 read CC100 read CC110 read CC100 read CC100 read CC110 read CC110 read CC110 read Remark n 0 1 14 13 12 2 3 4 5 6...

Page 306: ...ect usage example CC101 read CC101 read CC111 read CC101 read CC101 read CC111 read CC111 read CC111 read Remark n 0 1 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC101 Address FFFFF5E8H Initial value 0000H...

Page 307: ...of timer 1 TM1n and timer 2 TM2n This register can be read written in 8 bit or 1 bit units Caution Always set this register before using the timers 1 and 2 7 0 PRM02 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM2 Add...

Page 308: ...count 3 TOE10 Specifies timer output TO1n enable 0 Timer output disabled 1 Timer output enabled Caution When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE10 bi...

Page 309: ...count operation 3 RLEN Enables disables transfer from CM1n0 to TM1n 0 Disable transfer 1 Enable transfer Cautions 1 When RLEN 1 the value set to CM1n0 is transferred to TM1n upon occurrence of TM1n un...

Page 310: ...0 set value 1 1 Don t clear 1 0 CLR1 CLR0 Cautions 1 Clearing by match of the TM1n count value and CM1n0 set value is valid only during TM1n up count operation TM1n is not cleared during TM1n down cou...

Page 311: ...or 1 bit units Caution Overwriting the CCRn register during TM1n operation TM1CEn bit 1 is prohibited 7 0 CCR0 6 0 5 0 4 0 3 0 2 0 1 CMS1 0 CMS0 Address FFFFF5EAH Initial value 00H 7 0 CCR1 6 0 5 0 4...

Page 312: ...1 TMC10 TMC11 even when timer 1 is not used and the TCUD10 INTP100 TCLR10 INTP101 TCUD11 INTP110 and TCLR11 INTP111 pins are used as INTP100 INTP101 INTP110 and INTP111 1 2 7 TESUD01 SESA10 6 TESUD00...

Page 313: ...falling edge of TCLR1n 10 TM1n cleared status held while TCLR1n input is low level 11 TM1n cleared status held while TCLR1n input is high level Caution The set values of the CESUDn1 and CESUDn0 bits a...

Page 314: ...ted 3 When TM1n is in mode 4 specification of the valid edge for the TIUD1n and TCUD1n pins is invalid 7 0 PRM10 6 0 5 0 4 0 3 0 2 PRM12 1 PRM11 0 PRM10 Address FFFFF5EEH Initial value 07H 7 0 PRM11 6...

Page 315: ...register 1 The TM1n count sources in the UDC mode are as follows Operation Mode TM1n Operation Mode 1 Down count when TCUD1n high level Up count when TCUD1n low level Mode 2 Up count upon detection of...

Page 316: ...0 No TM1n count underflow 1 TM1n count underflow Caution The TM1UDFn bit is cleared to 0 upon completion of read access to the STATUSn register from the CPU 1 TM1OVFn TM1n overflow flag 0 No TM1n cou...

Page 317: ...2 0 1 0 0 CSL0 Address FFFFF5F6H Initial value 00H Bit Position Bit Name Function 0 CSL0 Specifies capture input to CC101 0 INTP101 1 INTP100 9 CC111 capture input selection register CSL11 The CSL11...

Page 318: ...into two modes according to the TM1n clear conditions UDC mode A TUMn register s CMD bit 1 MSEL bit 0 The TM1n clear source can be selected as only external clear input TCLR1n a match signal between...

Page 319: ...ee running operation TM1n performs full count operation from 0000H to FFFFH and after the TM1OVFn bit of the STATUSn register is set to 1 TM1n is cleared and resumes counting The free running cycle ca...

Page 320: ...CC1n1 are capture compare registers Which of these registers is used is specified with capture compare control register n CCRn 2 n 0 1 The valid edge of the capture trigger is specified by signal edg...

Page 321: ...ue of this register matches the value of TM1n the INTCM1n0 interrupt is generated Compare match is saved by hardware and TM1n is cleared at the next count clock after the match The CM1n1 register is a...

Page 322: ...UD1n input and both edges of TCUD1n input The UDC mode is further divided into two modes according to the TM1n clear conditions count operation is performed only with TIUD1n TCUD1n input in both modes...

Page 323: ...ster setting i Mode 1 PRM12 bit 1 PRM11 bit 0 PRM10 bit 0 In mode 1 the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin...

Page 324: ...RM11 bit 0 PRM10 bit 1 The count conditions in mode 2 are as follows TM1n up count upon detection of valid edge of TIUD1n pin TM1n down count upon detection of valid edge of TCUD1n pin Caution If the...

Page 325: ...M1n counts down when the valid edge is input to the TIUD1n pin If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is high TM1n counts up when the valid edge is input to the TIUD...

Page 326: ...es of the two signals input to the TIUD1n and TCUD1n pins Therefore TM1n counts four times per cycle of an input signal 4 count Figure 9 53 Mode 4 TIUD1n TCUD1n TM1n 0004H 0003H 0006H 0005H 0008H 0007...

Page 327: ...transfer operation ii Transfer operation The operations at the next count clock after the count value of TM1n becomes 0000H during TM1n count down operation are as follows In case of down count opera...

Page 328: ...CM1n0 INTCM1n1 INTCC1n0 Note INTCC1n1 Note is output Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode iv Capture function TM1n connects two capture comp...

Page 329: ...lue CM1n1 set value TM1n count value Clear TM1n not cleared if count clock counts down following match Clear TM1n not cleared if count clock counts up following match Remark n 0 1 ii Compare function...

Page 330: ...ion upon Match with CM1n0 During TM1n Up Count Operation Count clock rising edge set as valid edge CM1n0 FFFEH Clear TM1n Not clear TM1n TM1n FFFFH 0000H FFFEH 0001H FFFDH FFFFH Up count Up count Down...

Page 331: ...on Compare Match Count clock rising edge set as valid edge CM1n0 FFFEH TM1n FFFFH 0000H FFFEH 0001H FFFDH FFFFH Up count Up count Down count Clear TM1n Not clear TM1n Caution The operations at the nex...

Page 332: ...set as valid edge CM1n0 0001H Transfer operation is performed Transfer operation is not performed TM1n 0000H FFFFH 0001H FFFEH 0002H FFFFH Down count Down count Up count Caution The count operations a...

Page 333: ...Purpose Timer Mode and Count Clock Set to fCLK 2 Count clock fCLK CM1n1 0007H TM1n Internal match signal INTCM1n1 0008H 000BH 0009H 0009H 000AH Remarks 1 n 0 1 2 fCLK Base clock An interrupt signal su...

Page 334: ...counter TM20 TM21 2 channels Bit length Timer 2 registers TM20 TM21 16 bits During cascade operation 32 bits higher 16 bits TM21 lower 16 bits TM20 Capture compare register In 16 bit mode 6 In 32 bit...

Page 335: ...put Note 2 Timer counter clear operation can be performed with the TCLR2 pin input signal Up down count control Notes 3 5 with external pin input Note 2 Up down count operation in the compare mode can...

Page 336: ...write INTCC23 INTP23 INTP22 Buffer Note 4 CVSE40 Read write INTCC24 INTP24 INTP21 Buffer Note 4 CVSE50 Read write INTCC25 INTP25 INTP20 CVPE40 Read INTCC24 INTP24 INTP21 Note 4 CVPE30 Read INTCC23 IN...

Page 337: ...n n 3 4 y y 1 2 when m 12 y 3 4 when m 34 The following shows the output level sources during timer output Table 9 10 Output Level Sources During Timer Output TO2n Toggle Mode 0 OTMEn1 OTMEn0 00 Toggl...

Page 338: ...2B ED2 Sub channel 3 CVSE30 16 bit CVPE30 16 bit S T RA RB RN Output circuit 4 CVSE00 16 bit TM20 16 bit INTCC20 INTCC21 INTCC22 INTCC23 INTCC24 INTCC25 INTTM20 TO21 TO22 TO23 TO24 INTTM21 CVSE50 16 b...

Page 339: ...h signal input sub channel 0 5 RA TM20 zero count signal input reset signal of output circuit RB TM21 zero count signal input reset signal of output circuit RELOAD2A TM20 zero count signal input gener...

Page 340: ...e can be controlled with external pin TCLR2 Counter up down and clear operation control method can be set by software Stop upon occurrence of count value 0 and count operation start stop can be contro...

Page 341: ...e value of TB1En TB0En bits of CMSEm0 register 11B this register captures the contents of TM21 higher 16 bits This register is read only in 16 bit units Caution When the BFEEn bit 1 a compare match oc...

Page 342: ...en the BFEEn bit 1 a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset TM2x timer counter selected by T...

Page 343: ...STOPTE0 The STOPTE0 register is used to stop the operation clock input to timer 2 This register can be read written in 16 bit units When the higher 8 bits of the STOPTE0 register are used as the STOP...

Page 344: ...Address FFFFF642H Initial value 0000H Bit Position Bit Name Function Specifies the valid edge of the TM2n internal count clock TCOUNTEn signal TESnE1 TESnE0 Valid Edge 0 0 Falling edge 0 1 Rising edge...

Page 345: ...used as the SESE0H register and the lower 8 bits are used as the SESE0L register they can be read written in 8 bit or 1 bit units 14 0 13 0 12 0 2 IESE10 3 IESE11 4 IESE20 5 IESE21 6 IESE30 7 IESE31 8...

Page 346: ...red until the external clock TI2 is input 3 The ECREn bit and the ECEEn bit cannot be set to 1 4 If the ECEEn bit is set to 1 and the ECREn bit is set to 0 a down count operation cannot be performed 5...

Page 347: ...COUNTE1 is selected as the count of TM21 When CASE1 1 TCOUNTE0 and the TM20 overflow signal are selected as the count of TM21 14 6 CLREn Specifies software clear for TM2n 0 TM2n operation continued 1...

Page 348: ...TE1n bit 1 TM2n count is stopped when the count value is 0 TM2n counts up except when the UDSEn1 UDSEn0 bits 10 The count direction when the UDSEn1 and UDSEn0 bits 10 is determined by the value of ECL...

Page 349: ...the TO2n pin output 0 Active level is high level 1 Active level is low level Specifies toggle mode OTMEn1 OTMEn0 Toggle Mode 0 0 Toggle mode 0 Reverse output level of TO2n output every time a sub chan...

Page 350: ...el n capture compare register 0 ED1 and ED2 signal inputs ignored nothing is done even if these signals are input 1 Operation caused by ED1 and ED2 signal inputs enabled 11 3 LNKEn Specifies capture e...

Page 351: ...ter selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare r...

Page 352: ...mpare register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected with bits TB1En TB0En 10 2 CCSEn Selects captu...

Page 353: ...r selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare reg...

Page 354: ...mpare register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected with bits TB1En TB0En 10 2 CCSEn Selects captu...

Page 355: ...ly bits 14 0 13 0 12 0 2 ECFE0 3 OVFE0 4 0 5 0 6 0 7 0 8 UDFE1 9 RSFE1 10 ECFE1 11 OVFE1 15 0 1 RSFE0 0 UDFE0 TBSTATE0 Address FFFFF664H Initial value 0101H Bit Position Bit Name Function 11 3 OVFEn I...

Page 356: ...ation has occurred In compare register mode No compare match has occurred 1 In capture register mode At least one capture operation has occurred In compare register mode At least one compare match has...

Page 357: ...3 0 4 ODLE20 5 ODLE21 6 ODLE22 7 0 8 ODLE30 9 ODLE31 10 ODLE32 11 0 15 0 1 ODLE11 0 ODLE10 ODELE0 Address FFFFF668H Initial value 0000H Bit Position Bit Name Function Specifies output delay operation...

Page 358: ...8 0 9 0 10 0 11 0 15 0 1 SEVE1 0 SEVE0 CSCE0 Address FFFFF66AH Initial value 0000H Bit Position Bit Name Function 5 to 0 SEVEn Specifies capture operation by software in capture register mode 0 Contin...

Page 359: ...The set values of the TESnE1 TESnE0 bits and the CESE1 CESE0 bits of the CSE0 register and the IESEx1 IESEx0 bits of the SESE0 register are shown Remarks 1 fCLK Base clock 2 CT TM2n count signal input...

Page 360: ...00B ECEEn Bit 0 ECREn Bit 0 CLREn Bit 0 CASE1 Bit 0 fCLK FFFDH Stop FFFEH FFFFH 0000H 1234H 1235H 0000H Stop CT CNT RNote 2 INTTM2n output CNT 0 OSTEn bitNote 1 CEEn bitNote 1 Notes 1 Bits OSTE CEE o...

Page 361: ...UDSEn1 UDSEn0 Bits 00B OSTEn Bit 0 CEEn Bit 1 CASE1 Bit 0 fCLK ECREn bitNote CLREn bitNote ECLR CNT CT ECEEn bitNote 1234H 1235H 0000H 0001H 0000H Note Bits ECEEn ECREn CLREn of TCRE0 register Remark...

Page 362: ...output CNT 0 CT UDSEn1 UDSEn0 bitsNote 1 FFFFH 0000H 0001H don t care 01B 10B 0002H 0001H 0000H 0001H 0002H 0003H 0002H FFFEH Notes 1 UDSEn1 UDSEn0 bits of TCRE0 register 2 Can control TM20 TM21 clea...

Page 363: ...Bit 1 fCLK CNT TB0 CNT TB1 CTC CASCNote TB1 FFFBH FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H 0004H 1234H 1235H Note If in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the CTC risin...

Page 364: ...e count value of TM21 is output to sub channels 1 to 4 at the rising edge of MUXTB1 Figure 9 68 shows the block diagram of the timer 2 multiplex count generator and Figure 9 69 shows the multiplex cou...

Page 365: ...TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 0001H FFFEH 1234H FFFFH FFFFH FFFFH 1234H 1234H 0000H 1234H 1235H 0000H 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Remarks 1 fCLK Base clock 2 CNT Count value of...

Page 366: ...TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 1 5 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Note 2 Note 2 Undefined Undefined 2 4 13 11 Notes 1 Bits TB0Ey TB1Ey of CMSEx register 2 If a...

Page 367: ...least twice at the start of operation and read the CVPEm0 register Also read the CVPEm0 register after performing capture at least once 2 Write operation to the CVPEn0 register is not performed at the...

Page 368: ...235H 0000H 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Note 2 Note 3 Notes 1 TM21 performs count operation when in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the rising edge of CTC...

Page 369: ...TB0 TB1 TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Cleared by timer Set by software Event detection by EEVEy bit prohibited L Notes 1 EEVEy bit of CMSEx0 register 2 SEVEy bit of CSCE0 regi...

Page 370: ...8 9 10 6 7 8 2 2 9 9 8 8 Note 3 Note 3 Note 3 Note 3 Note 2 Notes 1 TB1Ey TB0Ey bits of CMSEx0 register 2 No interrupt is generated due to compare match with counter differing from TB1Ey TB0Ey bit set...

Page 371: ...1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 0 1 2 12 13 14 4 4 7 1 7 1 Note LNKEy bit of CMSEx0 register Remarks 1 fCLK Base clock 2 MUXCNT Count value to sub channel m MUX...

Page 372: ...E050 Register s CCSEy Bit 0 EEVEy Bit 1 and CSCE0 Register s SEVEy Bit 0 fCLK ED1 ED2 CAPTURE_S READ_ENABLE_S CVSEy0 register CNT LNKEyNote 1 1 2 3 4 5 6 7 8 9 10 0 Note 2 Note 2 Undefined 2 6 9 Notes...

Page 373: ...Ey0 register MATCH RNote 1 INTCC20 INTCC25 output CNT CPU write C C 1 2 2 3 4 4 5 6 7 8 8 9 10 0 Note 2 Note 3 Note 2 Note 2 Note 3 Note 3 Notes 1 Can control TM20 TM21 clear by sub channel 0 5 compar...

Page 374: ...Bits 0 fCLK RA RB RN TO2n timer output ALVEn bit 0Note 2 TO2n timer output ALVEn bit 1Note 2 OTMEn1 OTMEn0 bitsNote 1 S T 00B 01B Notes 1 OTMEn1 OTMEn0 bits of OCTLE0 register 2 ALVEn bit of OCTLE0 re...

Page 375: ...En bit of OCTLE0 register Remarks 1 fCLK Base clock 2 RA Zero count signal input of TM20 output circuit reset signal RB Zero count signal input of TM21 output circuit reset signal RN Interrupt signal...

Page 376: ...3V0UD Figure 9 81 Signal Output Operation During Delay Output Operation When OCTLE0 Register s OTMEn1 OTMEn0 Bits 0 ALVEn 0 SWFEn Bit 0 fCLK TO2n timer output ODELEn2 to ODELEn0 bitsNote S T 5 2 Note...

Page 377: ...fCLK Division Ratio fXX Selected fXX 2 Selected 1 2 fXX 2 fXX 4 1 4 fXX 4 fXX 8 1 8 fXX 8 fXX 16 1 16 fXX 16 fXX 32 1 32 fXX 32 fXX 64 1 64 fXX 64 fXX 128 1 128 fXX 128 fXX 256 1 256 fXX 256 fXX 512...

Page 378: ...CC31 Read write INTC31 INTP31 TO3 R Notes 1 When fXX is selected as the base clock fCLK of TM3 2 When fXX 2 is selected as the base clock fCLK of TM3 Remark fXX Internal system clock S R Set Reset Fi...

Page 379: ...tual value Figure 9 83 Timer 3 TM3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TM3 FFFFF680H 0000H Address Initial value 0 TM3 performs the count up operations of an internal count clock or external count clo...

Page 380: ...fCLK 32 fCLK 64 fCLK 128 and fCLK 256 by the TMC30 register fCLK base clock An overflow interrupt can be generated if the timer overflows Also the timer can be stopped following an overflow by settin...

Page 381: ...these registers to capture registers CMS1 and CMS0 of TMC31 0 When these registers are set to capture registers the valid edges of the corresponding external interrupt signals INTP30 and INTP31 are de...

Page 382: ...et synchronized with the generation of a match signal The interrupt selection source differs according to the function of the selected register Cautions 1 To write to capture compare registers 30 and...

Page 383: ...CLK of timer 3 TM3 This register can be read written in 8 bit or 1 bit units Cautions 1 Always set this register before using the timer 2 Set fCLK to 32 MHz or less 7 0 PRM03 6 0 5 0 4 0 3 0 2 0 1 0 0...

Page 384: ...l value 00H Bit Position Bit Name Function 7 TM3OVF Flag that indicates TM3 overflow 0 No overflow 1 Overflow The TM3OVF bit becomes 1 when TM3 changes from FFFFH to 0000H An overflow interrupt reques...

Page 385: ...clock 1 TM3CE Controls the operation of TM3 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution If TM3CE 0 the external pulse output TO3 becomes inactive leve...

Page 386: ...ill not malfunction even if a glitch is generated or make sure that the ENT1 bit and the ALV bit do not change at the same time 3 TO3 output remains unchanged by external interrupt signals INTP30 INTP...

Page 387: ...utput is enabled until a match signal is generated Caution If either CC30 or CC31 is specified as a capture register the ENT1 bit must be set to 0 5 ALV Specifies active level of external pulse output...

Page 388: ...SESC register during timer operation If they are to be changed they must be changed after setting the TM3CE bit of the TMC30 register to 0 If the SESC register is overwritten during timer operation t...

Page 389: ...timer output signal TO3 can be set or reset Also a capture operation that holds the TM3 count value in the CC30 or CC31 register is performed synchronized with the valid edge that was detected from th...

Page 390: ...FFFFH to 0000H Also the overflow interrupt INTTM3 is not generated When the TM3 register is changed from FFFFH to 0000H because the TM3CE bit changes from 1 to 0 the TM3 register is considered to be...

Page 391: ...31 is used as an external trigger capture trigger The TM3 count value during counting is captured and held in the capture register synchronized with that capture trigger signal The capture register va...

Page 392: ...User s Manual U14492EJ3V0UD Figure 9 87 TM3 Capture Operation Example When Both Edges Are Specified TM3 Count start TM3CE 1 Overflow TM3OVF 1 D0 D1 D2 D0 D1 D2 Interrupt request INTP31 TM3 count valu...

Page 393: ...signal causes the timer output pin TO3 to change and an interrupt request signal INTCC30 INTCC31 to be generated at the same time If the CC30 or CC31 register is set to 0000H the 0000H after the TM3...

Page 394: ...V0UD Figure 9 88 Compare Operation Example 2 2 b If CCLR bit 1 and CC30 is 0000H 0001H TM3 Count up 0000H 0000H 0000H FFFFH Compare register CC30 INTTM3 Match detection INTCC30 Remark The match is det...

Page 395: ...output level of the TO3 pin is reset The output level of the TO3 pin can be specified by the TMC31 register Table 9 13 TO3 Output Control TO3 Output ENT1 ALV External Pulse Output Output Level 0 0 Dis...

Page 396: ...ing value of the CC30 register the TM3 register is cleared 0000H and an interrupt request signal INTCC30 is generated at the same time that the count operation resumes Figure 9 90 Contents of Register...

Page 397: ...al Timer Operation Timing Example Count start 0001H 0000H 0001H 0000H 0001H p p p p p p p 0000H Interval time Interval time Interval time Count clock t TM3 register CC30 register INTCC30 interrupt Cle...

Page 398: ...000H and continues counting This enables a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register to be output When the setting value of the CC30 register and the...

Page 399: ...00H FFFFH p p p p p p q q q q q q q p Count clock TM3 register CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt TO3 output t Remarks 1 p Setting value of CC30 register 0000H to FFFFH q...

Page 400: ...g the difference between the TM3 register s count value Dx that was captured in the CC30 register according to the x th valid edge input of the INTP30 pin and the TM3 register s count value D x 1 that...

Page 401: ...D3 D2 D1 D0 D1 D0 t D3 D2 t 10000H D1 D2 tNote Count clock TM3 register INTP30 input CC30 register INTCC30 interrupt INTTM3 interrupt No overflow Overflow occurs No overflow Clear Count start Note Whe...

Page 402: ...3 first set 1 the TM3CAE bit 5 The analog noise elimination time two cycles of the input clock are required to detect a valid edge of the external interrupt input INTP30 or INTP31 and external clock i...

Page 403: ...e frequency of the count clock to 16 MHz or less Base clock fCLK 1 type set fCLK to 32 MHz or less fXX 2 Prescaler division ratio The following division ratios can be selected according to the base cl...

Page 404: ...pture Trigger Timer Output S R Other Functions TM4 Read Timer 4 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CM4 Read write INTCM4 Remark fXX Internal system clock S R Set Reset Figure 9 9...

Page 405: ...er Overflow Cautions 1 If the TM4CAE0 bit of the TMC4 register is cleared 0 a reset is performed asynchronously 2 If the TM4CE0 bit of the TMC4 register is cleared 0 a reset is performed synchronized...

Page 406: ...hen a read operation to a CM4 register is performed data in the master side is read out CM4 can be read written in 16 bit units Cautions 1 A write operation to a CM4 register requires 4 clocks until t...

Page 407: ...9 97 Example of Timing During TM4 Operation a When TM4 CM4 TM4 TM4CAE0 TM4CE0 CM4 INTCM4 M N N N Remark M TM4 value when overwritten N CM4 value when overwritten M N b When TM4 CM4 TM4 TM4CAE0 TM4CE0...

Page 408: ...timer operation If they are to be changed they must be changed after setting the TM4CE0 bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operation is not guaranteed 1 TM4CE0...

Page 409: ...upt causes TM4 to be cleared 0 at the next count timing This function enables timer 4 to be used as an interval timer CM4 can also be set to 0 In this case when an overflow occurs and TM4 becomes 0 a...

Page 410: ...SE UNIT 410 User s Manual U14492EJ3V0UD Figure 9 98 TM4 Compare Operation Example 2 2 b When CM4 is set to 0 1 0 0 0 FFFFH Overflow TM4 Count clock CM4 TM4 clear Match detection INTCM4 Count up Clear...

Page 411: ...nal units When a count operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles 3 To initialize the TM4 register status and start counting again clear 0 the TM4CE0 bit...

Page 412: ...Function 9 6 1 Overview The V850E IA1 provides a function to connect timer 1 and timer 2 Figure 9 99 Block Diagram of Timer Connection Function Timer 2 Timer 1 CVSE10 CVPE10 CVSE20 CVPE20 Capture 0 C...

Page 413: ...al to CVSE20 CVPE20 registers 0 Don t input INTCM101 signal to CVSE20 CVPE20 registers 1 Input INTCM101 signal to CVSE20 CVPE20 registers 2 TMIC2 Enables disables input of INTCM100 signal to CVSE20 CV...

Page 414: ...ller 1 channel Remark For details about the FCAN controller refer to CHAPTER 11 FCAN CONTROLLER UART0 to UART2 whereby one byte of serial data is transmitted received following a start bit support ful...

Page 415: ...upt INTSER0 Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSR0 Interrupt is generated when receive data is transferred from...

Page 416: ...and the transmission shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in...

Page 417: ...l parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXB0 register according to the contents that were set in the ASIM0 register...

Page 418: ...ART0 1 Supplies clock to UART0 Cautions 1 When UARTCAE0 0 is set UART0 is asynchronously reset 2 When UARTCAE0 0 UART0 is in a reset state To operate UART0 first set UARTCAE0 1 3 When the UARTCAE0 bit...

Page 419: ...ts with the value 1 the parity bit is set 1 If it contains an even number of bits with the value 1 the parity bit is cleared 0 This controls the number of bits with the value 1 contained in the transm...

Page 420: ...bit first clear 0 the TXE0 and RXE0 bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Cautions 1 To overwrite the SL bit first clear 0 the TXE0 bit 2 Since reception is always don...

Page 421: ...Address Initial value ASIS0 0 0 0 0 0 PE FE OVE FFFFFA03H 00H Bit Position Bit Name Function 2 PE This is a status flag that indicates a parity error 0 When the ASIM0 register s UARTCAE0 and RXE0 bits...

Page 422: ...ASIM0 register s UARTCAE0 or TXE0 bit is 0 or when data has been transferred to the transmission shift register 1 Data to be transferred next exists in TXB0 register Data exists in TXB0 register when...

Page 423: ...0 in the ASIM0 register the contents of the RXB0 register are retained and no processing is performed for transferring data to the RXB0 register even when the shift in processing of one frame is comp...

Page 424: ...ster data is transferred to the transmission shift register and a transmission completion interrupt request INTST0 is generated synchronized with the completion of the transmission of one frame from t...

Page 425: ...ined for the ASIS0 register Whether a reception error interrupt INTSER0 or a reception completion interrupt INTSR0 is generated when an error occurs can be specified according to the ISRM bit of the A...

Page 426: ...gure 10 2 The character bit length within one data frame the type of parity and the stop bit length are specified according to the asynchronous serial interface mode register 0 ASIM0 Also data is tran...

Page 427: ...r 0 TXB0 When a transmit operation is started the data in TXB0 is transferred to transmission shift register Then the transmission shift register outputs data to the TXD0 pin the transmit data is tran...

Page 428: ...92EJ3V0UD 428 Figure 10 3 Asynchronous Serial Interface Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXD0 output INTST0 output Start D0 D1 D2 D6 D7 TXD0 output INTS...

Page 429: ...that the TXBF0 bit is 0 and then write the next transmit data second byte to TXB0 register If writing to the TXB0 register is performed when the TXBF0 bit is 1 transmit data cannot be guaranteed While...

Page 430: ...gisters Interrupt occurrence Wait for interrupt Required number of transfers performed Write transmit data to TXB0 register Write transmit data to TXB0 register When reading ASIF0 register TXBF0 0 Whe...

Page 431: ...0 register simultaneously 11 or 00 may be read Thus whether writing to the TXB0 register is enabled or not should be judged only for the TXBF0 bit ASIF0 Register Transmission Starting Procedure Intern...

Page 432: ...Stop bit ASIF0 Register Transmission End Procedure Internal Operation TXBF0 TXSF0 6 Transmission of data m 2 is in progress 1 1 7 INTST0 interrupt occurs Read ASIF0 register confirm that TXBF0 bit 0...

Page 433: ...ording to the serial clock from the baud rate generator 0 BRG0 c Reception completion interrupt When RXE0 bit 1 in the ASIM0 register and the reception of one frame of data is completed the stop bit i...

Page 434: ...n error The data reception result is that the various flags of the ASIS0 register are set 1 and a reception error interrupt INTSER0 or a reception completion interrupt INTSR0 is generated at the same...

Page 435: ...ception b An error occurs during reception INTSR0 output Reception completion interrupt INTSER0 output Reception error interrupt INTSR0 output Reception completion interrupt INTSER0 output Reception e...

Page 436: ...is odd b Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd T...

Page 437: ...t delivered to the internal circuit see Figure 10 11 Refer to 10 2 6 1 a Base clock regarding the base clock Also since the circuit is configured as shown in Figure 10 10 internal processing during a...

Page 438: ...generator 0 BRG0 configuration Figure 10 12 Baud Rate Generator 0 BRG0 Configuration fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1024 fXX 2048 Base clock fCLK Selector UARTCAE0...

Page 439: ...be read written in 8 bit units Cautions 1 The maximum allowable frequency of the base clock fCLK is 25 MHz Therefore when the system clock s frequency is 50 MHz bits TPS3 to TPS0 cannot be set to 0000...

Page 440: ...Bit Position Bit Name Function Specifies the 8 bit counter s division value MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 Set Value k Serial Clock 0 0 0 0 0 x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fCLK 8...

Page 441: ...rate baud normal rate baud Desired error with rate baud rate baud Actual Error Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception de...

Page 442: ...163 0 15 fXX 25 65 0 16 fXX 23 215 0 07 fXX 22 130 0 16 19200 fXX 23 163 0 15 fXX 24 80 0 16 fXX 22 215 0 07 fXX 21 130 0 16 31250 fXX 23 100 0 fXX 23 65 0 fXX 22 132 0 fXX 21 80 0 38400 fXX 22 163 0...

Page 443: ...arity bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10...

Page 444: ...allowable baud rate error of UART0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 10 4 Maximu...

Page 445: ...low 1 When the supply of clocks to UART0 is stopped for example IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The...

Page 446: ...ror Interrupt sources 2 types Reception completion interrupt INTSRn Interrupt is generated when receive data is transferred from the shift register to the reception buffer register n RXBn after serial...

Page 447: ...registers 4 2 frame continuous reception buffer registers RXB1 RXB2 reception buffer registers RXBL1 RXBL2 RXBn is a 16 bit during 2 frame continuous reception 9 bit extension data reception buffer re...

Page 448: ...hronous serial interface mode registers n0 n1 ASIMn0 ASIMn1 Asynchronous serial interface status register n ASISn Transmission control parity addition Reception buffers n Ln RXBn RXBLn PEn FEn OVEn Re...

Page 449: ...8 bit or 1 bit units Cautions 1 If the contents of the ASIMn0 register are changed during UARTn transmission or reception the UARTn operation cannot be guaranteed n 1 2 2 Set the ASIMn0 register when...

Page 450: ...pecifies parity bit length PS1 PS0 Operation 0 0 No parity extension bit operation 0 1 0 parity Transmit side Transmission with parity bit 0 Receive side No parity error generated during reception 1 0...

Page 451: ...transmission 1 UMSR Specifies number of continuous frame receptions 0 1 frame data reception 1 2 frame continuous data reception 0 EBS Specifies extension bit operation for transmit receive data when...

Page 452: ...ion end n 1 2 The status flag that indicates reception errors always indicates the most recent error status In other words if the same error occurs several times before receive data is read this flag...

Page 453: ...til stop bit detection from the start bit detection timing 4 RB8 Indicates contents of receive data extension bit 1 bit when 9 bit extended format is specified EBS bit of ASIMn1 register 1 2 PEn Statu...

Page 454: ...ive enabled status receive data is transferred from the reception shift register to the reception buffer in synchronization with the end of shift in processing for 1 frame of data The reception comple...

Page 455: ...osition Bit Name Function 15 to 0 RXB15 to RXB0 Stores receive data 0 can be read for the RXBn register when 7 8 bit character data is received When an extension bit is set during 9 bit character data...

Page 456: ...reception of 2nd frame no error RXDn Frame 1 Frame 2 Reception completion interrupt not generated upon end of reception of 3rd frame occurrence of error RXDn Frame 3 Frame 3 Value of OVEn bit of ASISn...

Page 457: ...can be read but since shifting is done in synchronization with the shift clock the data that is read cannot be guaranteed 14 TXS14 13 TXS13 12 TXS12 2 TXS2 3 TXS3 4 TXS4 5 TXS5 6 TXS6 7 TXS7 8 TXS8 9...

Page 458: ...data in the reception shift register undergoes shift in processing and is transferred to the reception buffer The reception completion interrupt request INTSRn is generated following stop bit sampling...

Page 459: ...20 ASIM10 ASIM20 Specification of the number of frames and specification of the extension bit is done with asynchronous serial interface mode registers 11 21 ASIM11 ASIM21 Data is transmitted LSB fir...

Page 460: ...DATA Parity bit Stop bit 0 0 0 DATA Stop bit Stop bit 0 Other than PS1 PS0 0 DATA Parity bit Stop bit Stop bit 1 0 0 DATA DATA Stop bit Stop bit 1 Other than PS1 PS0 0 1 0 DATA DATA Parity bit Stop bi...

Page 461: ...tomatically added b Transmission interrupt request When the transmission shift register becomes empty upon completion of the transmission of 1 or 2 frames of data a transmission completion interrupt r...

Page 462: ...it Start Parity Stop D0 TXDn output INTSTn interrupt Flag in transmission SOTn D1 D2 D6 D7 b When stop bit length 2 bits Start Parity Stop D0 TXDn output INTSTn interrupt Flag in transmission SOTn D1...

Page 463: ...Time of one stop bit 2 2 fXX 4 2 fXX fXX Internal system clock Caution 4 2 fXX has a margin of double the clock that can actually be used for operation Example Count clock frequency 32 MHz 32 000 000...

Page 464: ...d rate generator After 8 serial clocks have been output following detection of the falling edge of the RXDn pin the RXDn pin is again sampled If a low level is detected at this time the falling edge o...

Page 465: ...bit of the ASIMn0 register 1 the receive data in the shift register is transferred to RXBn RXBLn and a reception completion interrupt request INTSRn is generated after 1 frame or 2 frames of data hav...

Page 466: ...D6 D7 c In 2 frame continuous transmission mode Start Start Parity Stop Parity Stop D0 RXDn input INTSRn interrupt Flag in reception SIRn D1 1st frame 2nd frame D1 D5 D6 D7 Cautions 1 Even if a recept...

Page 467: ...ption Error Causes PEn Parity error The parity specification during transmission did not match the parity of the reception data FEn Framing error No stop bit was detected OVEn Overrun error The recept...

Page 468: ...transmit data is even 1 2 During reception The number of bits with the value 1 within the receive data including the parity bit is counted and a parity error is generated if this number is even c 0 p...

Page 469: ...utputs between connection nodes do not conflict In the synchronous mode the falling edge of the serial clock is used as the transmission timing and the rising edge as the reception timing but transmit...

Page 470: ...transmission reception mode Serial clock Transmission register write signal Flag in transmission SOTn Transmission completion interrupt INTSTn Reception completion interrupt INTSRn Reception buffer R...

Page 471: ...nsmission reception mode Serial clock Transmission register write signal Flag in transmission SOTn Transmission completion interrupt INTSTn Reception completion interrupt INTSRn Reception buffer RXBn...

Page 472: ...g Note The transmit data is delayed by 1 system clock in relation to the serial clock d Transmission reception timing and transmit data timing using external serial clock Note External serial clock Sy...

Page 473: ...n reception SIRn Reception completion interrupt INTSRn Error interrupt STOP STOP 1 2 3 Explanation 1 If the start bit of the second frame is not detected no reception completion interrupt is generated...

Page 474: ...el The serial clock source is specified with registers ASIM10 and ASIM20 If dedicated baud rate generator output is specified BRG1 and BRG2 are selected as the clock sources Since the same serial cloc...

Page 475: ...in 8 bit or 1 bit units Cautions 1 Do not change the values of the BGCS1 and BGCS0 bits during transmission reception operations 2 Set PRSMn register other than the UARTCEn bit prior to setting the UA...

Page 476: ...M3 2 PRSCM2 1 PRSCM1 0 PRSCM0 Address FFFFFA50H Initial value 00H d Baud rate generation First when the UARTCEn bit of the PRSMn register is overwritten with 1 the 8 bit timer counter for baud rate si...

Page 477: ...f PRSMn register k 0 1 2 3 Note The setting of m 256 is performed by writing 00H to the PRSCMn register 2 Formula for calculating the baud rate in synchronous mode Baud rate bps fXX Internal system cl...

Page 478: ...692 3 13 0 16 153600 9600 153846 2 9615 385 2 13 0 16 166400 10400 166666 7 10416 67 1 24 0 16 307200 19200 307692 3 19230 77 1 13 0 16 614400 38400 615384 6 38461 54 0 13 0 16 1228800 76800 1142857 7...

Page 479: ...BGCSm Bit m 0 1 PRSCMn Register Setting Value n 1 2 Error 9600 600 9585 89 599 1181 3 163 0 15 19200 1200 19171 78 1198 236 2 163 0 15 38400 2400 38343 56 2396 472 1 163 0 15 76800 4800 76687 12 4792...

Page 480: ...lowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10 24 after the start...

Page 481: ...FLmax can be obtained as follows FL k 2 2 k 21 FL k 2 2 k FL 11 max FL 11 10 11 FL k 20 2 k 21 max FL Therefore the transfer destination s minimum receivable baud rate BRmin is as follows BRmin FLmax...

Page 482: ...B first and LSB first Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SOn Serial transmit data output SIn Serial receive data input SCKn Serial clock I O Interrupt so...

Page 483: ...e actual transmission reception operations are started up by accessing the buffer register 5 Clocked serial interface reception buffer registers 0 1 SIRB0 SIRB1 The SIRBn register is a 16 bit buffer r...

Page 484: ...Selector The selector selects the serial clock to be used 14 Serial clock controller Controls the serial clock supply to the shift register Also controls the clock output to the SCKn pin when the inte...

Page 485: ...ffer register SOTBn SOTBLn Reception buffer register SIRBn SIRBLn Shift register SIOn SIOLn Initial transmission buffer register SOTBFn SOTBFLn Interrupt controller Clock start stop control clock phas...

Page 486: ...CSIM1 The CSIMn register controls the CSIn operation n 0 1 These registers can be read written in 8 bit or 1 bit units however bit 0 is read only Caution Overwriting the TRMDn CCL DIRn CSIT and AUTO b...

Page 487: ...in output is fixed to low level Data reception is started by reading the SIRBn register When the TRMDn bit 1 transmission reception is started by writing data to the SOTBn register 5 CCL Specifies dat...

Page 488: ...face clock selection registers 0 1 CSIC0 CSIC1 The CSICn register is an 8 bit register that controls the CSIn transfer operation n 0 1 These registers can be read written in 8 bit or 1 bit units Cauti...

Page 489: ...1 fXX 26 Master mode 0 1 0 fXX 25 Master mode 0 1 1 fXX 24 Master mode 1 0 0 fXX 23 Master mode 1 0 1 fXX 22 Master mode 1 1 0 Clock generated by BRG3 Master mode 1 1 1 External clock SCKn Slave mode...

Page 490: ...e 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOTn bit of CSIMn...

Page 491: ...the CSIMn register The SIRBLn register is the same as the lower bytes of the SIRBn register Cautions 1 Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register...

Page 492: ...utions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 14 SIRBE...

Page 493: ...RBELn register is the same as the SIRBLn register It is used to read the contents of the SIRBLn register Cautions 1 The receive operation is not started even if data is read from the SIRBELn register...

Page 494: ...SIMn register 1 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOTn bit of CSIMn register 0 If the SOTBn register is accessed during data tr...

Page 495: ...ame as the lower bytes of the SOTBn register Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO...

Page 496: ...SIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 14 SOTBF 14 13 SOTBF 13 12 SOTBF 12 2 SOT...

Page 497: ...s the same as the lower bytes of the SOTBFn register Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOTn bit o...

Page 498: ...ly when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SIOn register is read during data transfer the data cannot be gu...

Page 499: ...egister The SIOLn register is the same as the lower bytes of the SIOn register Caution Read the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the...

Page 500: ...value of the CSOTn bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSIn is set 1 and the CSOTn bit is cle...

Page 501: ...ation mode CKP bit 0 DAP bit 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bi...

Page 502: ...ation mode CKP bit 0 DAP bit 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSI...

Page 503: ...t signal delay control CSIT bit of CSIMn register 0 Figure 10 27 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1...

Page 504: ...1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 d When CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INT...

Page 505: ...ot 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 10 28 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6...

Page 506: ...en CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 0 1 2 Reg_R W Int...

Page 507: ...ssion reception completion interrupt request INTCSIn has been set 1 read the SIRBn register Note reserve next transfer 5 Repeat steps 3 and 4 N 2 times N Number of transfer data 6 Following output of...

Page 508: ...indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repe...

Page 509: ...errupt request INTCSIn 5 When the transmission reception completion interrupt request INTCSIn has been set 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register...

Page 510: ...l This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been re...

Page 511: ...ed with the period shown in Figure 10 31 Figure 10 31 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 SCKn I O INTCSIn interrupt Reser...

Page 512: ...Next Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 SCKn I O INTCSIn interrupt Reservation period 6 5 SCKn cycles d When data length 16 bits operation mod...

Page 513: ...tween transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot b...

Page 514: ...10 33 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 10 33 Interrupt Request and Register Access Contention SCKn I O INTCSIn inter...

Page 515: ...utput changes 2 SOn pin When the CSIn operation is disabled CSICAEn bit of CSIMn register 0 the SOn pin output status is as follows n 0 1 Table 10 10 SOn Pin Output Status TRMDn DAP AUTO CCL DIRn SOn...

Page 516: ...X The serial clock source is specified with registers CSIC0 and CSIC1 If dedicated baud rate generator output is specified BRG3 is selected as the clock source Since the same serial clock can be share...

Page 517: ...signals This register can be read written in 8 bit or 1 bit units Cautions 1 Do not change the values of the BGCS1 and BGCS0 bits during transmission reception operation 2 Set the PRSM3 register prio...

Page 518: ...ing the CSICAEn bit of the CSIMn register to 1 If the contents of the PRSCM3 register are overwritten when the value of the CSICAEn bit is 1 the cycle of the baud rate signal is not guaranteed 7 PRSCM...

Page 519: ...hen fXX 40 MHz BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 2500000 0 0 5 1000000 0 0 10 500000 0 0 20 250000 0 0 50 100000 0 0 100 50000 0 0 200 25000 0 1 250 10000 1 0 250 5000 c When fXX 50 MHz...

Page 520: ...Storage to reception buffer corresponding to ID Storage to buffer specified by receive mask function Remote reception Remote frames can be received in either the receive message buffer or the transmit...

Page 521: ...s interface as a means of transmitting and receiving signals 2 MAC Memory Access Controller This functional block controls access to the CAN module and to the CAN RAM within the FCAN 3 CAN module This...

Page 522: ...roller CAN RAM NPB NEC peripheral I O bus MAC Memory Access Controller NPB interface CAN module Interrupt request INTCREC INTCTRX INTCERR INTCMAC Message buffer 0 Message buffer 1 Message buffer 2 Mes...

Page 523: ...field xxxxm9E0H to xxxxm9FFH Message buffer 15 field xxxxmA00H to xxxxmA1FH Message buffer 16 field xxxxmA20H to xxxxmA3FH Message buffer 17 field xxxxmA40H to xxxxmA5FH Message buffer 18 field xxxxmA...

Page 524: ...after the SOF is detected on the CAN bus see Figure 11 2 and when the TMR bit is 1 the time stamp counter value is captured after the EOF is detected on the CAN bus a valid message is confirmed see F...

Page 525: ...ust be captured using the SOF In addition the ability to capture the time stamp counter value when message is stored in CAN message buffer n is useful for evaluating the FCAN controller s performance...

Page 526: ...value 2 Note 2 Note 3 3 M_DATAn0 register value Note 2 Note 3 4 M_DATAn0 register value M_DATAn1 register value Note 2 Note 3 5 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register value...

Page 527: ...y among messages is determined based on the locations of the messages in memory the message that has the lowest message number among the messages in the message buffer has the highest priority When se...

Page 528: ...e value is defined as 1 by masking is not subject to the abovementioned comparison between the received message s identifier and the message buffer s identifier However this comparison is performed fo...

Page 529: ...ID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0...

Page 530: ...vel and bit expression rules Higher Lower 11 7 1 Protocol mode function 1 Standard format mode 2032 different identifiers can be set in this mode The standard format mode uses 11 bit identifiers which...

Page 531: ...t is output when an error has been detected Overload frame Frame that is output when receiving side is not ready Remark Dominant D Dominant in wired OR Recessive R Recessive in wired OR In the figure...

Page 532: ...rt of frame SOF Remote frame 1 2 3 5 6 7 8 Remark The data field is not transferred even if the control field s data length code is not 0000B 2 Description of fields 1 Start of frame SOF The start of...

Page 533: ...Field In Extended Format Mode R D r1 r0 RTR IDE SRR IdentifierNote Identifier Arbitration field Control field 11 bits 18 bits ID28 ID18 ID17 ID0 1 bit 1 bit 1 bit Note Setting the higher 7 bits of th...

Page 534: ...ntrol Field R D r1 IDE r0 RTR DLC2 DLC3 DLC1 DLC0 Control field Data field Arbitration field In standard format mode the arbitration field s IDE bit is the same bit as the r1 bit Table 11 6 Data Lengt...

Page 535: ...equence and a 1 bit CRC delimiter Figure 11 14 CRC Field R D CRC sequence CRC delimiter 1 bit 15 bits CRC field ACK field Data field control field The polynomial P X used to generate the 15 bit CRC se...

Page 536: ...g depending on whether or not an error is detected between the start of frame field and the CRC field If an error is detected ACK slot Recessive R If no error is detected ACK slot Dominant D The trans...

Page 537: ...de is set if a transmission starts from a different node in bus idle mode The error passive node is composed of an intermission field suspend transmission field and bus idle field Figure 11 17 Interfr...

Page 538: ...rame ends when the next recessive R bit is detected Figure 11 18 Error Frame 1 R D 2 3 6 bits 0 to 6 bits 8 bits 4 5 Interframe space or overload frame Error delimiter Error flag Error flag Error bit...

Page 539: ...Overload flag node m Frame Overload frame No Name Bit count Definition 1 Overload flag starting from node m 6 Consecutive output of 6 dominant D bits Output when node m is not ready to receive 2 Over...

Page 540: ...tween a data frame and a remote frame the data frame takes priority because its last bit RTR is dominant D 11 8 2 Bit stuffing Bit stuffing is when one bit of inverted data is added for resynchronizat...

Page 541: ...of frame to end of frame error frame or overload frame Stuff error Use stuff bits to check receive data Six consecutive bits of same level data Transmitting receiving nodes Start of frame to CRC sequ...

Page 542: ...uring startup if only one node is active the error frame and data are repeatedly resent because no ACK is returned even data has been transmitted In such cases bus off mode cannot be set Even if the n...

Page 543: ...ring output of active error flag or overload flag transmitting node with error active status 8 No change Detection of bit error during output of active error flag or overload flag receiving node with...

Page 544: ...ase segment 1 Sample point Prop segment Sync segment Segment Name Segment Length Description Sync segment Synchronization Segment 1 This segment begins when resynchronization occurs Prop segment Propa...

Page 545: ...bus idle mode When a falling edge is detected on the bus the current bit is assigned to the sync segment and the next bit is assigned to the prop segment In such cases synchronization is performed re...

Page 546: ...t timing specified by the SJW synchronization is performed in the same way as hardware synchronization When the edge is detected as extending beyond the bit timing specified by the SJW synchronization...

Page 547: ...e usual method Use the procedure described in Figure 11 23 below to set or clear the lower 8 bits in these registers Setting or clearing of lower 8 bits in the above registers is performed in combinat...

Page 548: ...During Write Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Bit Status Af...

Page 549: ...register can be read written in 8 bit or 1 bit units Caution Set this register before using FCAN 7 0 PRM04 6 0 5 0 4 0 3 0 2 0 1 PRM5 0 PRM4 Address FFFFF930H Initial value 00H Bit Position Bit Name F...

Page 550: ...fer the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus 7 0 M_DLCn n 00 to 31 6 0 5 0 4 0 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Address See...

Page 551: ...8A4H M_DLC21 xxxxmAA4H M_DLC06 xxxxm8C4H M_DLC22 xxxxmAC4H M_DLC07 xxxxm8E4H M_DLC23 xxxxmAE4H M_DLC08 xxxxm904H M_DLC24 xxxxmB04H M_DLC09 xxxxm924H M_DLC25 xxxxmB24H M_DLC10 xxxxm944H M_DLC26 xxxxmB4...

Page 552: ...frame is received 1 DN flag set when remote frame is received 7 RMDE1 Cautions 1 When the RMDE1 bit is set the setting of the RMDE0 bit is irrelevant 2 If a remote frame arrives at the transmit messag...

Page 553: ...ed by the transmit message buffer when the auto acknowledge function has not been set RMDE0 bit 0 2 An interrupt request is not generated when interrupts are enabled under the following conditions Whe...

Page 554: ...M_CTRL21 xxxxmAA5H M_CTRL06 xxxxm8C5H M_CTRL22 xxxxmAC5H M_CTRL07 xxxxm8E5H M_CTRL23 xxxxmAE5H M_CTRL08 xxxxm905H M_CTRL24 xxxxmB05H M_CTRL09 xxxxm925H M_CTRL25 xxxxmB25H M_CTRL10 xxxxm945H M_CTRL26 x...

Page 555: ...according to the FCAN s time stamp setting which is either the time stamp counter value that was captured when the SOF was sent via the bus or the value captured when the CAN module writes data to the...

Page 556: ...4 3 D5_3 2 D5_2 1 D5_1 0 D5_0 Address See Table 11 17 Initial value Undefined 7 D6_7 M_DATAn6 n 00 to 31 6 D6_6 5 D6_5 4 D6_4 3 D6_3 2 D6_2 1 D6_1 0 D6_0 Address See Table 11 17 Initial value Undefine...

Page 557: ...14 xxxxm9C8H xxxxm9C9H xxxxm9CAH xxxxm9CBH xxxxm9CCH xxxxm9CDH xxxxm9CEH xxxxm9CFH 15 xxxxm9E8H xxxxm9E9H xxxxm9EAH xxxxm9EBH xxxxm9ECH xxxxm9EDH xxxxm9EEH xxxxm9EFH 16 xxxxmA08H xxxxmA09H xxxxmA0AH x...

Page 558: ...ID0 Third byte higher two bits of receive data Note is stored Note See 11 10 5 CAN message data registers n0 to n7 M_DATAn0 to M_DATAn7 n 00 to 31 14 0 13 0 12 ID28 2 ID18 3 ID19 4 ID20 5 ID21 6 ID22...

Page 559: ...he addresses xxxx as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set Table 11 19 Addresses of M_IDHn n 00 to 31 Register Name AddressNote m...

Page 560: ...ve message mask 1 is set 1 0 0 Receive message mask 2 is set 1 0 1 Receive message mask 3 is set 1 1 0 Setting prohibited 1 1 1 Receive message used in diagnostic processing mode 5 to 3 MT2 to MT0 Whe...

Page 561: ...M_CONF21 xxxxmAB4H M_CONF06 xxxxm8D4H M_CONF22 xxxxmAD4H M_CONF07 xxxxm8F4H M_CONF23 xxxxmAF4H M_CONF08 xxxxm914H M_CONF24 xxxxmB14H M_CONF09 xxxxm934H M_CONF25 xxxxmB34H M_CONF10 xxxxm954H M_CONF26 x...

Page 562: ...tware compatibility Bit Position Bit Name Function 2 DN This is the message update flag 0 No message was received after DN bit was cleared 1 At least one message was received after DN bit was cleared...

Page 563: ...M_STAT21 xxxxmAB5H M_STAT06 xxxxm8D5H M_STAT22 xxxxmAD5H M_STAT07 xxxxm8F5H M_STAT23 xxxxmAF5H M_STAT08 xxxxm915H M_STAT24 xxxxmB15H M_STAT09 xxxxm935H M_STAT25 xxxxmB35H M_STAT10 xxxxm955H M_STAT26 x...

Page 564: ...he message update flag set DN clear DN Operation 0 1 Cleared DN bit cleared 1 0 Set DN bit set Other than above No change in DN bit value 10 2 set DN clear DN Specifies setting clearing of the transmi...

Page 565: ...TAT21 xxxxmAB6H SC_STAT06 xxxxm8D6H SC_STAT22 xxxxmAD6H SC_STAT07 xxxxm8F6H SC_STAT23 xxxxmAF6H SC_STAT08 xxxxm916H SC_STAT24 xxxxmB16H SC_STAT09 xxxxm936H SC_STAT25 xxxxmB36H SC_STAT10 xxxxm956H SC_S...

Page 566: ...set m 2 6 A E Bit Position Bit Name Function 14 INTMAC Indicates an MAC errorNote interrupt GINT2 GINT1 is pending 0 Not pending 1 Pending 2 CAN1ERR Indicates a CAN access error interrupt C1INT6 to C1...

Page 567: ...n the interrupt enable bit has been set to 1 However the interrupt pending bit is not automatically cleared to 0 just because the interrupt enable bit has been cleared to 0 Use software processing to...

Page 568: ...leared to 0 just because the interrupt enable bit has been cleared to 0 Use software processing to clear the interrupt pending bit to 0 7 0 C1INTP 6 C1INT6 5 C1INT5 4 C1INT4 3 C1INT3 2 C1INT2 1 C1INT1...

Page 569: ...e CSTP bit has not been set to 1 3 When a change occurs on the CAN bus via a CSTP bit setting while the clock supply to the CPU or peripheral functions is stopped CPU can be woken up 14 0 13 0 12 0 2...

Page 570: ...ions on Bit Set Clear Function 2 When writing to the CGST register set or clear bits according to the register configuration shown in part b Write 1 3 Address xxxxmC10HNote Initial value 0100H 14 0 13...

Page 571: ...te See 11 10 17 CAN time stamp count register CGTSC 0 GOM Indicates the status of the global operation mode 0 Access to CAN module registerNote is prohibited 1 Access to CAN module registerNote is ena...

Page 572: ...value 11 3 set EFSD clear EFSD Sets clears the TSM bit set TSM clear TSM Operation 0 1 TSM bit cleared to 0 1 0 TSM bit set to 1 Other than above No change in TSM bit value 10 2 set TSM clear TSM Sets...

Page 573: ...4 0 5 0 6 0 7 0 8 0 9 set G_IE1 10 set G_IE2 11 0 15 0 1 clear G_IE1 0 0 CGIE Write 14 0 13 0 12 0 2 G_IE2 3 0 4 0 5 0 6 0 7 0 8 0 9 1 10 0 11 1 15 0 1 G_IE1 0 0 Note xxxx CAN message buffer registers...

Page 574: ...A E Bit Position Bit Name Function Indicates global timer system clock fGTS see Figure 11 25 n CGTS 7 CGTS 6 CGTS 5 CGTS 4 CGTS 3 CGTS 2 CGTS 1 CGTS 0 System Timer Prescaler Selection fGTS fGTS1 n 1 0...

Page 575: ...TCS0 MCP3 MCP2 Prescaler Data bit time CAN1 bit rate prescaler register C1BRP CAN main clock selection register CGCS Global timer clock prescaler Baud rate generator Global timer system clock CAN1 syn...

Page 576: ...r function writes 0 to all bits in the CGTSC register This register is read only in 16 bit units 14 TSC14 13 TSC13 12 TSC12 2 TSC2 3 TSC3 4 TSC4 5 TSC5 6 TSC6 7 TSC7 8 TSC8 9 TSC9 10 TSC10 11 TSC11 15...

Page 577: ...dresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E a Read Bit Position Bit Name Function 9 MM Confirms multiple hits from...

Page 578: ...the DN flag of M_STATn register not checked 1 Status of the DN flag of M_STATn register checked 8 SMNO Sets search module 0 No search module setting 1 CAN module set as search target 4 to 0 STRT4 to...

Page 579: ...o compare the lower 18 bits i e to mask the lower 18 bits set the CMID17 to CMID0 bits to 1 a 0 to 3 Address See Table 11 23 Initial value Undefined 14 0 13 0 12 CMID 28 2 CMID 18 3 CMID 19 4 CMID 20...

Page 580: ...6 A E C1MASKL0 xxxxmC40H C1MASKH0 xxxxmC42H C1MASKL1 xxxxmC44H C1MASKH1 xxxxmC46H C1MASKL2 xxxxmC48H C1MASKH2 xxxxmC4AH C1MASKL3 xxxxmC4CH C1MASKH3 xxxxmC4EH Note CAN message buffer registers can be...

Page 581: ...EVT 6 clear DLEVR 7 0 8 set INIT 9 set SLEEP 10 set STOP 11 set TMR 15 0 1 clear SLEEP 0 clear INIT C1CTRL Write 14 TECS0 13 RECS1 12 RECS0 2 STOP 3 TMR 4 OVM 5 DLEVT 6 DLEVR 7 0 8 ISTAT 9 RSTAT 10 TS...

Page 582: ...is reset 6 DLEVR This is the dominant level control bit for receive pins 0 A low level to a receive pin is acknowledged as dominant 1 A high level to a receive pin is acknowledged as dominant 5 DLEVT...

Page 583: ...odule 0 Normal operation mode 1 Initialization mode Cautions 1 Be sure to confirm that the CAN module has entered the initialization mode using the ISTAT bit ISTAT bit 1 after setting the INIT bit to...

Page 584: ...ther than above TMR bit not changed 11 3 set TMR clear TMR Sets clears the STOP bit set STOP clear STOP Operation 0 1 STOP bit cleared to 0 1 0 STOP bit set to 1 Other than above STOP bit not changed...

Page 585: ...te 14 0 13 0 12 0 2 VALID 3 BERR 4 PBB 5 SSHT 6 MOM 7 DGM 8 0 9 0 10 0 11 0 15 0 1 WAKE 0 OVR Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I...

Page 586: ...red due to a transmission it is handled as an incomplete transmission Cautions 1 In single shot mode even if the CAN lost in arbitration it is handled as a completed message transmission When in this...

Page 587: ...Normal operation 1 CAN sleep mode canceled 0 OVR Indicates overrun error status 0 Normal operation 1 Overrun occurred during RAM access Caution When an overrun error has occurred the OVR bit is set t...

Page 588: ...SSHT bit set SSHT clear SSHT Operation 0 1 SSHT bit cleared to 0 1 0 SSHT bit set to 1 Other than above SSHT bit not changed 13 5 set SSHT clear SSHT Sets clears the PBB bit set PBB clear PBB Operati...

Page 589: ...owever that the xxxx addresses cannot be changed after being set m 2 6 A E Bit Position Bit Name Function Indicates the last error information LERR3 LERR2 LERR1 LERR0 Last Error Information 0 0 0 0 Er...

Page 590: ...ers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E Bit Position Bit Name Function 15 t...

Page 591: ...12 0 2 E_INT2 3 E_INT3 4 E_INT4 5 E_INT5 6 E_INT6 7 0 8 1 9 0 10 0 11 1 15 0 1 E_INT1 0 E_INT0 Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral...

Page 592: ...INT4 Operation 0 1 E_INT4 interrupt cleared to 0 1 0 E_INT4 interrupt set to 1 Other than above E_INT4 interrupt not changed 12 4 set E_INT4 clear E_INT4 Sets clears the E_INT3 bit set E_INT3 clear E_...

Page 593: ...J3V0UD 3 3 b Write 2 2 Bit Position Bit Name Function Sets clears the E_INT0 bit set E_INT0 clear E_INT0 Operation 0 1 E_INT0 interrupt cleared to 0 1 0 E_INT0 interrupt set to 1 Other than above E_IN...

Page 594: ...tion Indicates CAN module status CACT4 CACT3 CACT2 CACT1 CACT0 CAN Module Status 0 0 0 0 0 Reset state 0 0 0 0 1 Bus idle wait 0 0 0 1 0 Bus idle state 0 0 0 1 1 Start of frame 0 0 1 0 0 Standard iden...

Page 595: ...y the value set to the C1SYNC register While in normal operation mode C1DEF register s MOM bit 0 the C1BRP register can only be accessed when the initialization mode has been set C1CTRL register s INI...

Page 596: ...be changed after being set m 2 6 A E a When TLM 0 Bit Position Bit Name Function 15 TLM Specifies transfer layer mode 0 6 bit prescaler mode 6 BTYPE Specifies CAN bus type 0 Low speed 125 kbps 1 High...

Page 597: ...clock fBTL for CAN module n BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN Protocol Layer Base System Clock fBTL 0 0 0 0 0 0 0 0 0 Setting prohibited 1 0 0 0 0 0 0 0 1 fMEM 2 2 0 0 0 0 0 0 1 0 fMEM 3 3 0...

Page 598: ...0 this register cannot be accessed 2 Storage of the last 8 bits is automatically stopped if an error or a valid message ACK delimiter is detected on the CAN bus Reset is automatically performed each t...

Page 599: ...stem clock 1 2 14 0 13 0 12 SAMP 2 DBT2 3 DBT3 4 DBT4 5 SPT0 6 SPT1 7 SPT2 8 SPT3 9 SPT4 10 SJW0 11 SJW1 15 0 1 DBT1 0 DBT0 C1SYNC Address xxxxmC5EHNote Initial value 0218H Note xxxx CAN message buffe...

Page 600: ...e Setting prohibited 9 to 5 SPT4 to SPT0 Remark Sampling point within bit timing is selected Sets data bit time DBT4 DBT3 DBT2 DBT1 DBT0 Data Bit Time 0 0 1 1 1 BTL 8 0 1 0 0 0 BTL 9 0 1 0 0 1 BTL 10...

Page 601: ...ntrol Register C1SYNC Settings See Figure 11 32 CAN1 Interrupt Enable Register C1IE Settings See Figure 11 33 CAN1 Definition Register C1DEF Settings See Figure 11 34 CAN1 Control Register C1CTRL Sett...

Page 602: ...er Figure 11 28 CAN Global Interrupt Enable Register CGIE Settings START No Enable interrupt for G_IE1 bit Yes set G_IE1 1 clear G_IE1 0 No Enable interrupt for G_IE2 bit An interrupt occurs if a memo...

Page 603: ...0 Figure 11 30 CAN1 Bit Rate Prescaler Register C1BRP Settings START No Transfer speed is 125 kbps or less Yes BTYPE 0 low speed fBTL setting When TLM 0 BRP5 to BRP0 When TLM 1 BRP7 to BRP0 When TLM 0...

Page 604: ...e BTL m 1 m 7 to 24 set using bits DBT4 to DBT0 Sampling point BTL m 1 m 4 to 16 set using bits SPT4 to SPT0 Set sampling point SPT4 to SPT0 Set SJW SJW1 SJW0 SAMP 1 Yes Set once only single shot samp...

Page 605: ...No clear E_INT2 1 set E_INT2 0 Enable interrupt for E_INT2 Interrupt enable flag for error passive or bus off by TEC set E_INT3 1 clear E_INT3 0 No clear E_INT3 1 set E_INT3 0 Enable interrupt for E_I...

Page 606: ...bers Diagnostic processing mode Transmit priority is determined based on identifiers Single shot mode Transmit only once Do not retransmit clear DGM 1 set DGM 0 No set DGM 1 clear DGM 0 Store to buffe...

Page 607: ...pins Set dominant level for receive pins Store timer value when EOF occurs Do not overwrite message in DN flag delete new message Set dominant level to high level Set dominant level to high level set...

Page 608: ...1MASKLa and C1MASKHa a 0 to 3 Settings START Standard frame Mask setting for standard frame x 18 to 28 Mask setting for extended frame x 0 to 28 Mask setting for message ID format No CMIDx 0 CMIDx 1 M...

Page 609: ...IIDE 0 standard M_IDHn Set message configuration See Figure 11 37 CAN Message Configuration Registers 00 to 31 M_CONF00 to M_CONF31 Settings See Figure 11 38 CAN Message Control Registers 00 to 31 M_C...

Page 610: ...ssage buffer Yes Yes MA 0 MA 1 Yes No No No No No No No MT2 to MT0 111 used in diagnostic processing mode MT2 to MT0 000 MT2 to MT0 001 MT2 to MT0 010 MT2 to MT0 011 MT2 to MT0 100 MT2 to MT0 101 Yes...

Page 611: ...TART Yes No No RTR 0 RTR 1 Transmit receive remote frame Transmit receive data frame Set remote frame auto acknowledge function Yes No IE 0 IE 1 Enable interrupt Disable interrupt Yes No RMDE0 1 RMDE0...

Page 612: ...t messages are output from the target message buffer Figure 11 39 Transmit Setting START End of transmit operation Set RDY flag set RDY 1 clear RDY 0 SC_STATn Set data M_DATAnm Select transmit message...

Page 613: ...interrupt pending flag Set RDY flag set RDY 1 clear RDY 0 SC_STATn End of receive operation Yes Receive data frame No Yes Receive data frame Receive remote frame Detection methods 1 Detect using CAN1...

Page 614: ...ke up occurs when there is a bus operation Figure 11 41 CAN Sleep Mode Settings START End of CAN sleep mode settings No Yes SLEEP 1 C1CTRL set SLEEP 1 clear SLEEP 0 C1CTRL Figure 11 42 Clearing of CAN...

Page 615: ...N sleep mode clearing operation 11 11 5 CAN stop mode In CAN stop mode the FCAN controller can be set to standby mode No wake up occurs when there is a bus operation stop mode is controlled by CPU acc...

Page 616: ...CHAPTER 11 FCAN CONTROLLER 616 User s Manual U14492EJ3V0UD Figure 11 45 Clearing of CAN Stop Mode START End of CAN stop mode clearing operation clear STOP 1 set STOP 0 clear SLEEP 1 set SLEEP 0 C1CTRL...

Page 617: ...C1SYNC 1 Example of FCAN baud rate setting when C1BRP register s TLM bit 0 The following is an example of how correct settings for the C1BRP register and C1SYNC register can be calculated Conditions...

Page 618: ...10 The settings that can actually be made for the V850E IA1 are in the range from 5 to 7 above the section enclosed in broken lines Among these options in the range from 5 to 7 above option 6 is the...

Page 619: ...baud rate iii SPT sampling point setting Given SJW 3 SJW DBT SPT 3 15 SPT SPT 12 Therefore SPT is set as 11 max SPT is calculated as below SPT BTL a 1 4 a 16 Value a is set using bits 9 to 5 SPT4 to...

Page 620: ...the message buffer having the lowest message number is selected 2 Receive messages can be stored in receive message buffers when the receive messages meet the following conditions 1 Messages are not l...

Page 621: ...n be stored in receive message buffers when the receive messages meet the following conditions Messages are not linked to masks M_STATn register s DN bit has been set to 1 n 00 to 31 If several receiv...

Page 622: ...ad When the CPU performs sequential access of a CAN message buffer data is read from the buffer in the order shown in Figure 11 47 below Only the FCAN can set the M_STATn register s DN bit to 1 and on...

Page 623: ...ncrementing 1 the read address when data is read in the following order M_DLCn register M_CTRLn register M_TIMEn register M_DATAn0 to M_DATAn7 registers M_IDLn M_IDHn register If these linear address...

Page 624: ...bus error has been detected Bit error Bit stuff error Form error CRC error ACK error 3 When the CAN bus mode has been changed Error passive status elapsed while FCAN was transmitting Bus off status wa...

Page 625: ...tamp counter Set TSM bit 0 in CGST register set TSM bit 0 clear TSM bit 1 3 Stop CAN interface Set GOM bit 0 in CGST register set GOM bit 0 clear GOM bit 1 Stop CAN clock Cautions 1 If the above proce...

Page 626: ...When receiving a remote frame with an extended ID and storing it in the receive message buffer the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC...

Page 627: ...bit address setting for match detection on chip at a single point this function outputs a match trigger falling edge to the NBD tool when the address match detection shown below is performed The lower...

Page 628: ...of the CPU but exists independently as NBD space Because of this NBD space is space that cannot be read or written from within the CPU but can only be read or written from the NBD dedicated interface...

Page 629: ...n is shown below 1 Basic protocol Figure 12 2 Basic Protocol 1 On a read CLK_DBG SYNC AD0_DBG to AD3_DBG N Address section Command packet Flag sense Control section N R Data packet 2 On a write CLK_DB...

Page 630: ...D20 15th D27 D26 D25 D24 16th D31 D30 D29 D28 Caution Values are for command packet maximum setup Access to NBD space Address 12 bits A0 to A11 Fixed Data 8 bits D0 to D7 Access to target space Addre...

Page 631: ...AM data will be destroyed 2 A write is invalid and read data is undefined in cases where Setting prohibited is specified 3 Flag sense packet NBD Bus Line AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 RFLG...

Page 632: ...d SYNC inactive confirmation Table 12 3 Command Packet On a Write ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 0 2nd SIZ1 SIZ0 1 1 3rd to 8th Target space write address specification 24 bits 9th...

Page 633: ...n a Write to NBD Space ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 0 2nd 0 0 1 0 3rd A3 A2 A1 A0 4th A7 A6 A5 A4 5th A11 A10 A9 A8 6th D3 D2 D1 D0 7th D7 D6 D5 D4 Caution An NBD space write addr...

Page 634: ...the system clock of the target CPU The active width is one cycle of the internal system clock of the CPU 1 Event detection conditions Execution PC address match Match detection range for timing of a w...

Page 635: ...AU11 10 EVAU10 9 EVAU9 8 EVAU8 NBD space address 801H Initial value Undefined 23 EVAU23 EVTU_A23 to EVTU_A16 22 EVAU22 21 EVAU21 20 EVAU20 19 EVAU19 18 EVAU18 17 EVAU17 16 EVAU16 NBD space address 802...

Page 636: ...chip ID registers have fixed values for each product The chip ID registers TID0 to TID2 are read only registers 7 MC7 TID0 6 MC6 MC7 to MC0 Semiconductor manufacturer classification code NEC Electron...

Page 637: ...ss of RAM Remark Register values written from the NBD tool can be read by DMA CPU and values written by DMA CPU can be read by the NBD tool 2 RAM access data buffer register H NBDH NBDH register opera...

Page 638: ...can be read from the NBDMSL register by DMA CPU 4 DMA source address setting register SH NBDMSH NBDMSH register specifies a DMA source address It can be written from the NBD tool and read by DMA CPU...

Page 639: ...can be read from the NBDMDL register by DMA CPU 6 DMA destination address setting register DH NBDMDH NBDMDH register specifies a DMA destination address It can be written from the NBD tool and read b...

Page 640: ...wards Reset again 12 6 3 Restrictions related to NBD event trigger function 1 If a ROM execution address event trigger is set to the address after a branch instruction an event is generated due to pip...

Page 641: ...te DMA registers are 16 bit access only 4 Set DMA addressing control register n DADCn of the DMA channel assigned to the NBDREW interrupt for 32 bit transfer bit transfer settings of 8 bits 4 16 bits...

Page 642: ...00F088 r24 DMACH0 Destination Address st h r24 DDAL0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000800c...

Page 643: ...0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000400c r24 DMACH1 Block MODE 16Bit MODE st h r24 DADC1 r0...

Page 644: ...L0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000000c r24 DMACH1 Block MODE 8Bit MODE st h r24 DADC1 r0...

Page 645: ...ADSCM10 register and sends it to the sample and hold circuit n 0 to 7 2 Sample and hold circuit The sample and hold circuit individually samples analog inputs sent sequentially from the input circuit...

Page 646: ...s to ANI0n and ANI1n that are within the range of the ratings In particular if a voltage including noise higher than AVDD or lower than AVSS even one within the range of absolute maximum ratings is in...

Page 647: ...AVREF0 AVREF1 may give rise to an invalid conversion result Software processing is needed in order to prevent this invalid conversion result from adversely affecting the system The following are exam...

Page 648: ...er Mode ITRG0 A D converter 0 ADTRG0 INTCM003 INTCM013 ITRG0 A D converter 1 ADTRG1 INTTM00 INTTM01 0 ITRG0 ITRG22 ITRG21 ITRG20 0 ITRG12 ITRG11 ITRG10 Internal bus Selector Selector Selector Selector...

Page 649: ...ister they can be read written in 8 bit or 1 bit units However writing to an ADSCMn0 register during A D conversion operation initializes conversion operation and starts the conversion over from the b...

Page 650: ...ble 1 Enable 14 ADCSn Shows status of A D converter 0 or 1 This bit is read only 0 Stopped 1 Operating The ADCSn bit is 0 for the duration of 6 fXX 2 immediately after the start of A D conversion and...

Page 651: ...put pin number that is set by bits SANI3 to SANI0 to a smaller pin number than the conversion termination analog input pin number that is set by bits ANIS3 to ANIS0 7 to 4 SANI3 to SANI0 Specifies ana...

Page 652: ...n operation is suspended and subsequently terminates 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0 0 0 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0...

Page 653: ...CMP9 10 DET ANI0 11 DET ANI1 15 ADET EN0 1 DET CMP1 0 DET CMP0 ADETM0 Address FFFFF244H Initial value 0000H 14 ADET LH1 13 DET ANI3 12 DET ANI2 2 DET CMP2 3 DET CMP3 4 DET CMP4 5 DET CMP5 6 DET CMP6...

Page 654: ...3 0 12 0 2 ADCRn2 3 ADCRn3 4 ADCRn4 5 ADCRn5 6 ADCRn6 7 ADCRn7 8 ADCRn8 9 ADCRn9 10 0 11 0 15 0 1 ADCRn1 0 ADCRn0 ADCR0n Address See Table 13 1 Initial value 0000H ADCR1n Address See Table 13 2 Initia...

Page 655: ...spondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers A D Converter Analog Input Pin A D Conversion Result Register ANI00 ADCR00 ANI01 ADCR01 ANI02 ADCR02 ANI03 ADCR03 ANI04 ADCR04 A...

Page 656: ...er source of A D converter 1 ITRG22 ITRG21 ITRG20 ITRG10 Trigger Source 0 0 0 Select INTCM003 0 0 1 Select INTCM013 0 1 0 Select INTTM00 0 1 1 Select INTTM01 1 0 0 Select INTCM003 and INTTM00 1 0 1 Se...

Page 657: ...returns integer of value in VIN Analog input voltage AVREF AVREF0 or AVREF1 pin voltage ADCR Value of A D conversion result register ADCR0n or ADCR1n Figure 13 3 illustrates the relationship between t...

Page 658: ...ated A D Converter A D Conversion Termination Interrupt Signal 0 Generate INTAD0 1 Generate INTAD1 2 Voltage detection interrupts INTDET0 INTDET1 In voltage detection mode ADETEN0 or ADETEN1 bit of AD...

Page 659: ...s store the conversion result in the ADCR0n or ADCR1n register When the specified number of A D conversions have terminated generate an A D conversion termination interrupt INTAD0 INTAD1 n 0 to 7 Note...

Page 660: ...he conversion timing of the analog input set for the ANI0n or ANI1n pin n 0 to 7 is a mode that starts A D conversion by setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 In this...

Page 661: ...1n or ANI0n n 0 to 7 Figure 13 4 Example of Select Mode Operation Timing ANI01 For A D Converter 0 ANI01 input A D conversion Data 1 ANI01 Data 2 ANI01 Data 3 ANI01 Data 4 ANI01 Data 5 ANI01 Data 6 AN...

Page 662: ...interrupt INTAD0 or INTAD1 Figure 13 5 Example of Scan Mode Operation Timing For A D Converter 0 4 Channel Scan ANI00 to ANI03 ANI00 input ANI01 input ANI02 input ANI03 input A D conversion Data 1 ANI...

Page 663: ...generated for each A D conversion termination which terminates A D conversion ADCS0 or ADCS1 bit 0 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 07 10 to 17 To restart A D con...

Page 664: ...f ADSCM00 or ADSCM10 register Be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to Note 2 2 Set using ANIS3 to ANIS0 bits of ADSCM00 or...

Page 665: ...each A D conversion termination A D conversion operation is repeated until the ADCE0 or ADCE1 bit 0 ADCS0 or ADCS1 bit 1 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 07 10 to...

Page 666: ...00 or ADSCM10 register Remark x 00 to 07 10 to 17 It is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A D conversion restart operation in A D trigger poll...

Page 667: ...DCR1n register corresponding to the analog input n 0 to 7 An A D conversion termination interrupt INTAD0 or INTAD1 is generated for each A D conversion which terminates A D conversion ADCS0 or ADCS1 0...

Page 668: ...Register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 Interrupt specified by ITRG0 register ANIn7 ADCRn7 Remark n 0 1 After all of the specified A D conve...

Page 669: ...is A D converted and the result is stored in one ADCR0n or ADCR1n register Analog inputs correspond one to one with A D conversion result registers For each A D conversion an A D conversion terminatio...

Page 670: ...ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ADTRGn signal ANIn7 ADCRn7 Remark n 0 1 After all specified A D conversions terminate A D conversion is restarted when an external trigger signal occurs This is optima...

Page 671: ...or timer trigger is input during A D conversion operation that trigger input is ignored 3 When interval conversion time If an external or timer trigger is input at the same time as A D conversion ter...

Page 672: ...e timing of the stop of operation of the A D converter conflict the A D conversion value may be undefined Because of this be sure to read the A D conversion result while the A D converter is in operat...

Page 673: ...g formula regardless of the resolution 1 FSR Max value of analog input voltage that can be converted Min value of analog input voltage that can be converted 100 AVREFn 0 100 AVREFn 100 Remark n 0 1 1L...

Page 674: ...o scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 13 17 Quantization Error 0 0 1 1 Digital output Quantization error 1 2LSB 1...

Page 675: ...111 Figure 13 19 Full Scale Error 100 011 010 000 0 AVREFn AVREFn 1 AVREFn 2 AVREFn 3 Digital output Lower 3 bits Analog input LSB Full scale error 111 n 0 1 6 Differential linearity error While the i...

Page 676: ...error are 0 Figure 13 21 Integral Linearity Error 0 AVREFn n 0 1 Digital output Analog input Integral linearity error Ideal line 1 1 0 0 8 Conversion time This expresses the time from when the analog...

Page 677: ...y ports The port configuration is shown below Port DH P00 P07 P10 P15 P20 P27 P30 P37 P40 P47 PDH0 PDH7 PDL0 PDL15 PCS0 PCS7 PCT0 PCT7 PCM0 PCM4 Port DL Port CS Port CT Port CM Port 0 Port 1 Port 2 Po...

Page 678: ...evel for the signal output in the control mode in the corresponding bits of port n n 0 to 4 CM CS CT DH and DL 2 Switch to the control mode using the port n mode control register PMCn If 1 above is no...

Page 679: ...O10 P10 Input mode PMC1 PFC1 P11 TCUD10 INTP100 P11 Input mode P12 TCLR10 INTP101 P12 Input mode PMC1 P13 TIUD11 TO11 P13 Input mode PMC1 PFC1 P14 TCUD11 INTP110 P14 Input mode Port 1 P15 TCLR11 INTP1...

Page 680: ...IT PCM0 Input mode WAIT PCM1 CLKOUT PCM1 Input mode CLKOUT PCM2 HLDAK PCM2 Input mode HLDAK PCM3 HLDRQ PCM3 Input mode HLDRQ PMCCM Port CM PCM4 PCM4 Input mode PCT0 LWR PCT0 Input mode LWR PCT1 UWR PC...

Page 681: ...r s Manual U14492EJ3V0UD 3 Port block diagrams Figure 14 1 Type A Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector...

Page 682: ...s Manual U14492EJ3V0UD Figure 14 2 Type B Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Noise elimination Edge detection Input signal in control mode Internal bus Selector Selector...

Page 683: ...UNCTIONS 683 User s Manual U14492EJ3V0UD Figure 14 3 Type C Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Remark m Port nu...

Page 684: ...PM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE2 Address Input signal in control mode Selector Selector Internal bus Remark m Port number n Bit number Figure 14 5 Type E Block Diagram WRPORT RDI...

Page 685: ...RDIN Pmn Address Noise elimination Edge detection 1 Input signal in control mode Internal bus Selector Figure 14 7 Type G Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control...

Page 686: ...UNCTIONS 686 User s Manual U14492EJ3V0UD Figure 14 8 Type H Block Diagram Internal bus Selector Selector WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Remark m Port nu...

Page 687: ...User s Manual U14492EJ3V0UD Figure 14 9 Type J Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector MODE0 to MODE2 Rema...

Page 688: ...M Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode SCKx ASCKy output enable signal Internal bus Selector Selector Selector Re...

Page 689: ...gure 14 11 Type N Block Diagram WRPFC WRPMC WRPM WRPORT RDIN PFCmn PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode Noise elimination Edge detection Internal bus S...

Page 690: ...Figure 14 12 Type O Block Diagram WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn Output signal in control mode MODE0 to MODE2 I O control I O control Address Input signal in control mode Selector Selector...

Page 691: ...Manual U14492EJ3V0UD Figure 14 13 Type P Block Diagram WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE2 Output signal in control mode I O control Address Selector Selector Internal bus Select...

Page 692: ...nput Although this port also serves as NMI ESO0 INTP0 ESO1 INTP1 ADTRG0 INTP2 ADTRG1 INTP3 and INTP4 to INTP6 NMI ESO0 INTP0 ESO1 INTP1 ADTRG0 INTP2 ADTRG1 INTP3 and INTP4 to INTP6 cannot be switched...

Page 693: ...Real time pulse unit RPU input or external interrupt request input B P13 TIUD11 TO11 Real time pulse unit RPU I O N P14 TCUD11 INTP110 Port 1 P15 TCLR11 INTP111 Real time pulse unit RPU input or exte...

Page 694: ...Function 5 PMC15 Specifies operation mode of P15 pin 0 I O port mode 1 TCLR11 input mode or external interrupt request INTP111 input mode 4 PMC14 Specifies operation mode of P14 pin 0 I O port mode 1...

Page 695: ...mode is specified by the port 1 mode control register PMC1 the setting of this register is invalid 7 0 PFC1 6 0 5 0 4 0 3 PFC13 2 0 1 0 0 PFC10 Address FFFFF462H Initial value 00H Bit Position Bit Nam...

Page 696: ...o TO24 INTP24 Real time pulse unit RPU output or external interrupt request input N P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 Real time pulse unit RPU input or external interrupt request input B Port 2 P2...

Page 697: ...me Function 7 PMC27 Specifies operation mode of P27 pin 0 I O port mode 1 TO3 output mode or external interrupt request INTP31 input mode 6 PMC26 Specifies operation mode of P26 pin 0 I O port mode 1...

Page 698: ...C2 the setting of this register is invalid 7 PFC27 PFC2 6 0 5 0 4 PFC24 3 PFC23 2 PFC22 1 PFC21 0 0 Address FFFFF464H Initial value 00H Bit Position Bit Name Function 7 PFC27 Specifies operation mode...

Page 699: ...in Name Remarks Block Type P30 RXD0 H P31 TXD0 G P32 RXD1 C P33 TXD1 A P34 ASCK1 M P35 RXD2 C P36 TXD2 A Port 3 P37 ASCK2 Serial interface UART0 to UART2 I O M 2 Setting in I O mode and control mode P...

Page 700: ...I O mode 6 PMC36 Specifies operation mode of P36 pin 0 I O port mode 1 TXD2 output mode 5 PMC35 Specifies operation mode of P35 pin 0 I O port mode 1 RXD2 input mode 4 PMC34 Specifies operation mode o...

Page 701: ...e Pin Name Remarks Block Type P40 SI0 C P41 SO0 A P42 SCK0 M P43 SI1 C P44 SO1 A P45 SCK1 M P46 CRXD C Port 4 P47 CTXD Serial interface CSI0 CSI1 FCAN I O A 2 Setting in I O mode and control mode Port...

Page 702: ...D output mode 6 PMC46 Specifies operation mode of P46 pin 0 I O port mode 1 CRXD input mode 5 PMC45 Specifies operation mode of P45 pin 0 I O port mode 1 SCK1 I O mode 4 PMC44 Specifies operation mode...

Page 703: ...on in control mode Port Alternate Pin Name Remarks Block Type Port DH PDH7 to PDH0 A23 to A16 Memory expansion address bus P 2 Setting in I O mode and control mode Port DH is set in I O mode using the...

Page 704: ...or 1 bit units 7 PMCDH7 PMCDH 6 PMCDH6 5 PMCDH5 4 PMCDH4 3 PMCDH3 2 PMCDH2 1 PMCDH1 0 PMCDH0 Address FFFFF046H Initial valueNote 00H FFH Note 00H Single chip mode 0 FFH Single chip mode 1 ROMless mode...

Page 705: ...PDL6 5 PDL5 4 PDL4 3 PDL3 2 PDL2 1 PDL1 0 PDL0 Address FFFFF005H Initial value Undefined Address FFFFF004H Bit Position Bit Name Function 15 to 0 PDLn n 15 to 0 I O port Besides functioning as a port...

Page 706: ...tput mode of PDLn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port DL mode control register PMCDL The PMCDL register can be read written in 16 bit units When using the higher 8...

Page 707: ...PCS3 2 PCS2 1 PCS1 0 PCS0 Address FFFFF008H Initial value Undefined Bit Position Bit Name Function 7 to 0 PCSn n 7 to 0 I O port Besides functioning as a port in control mode this can operate as the...

Page 708: ...FF028H Initial value FFH Bit Position Bit Name Function 7 to 0 PMCSn n 7 to 0 Specifies input output mode of PCSn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port CS mode contr...

Page 709: ...CT1 UWR Write strobe signal output J PCT2 PCT3 Fixed in port mode E PCT4 RD Read strobe signal output J PCT5 Fixed in port mode E PCT6 ASTB Address strobe signal output J Port CT PCT7 Fixed in port mo...

Page 710: ...alueNote 00H 53H Note 00H Single chip mode 0 53H Single chip mode 1 ROMless mode 0 or 1 Bit Position Bit Name Function 6 PMCCT6 Specifies operation mode of PCT6 pin 0 I O port mode 1 ASTB output mode...

Page 711: ...Block Type PCM0 WAIT Wait insertion signal input D PCM1 CLKOUT Internal system clock output J PCM2 HLDAK Bus hold acknowledge signal output J PCM3 HLDRQ Bus hold request signal input D Port CM PCM4 Fi...

Page 712: ...eNote 00H 0FH Note 00H Single chip mode 0 0FH Single chip mode 1 ROMless mode 0 or 1 Bit Position Bit Name Function 3 PMCCM3 Specifies operation mode of PCM3 pin 0 I O port mode 1 HLDRQ input mode 2 P...

Page 713: ...that changes in less than these elimination times is not accepted internally Pin Noise Elimination Time P00 NMI P01 ESO0 INTP0 P02 ESO1 INTP1 P03 ADTRG0 INTP2 P04 ADTRG1 INTP3 P05 INTP4 to P07 INTP6...

Page 714: ...0 INTP100 P12 TCLR10 INTP101 Timer 11 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 Select from fXXTM10 11 fXXTM10 11 2 fXXTM10 11 4 fXXTM10 11 8 P26 TI3 INTP30 TCLR3 Select from fXXTM3 2 fXXT...

Page 715: ...3 rising edge detection Timers 1 to 3 falling edge detection 2 clocks 2 clocks 5 clocks 5 clocks 4 clocks 4 clocks 3 clocks 3 clocks Caution If there are three or less noise elimination clocks while...

Page 716: ...0 0 fXXTM10 8 0 1 fXXTM10 4 1 0 fXXTM10 2 1 1 fXXTM10 1 0 NRC101 NRC100 Remark fXXTM10 Clock of TM10 selected by PRM02 register 2 Timer 11 noise elimination time selection register NRC11 The NRC11 re...

Page 717: ...32 1 NRC31 0 NRC30 Address FFFFF698H Initial value 00H Bit Position Bit Name Function Selects the TO3 INTP31 pin noise elimination clock NRC33 NRC32 Noise elimination clock 0 0 fXXTM3 256 0 1 fXXTM3 1...

Page 718: ...al Filter Pin Analog Filter Noise Elimination Time Noise Elimination Time Sampling Clock P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 10 to 100 ns 4 to 5 clocks fXXTM2 Cautions 1...

Page 719: ...ccur as soon as the PMC2 register is set n 0 to 5 1 2 7 DFEN00 FEM0 6 0 5 0 4 0 3 EDGE010 2 EDGE000 1 TMS010 0 TMS000 Address FFFFF630H Initial value 00H Address FFFFF631H Initial value 00H Address FF...

Page 720: ...liminator specification 1 0 Capture to sub channel 1 according to timer 1 1 Capture to sub channel 2 according to timer 1 0 TMS01n TMS00n Note Capture input according to INTCM100 and INTCM101 can be s...

Page 721: ...ull down resistor must be attached to each pin of ports DH DL CS CT and CM If there are no resistors the external memory that is connected may be destroyed when these pins become high impedance Simila...

Page 722: ...ernal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET pin 2 Reset at power on A reset operation at power on pow...

Page 723: ...C11H Peripheral area selection control register BPC 0000H Bus size configuration register BSC 0000H 5555H Bus control function System wait control register VSWC 77H Bus cycle type configuration regist...

Page 724: ...HS 00H Dead time timer reload register n DTRRn n 0 1 0FFFH Buffer registers CM0n CM1n BFCM0n BFCM1n n 0 to 3 FFFFH Timer control register 0n TMC0n n 0 1 0508H Timer control register 0nL TMC0nL n 0 1 0...

Page 725: ...H Timer 2 output control register 0H OCTLE0H 00H Timer 2 sub channel 0 5 capture compare control register CMSE050 0000H Timer 2 sub channel 1 2 capture compare control register CMSE120 0000H Timer 2 s...

Page 726: ...SIRBELn n 0 1 00H Clocked serial interface initial transmission buffer register n SOTBFn n 0 1 0000H Clocked serial interface initial transmission buffer register Ln SOTBFLn n 0 1 00H Serial I O shift...

Page 727: ...r CGINTP 00H CAN1 interrupt pending register C1INTP 00H CAN stop register CSTOP 0000H CAN global status register CGST 0100H CAN global interrupt enable register CGIE 0A00H CAN main clock selection reg...

Page 728: ...CDL 0000H FFFFH Mode control register PMCDLL 00H FFH Mode control register PMCDLH 00H FFH Mode control register PMCCT 00H 53H Mode control register PMCCM 00H 0FH Port function Function control registe...

Page 729: ...system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production is made easier 16 1 Features All area batch erase or erase in ar...

Page 730: ...53 128 VDD3 53 128 LVDDNote 3 CVDD 21 CVDD 21 VDD5 56 91 125 VDD5 56 91 125 AVREF0 137 AVREF0 137 AVREF1 4 AVREF1 4 MODE1 27 MODE1 27 VDD AVDD 2 135 AVDD 2 135 VSS3 54 127 VSS3 54 127 VSS5 55 90 126...

Page 731: ...face between the dedicated flash programmer and the V850E IA1 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing Supply the operating clock of the V...

Page 732: ...V850E IA1 board using a resonator and a capacitor The dedicated flash programmer outputs transfer clocks and the V850E IA1 operates as a slave 3 Handshake supported CSI communication Transfer rate up...

Page 733: ...ming mode 7 8 V writing voltage is supplied to the VPP pin The following shows an example of the connection of the VPP pin Figure 16 5 Connection Example of VPP Pin V850E IA1 VPP Pull down resistor RV...

Page 734: ...ut or output connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or make the setting so...

Page 735: ...gnal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side 16 5 4 NMI pin Do not change the input signal to the NMI pin in flash memory programming mo...

Page 736: ...DD5 and VSS5 VDD of the dedicated flash programmer is provided with a power supply monitoring function Note Connect VDD after converting the power supply to 3 3 V using a regulator 16 6 Programming Me...

Page 737: ...Memory Programming Mode n 1 Flash memory programming mode MODE0 to MODE2 010 011 7 8 V VPP 3 3 V 0 V RESET 2 16 6 3 Selection of communication mode In the V850E IA1 a communication mode is selected by...

Page 738: ...command Compares the contents of the specified area and the input data Batch erase command Erases the contents of the entire memory Area erase command Erases the contents of the specified area Erase...

Page 739: ...programming Self programming implements erasure and writing of the flash memory by calling the self programming function device s internal processing on the program placed in the block 0 space 000000H...

Page 740: ...area in which an over erase occurred Acquire information Flash memory information read Reads out information about flash memory 16 7 3 Outline of self programming interface To execute self programming...

Page 741: ...lash memory a high voltage must be applied to the VPP pin To execute self programming a circuit that can generate a write voltage VPP and that can be controlled by software is necessary on the applica...

Page 742: ...mory starts until manipulation is complete Cautions 1 Apply 0 V to the VPP pin when reset is released 2 Implement self programming in single chip mode 0 or 1 3 Apply the voltage to the VPP pin in the...

Page 743: ...er while the flash memory is being manipulated Because the internal timer is initialized after the flash memory has been used initialize the timer with the application program to use the timer again S...

Page 744: ...ction numbers are used as parameters when the device internal processing is called Table 16 8 Self Programming Function Number Function No Function Name 0 Acquiring flash information 1 Erasing area 2...

Page 745: ...fy start address Number of bytes to be verified 0 Normal completion Other than 0 Error Erase verify 10 None acts on erase manipulation area immediately before 0 Normal completion Other than 0 Error Co...

Page 746: ...If write back time is 1 ms 1 1 000 100 10 integer operation ep 0x10 2 bytes Input Timer set value for creating internal operation unit time unsigned 2 bytes Write a set value that makes the value of...

Page 747: ...tion For the flash information acquisition function function No 0 the option number r7 to be specified and the contents of the return value r10 are as follows To acquire all flash information call the...

Page 748: ...number The area numbers and memory map of the PD70F3116 are shown below Figure 16 16 Area Configuration Area 1 128 KB Area 0 128 KB 0 x 3 F F F F End address of area 1 0 x 0 0 0 0 0 Start address of a...

Page 749: ...disables writing erasing on chip flash memory When this bit is 1 writing erasing on chip flash memory is disabled even if a high voltage is applied to the VPP pin 0 Enables writing erasing flash memor...

Page 750: ...MC r0 5 NOP 6 NOP 7 NOP 8 NOP 9 NOP 10 LDSR rY 5 Remark rX Value written to the PSW rY Value returned to the PSW No special sequence is required for reading a specific register Cautions 1 If an interr...

Page 751: ...lash memory FLSPM bit 0 to select normal operation mode 7 Wait for the internal manipulation setup time see 16 7 13 5 Internal manipulation setup parameter 1 Parameter r6 First argument sets a self pr...

Page 752: ...pulation setup parameter EntryProgram add 4 sp Prepare st w lp 0 sp Save return address movea lo 0x00a0 r0 r10 ldsr r10 5 PSW NP ID mov lo 0x0002 r10 st b r10 PHCMD r0 PHCMD 2 st b r10 FLPMC r0 VPPDIS...

Page 753: ...h memory In the program example in 4 above the elapse of this wait time is ensured by setting ISETUP to 130 50 MHz operation The total number of execution clocks in this example is 39 clocks divh inst...

Page 754: ...et RAM parameter Mask interrupts Pre write Erase area Erase byte verify Erase verify Area write back Erase verify Clear number of times write back is repeated Erase byte verify Write error Undererase...

Page 755: ...data in word units is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 18 Continuous Writing Flow Function No 16 Y...

Page 756: ...processing of each function number must be executed in accordance with the specified calling procedure Figure 16 19 Internal Verify Flow Function No 21 Yes No Internal verify Mask interrupts Set VPP v...

Page 757: ...formation is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 20 Acquiring Flash Information Flow Function No 0 Ac...

Page 758: ...odule is located in area 0 and the data in area 1 is rewritten or erased The rewriting module is a user program to rewrite the flash memory The other areas can be also rewritten by using the flash fun...

Page 759: ...the self programming library is outlined below Figure 16 22 Outline of Self Programming Library Configuration Application program Entry program RAM parameter Device internal processing Flash memory Se...

Page 760: ...NOP 9 LDSR rY 5 10 TST1 3 FLPMC r0 BNZ Start address of self programming routine BR Routine when writing is not performed Remark rX Value written to the PSW rY Value returned to the PSW Cautions 1 If...

Page 761: ...AVDD pins at 0 V until the voltage on the VDD3 pin rises to the level at which the operation is guaranteed 3 0 to 3 6 V To turn OFF Keep the voltage on the VDD3 pin at the level at which the operation...

Page 762: ...f the voltage on the VDD3 pin drops below the level at which the operation is guaranteed 3 0 to 3 6 V before the voltage on the VDD5 and AVDD pins drops to 0 V the status of the I O pin is undefined N...

Page 763: ...in when VDD3 is supplied 0 5 to 6 0 V Clock input voltage VK X1 pin 0 5 to VDD3 1 0Note 1 V AVDD VDD5 0 5 to VDD5 0 5Note 1 V Analog input voltage VIAN ANI00 to ANI07 pins ANI10 to ANI17 pins VDD5 AVD...

Page 764: ...V 4 5 V 4 5 V VPP VDD3 VDD5 VPP 0 V 3 0 V 3 0 V a a b b Cautions 1 Do not directly connect output or I O pins of IC products to each other or to VDD VCC and GND Open drain pins or open collector pins...

Page 765: ...ternal System Clock Frequency fXX Operating Ambient Temperature TA VDD3 VDD5 PD703116 703116 A 70F3116 70F3116 A 4 to 25 MHz 40 to 85 C 3 3 V 0 3 V 5 0 V 0 5 V Direct mode PD703116 A1 70F3116 A1 4 to...

Page 766: ...lose to the X1 and X2 pins as possible 2 Do not wire any other signal lines in the area indicated by the broken lines 3 For the resonator selection and oscillator constant customers are required to ei...

Page 767: ...chip 0 3 0 3 6 Surface mount CSTCR6M00G55 R0 6 0 On chip On chip 0 3 0 3 6 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manu...

Page 768: ...RESET pin 0 0 2VDD3 V VOH1 Pins other than Note 4 IOH 2 5 mA VDD5 1 0 V Output voltage high VOH2 Pins for NBDNote 4 IOH 2 5 mA VDD3 1 0 V IOL 15 mA 2 0 V VOL1 PWM outputNote 5 IOL 2 5 mA 0 4 V VOL2 Pi...

Page 769: ...5 Note 3 20 40 mA VDD3 CVDD Note 2 1 2fXX 2 3fXX mA In HALT mode IDD2 PD70F3116 VDD5 Note 3 20 40 mA VDD3 CVDD 3 0 10 mA In IDLE mode IDD3 VDD5 Note 3 0 5 2 0 mA 40 C TA 85 C 20 1200 A VDD3 CVDD 40 C...

Page 770: ...DR VDDDR V Note 2 0 0 2HVDDDR V Data retention input voltage low VILDR Note 3 0 0 2VDDDR V Notes 1 The current of the TO000 to TO005 and TO010 to TO015 pins is not included 2 P00 NMI P01 ESO0 INTP0 P0...

Page 771: ...Other than b to d below b AD0 PDL0 to AD15 PDL15 A16 PDH0 to A23 PDH7 LWR PCT0 UWR PCT1 PCT2 PCT3 RD PCT4 PCT5 ASTB PCT6 PCT7 WAIT PCM0 CLKOUT PCM1 HLDAK PCM2 HLDRQ PCM3 PCM4 CS0 PCS0 to CS7 PCS7 pin...

Page 772: ...PD70F3116 only Load conditions Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration insert a buffer or other element to reduce the device s load capacitan...

Page 773: ...t low level width 3 tWXL PLL mode 50 ns Direct mode 4 ns X1 input rise time 4 tXR PLL mode 10 ns Direct mode 4 ns X1 input fall time 5 tXF PLL mode 10 ns Note 2 4 50 MHz Note 1 4 32 MHz CPU operation...

Page 774: ...F3116 70F3116 A TA 40 to 110 C PD703116 A1 70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit Output rise...

Page 775: ...5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit RESET pin high level width 14 tWRSH 500 ns At power on and at STOP mode release 500 TOST ns RESET p...

Page 776: ...wAS T 15 ns Data output time from LWR UWR 28 tDWROD 10 ns Data output setup time to LWR UWR 29 tSODWR 1 w T 25 ns Data output hold time from LWR UWR 30 tHWROD T 20 ns 31 tSAWT1 w 1 1 5 wAS wAH T 40 ns...

Page 777: ...T to ASTB 47 tDKST 3 wAHT 19 wAHT ns Delay time from CLKOUT to RD LWR UWR 48 tDKRDWR 5 19 ns Data input setup time to CLKOUT 49 tSIDK 21 ns Data input hold time from CLKOUT 50 tHKID 5 ns Delay time fr...

Page 778: ...CLKOUT synchronous asynchronous 1 wait Remark LWR and UWR are high level 21 CLKOUT output A16 to A23 output RD output AD0 to AD15 I O ASTB output WAIT input T1 T2 TW T3 Data Address Hi Z 45 19 46 47...

Page 779: ...rite cycle CLKOUT synchronous asynchronous 1 wait Remark RD is high level CLKOUT output AD0 to AD15 I O ASTB output LWR output UWR output A16 to A23 output WAIT input T1 T2 TW T3 Data Address 45 51 47...

Page 780: ...S 780 User s Manual U14492EJ3V0UD e Bus hold CLKOUT output HLDRQ input HLDAK output A16 to A23 output AD0 to AD15 I O ASTB output RD output LWR output UWR output TH TH TH TI Hi Z Hi Z Hi Z Data Hi Z 5...

Page 781: ...ers INTP100 INTP101 Can be selected from fXXTM10 fXXTM10 2 fXXTM10 4 and fXXTM10 8 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time selection register NRC10 fXXTM10 clock s...

Page 782: ...setting the following registers When using TIUDn TCUDn and TCLRn n 10 11 the following cycles can be selected by setting the NRCn1 and NRCn0 bits of timer n noise elimination time selection register N...

Page 783: ...Parameter Symbol Conditions MIN MAX Unit SCKn cycle 66 tCYSK1 Output 200 ns SCKn high level width 67 tWSK1H Output 0 5tCYSK1 25 ns SCKn low level width 68 tWSK1L Output 0 5tCYSK1 25 ns SIn setup time...

Page 784: ...VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit UART0 baud rate generator input frequency fBRG 25 MHz Remark fBRG UART0 baud rate generator input frequency...

Page 785: ...TX T 10 ns TXDn output hold time from ASCKn 79 tHSKTX k 1 T 20 ns Remarks 1 T 2tCYK 2 k Setting value of prescaler compare register n PRSCMn of UARTn 3 n 1 2 b Clocked slave mode TA 40 to 85 C PD70311...

Page 786: ...CHAPTER 18 ELECTRICAL SPECIFICATIONS 786 User s Manual U14492EJ3V0UD 10 UART1 UART2 timing 2 2 Remark n 1 2 73 75 74 76 77 78 79 RXDn input TXDn output ASCKn I O Output data Input data...

Page 787: ...itions MIN MAX Unit NBD cycle 80 tNDCYC 80 ns NBD cycle low level width 81 tNDL 35 ns NBD data output delay time 82 tNDD 5 tNDCYC 20 ns NBD data output hold time 83 tNDHD 2 ns NBD data input setup tim...

Page 788: ...tization error 1 2 LSB Conversion time tCONV 5 10 s Sampling time tSAMP 833 ns Zero scale errorNote 1 3 LSB Full scale errorNote 1 3 LSB Differential linearity errorNote 1 3 LSB Integral linearity err...

Page 789: ...ng time tWT Note 5 18 20 22 s Overall writing time per word tWTW When the step writing time 20 s 1 word 4 bytes Note 6 20 200 s word Number of rewrites per area CERWR 1 erase 1 write after erase 1 rew...

Page 790: ...tDRPSR 10 s VPP to RESET set time 89 tPSRRF 1 s RESET to VPP count start time 90 tRFOF VPP 7 8 V 10T 1500 ns Count execution time 91 tCOUNT 15 ms VPP counter high level width 92 tCH 1 s VPP counter l...

Page 791: ...E A 22 0 0 2 B 20 0 0 2 C 20 0 0 2 D F 1 25 22 0 0 2 S144GJ 50 UEN S 1 5 0 1 K 1 0 0 2 L 0 5 0 2 R 3 4 3 G 1 25 H 0 22 0 05 I 0 08 J 0 5 T P M 0 17 N 0 08 P 1 4 Q 0 10 0 05 0 03 0 07 Each lead centerl...

Page 792: ...PD70F3116GJ UEN 144 pin plastic LQFP fine pitch 20 20 PD70F3116GJ A UEN 144 pin plastic LQFP fine pitch 20 20 PD70F3116GJ A1 UEN 144 pin plastic LQFP fine pitch 20 20 Soldering Method Soldering Condi...

Page 793: ...Pin Plastic LQFP Fine Pitch 20 20 Side view Target system NQPACK144SD YQPACK144SD 206 26 mm Note In circuit emulator option board Conversion connector IE 703116 MC EM1 In circuit emulator IE V850E MC...

Page 794: ...654 ADETM0 A D voltage detection mode register 0 ADC 653 ADETM0H A D voltage detection mode register 0H ADC 653 ADETM0L A D voltage detection mode register 0L ADC 653 ADETM1 A D voltage detection mod...

Page 795: ...ter CM11 RPU 232 BFCM12 Buffer register CM12 RPU 232 BFCM13 Buffer register CM13 RPU 233 BPC Peripheral area selection control register CPU 93 BRGC0 Baud rate generator control register 0 UART0 440 BS...

Page 796: ...381 CC31 Capture compare register 31 RPU 381 CC3IC0 Interrupt control register INTC 179 CC3IC1 Interrupt control register INTC 179 CCINTP CAN interrupt pending register FCAN 566 CCR0 Capture compare c...

Page 797: ...capture register RPU 358 CSE0 Timer 2 count clock control edge selection register 0 RPU 344 CSE0H Timer 2 count clock control edge selection register 0H RPU 344 CSE0L Timer 2 count clock control edge...

Page 798: ...gister 1H DMAC 142 DDA1L DMA destination address register 1L DMAC 143 DDA2H DMA destination address register 2H DMAC 142 DDA2L DMA destination address register 2L DMAC 143 DDA3H DMA destination addres...

Page 799: ...filter mode register 5 RPU 191 719 FLPMC Flash programming mode control register CPU 749 IMR0 Interrupt mask register 0 INTC 182 IMR0H Interrupt mask register 0H INTC 182 IMR0L Interrupt mask registe...

Page 800: ...ister DH NBD 639 NBDMDL DMA destination address setting register DL NBD 639 NBDMSH DMA source address setting register SH NBD 638 NBDMSL DMA source address setting register SL NBD 638 NRC10 Timer 10 n...

Page 801: ...control register Port 702 PMCCM Port CM mode control register Port 712 PMCCS Port CS mode control register Port 708 PMCCT Port CT mode control register Port 710 PMCDH Port DH mode control register Po...

Page 802: ...egister 11 INTC RPU 187 312 SESC Valid edge selection register INTC RPU 190 388 SESE0 Timer 2 sub channel input event edge selection register 0 RPU 345 SESE0H Timer 2 sub channel input event edge sele...

Page 803: ...C2 Interrupt control register INTC 179 STOPTE0 Timer 2 clock stop register 0 RPU 343 STOPTE0H Timer 2 clock stop register 0H RPU 343 STOPTE0L Timer 2 clock stop register 0L RPU 343 TBSTATE0 Timer 2 ti...

Page 804: ...on selection register 0 RPU 413 TOMR0 Timer output mode register 0 RPU 242 TOMR1 Timer output mode register 1 RPU 242 TUC00 Timer unit control register 00 RPU 241 TUC01 Timer unit control register 01...

Page 805: ...bit data that specifies a trap vector 00H to 1FH cccc 4 bit data that shows a condition code sp Stack pointer r3 ep Element pointer r30 list X item register list 2 Symbols used in operands Symbol Exp...

Page 806: ...If n is a computation result and n 80000000H make n 80000000H result Reflect result in flag Byte Byte 8 bits Half word Halfword 16 bits Word Word 32 bits Addition Subtraction Bit concatenation Multipl...

Page 807: ...NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY or Z 1 Not hig...

Page 808: ...turn PC CTPSW PSW adr CTBP zero extend imm6 logically shift left by 1 PC CTBP zero extend Load memory adr Halfword 5 5 5 1 0 b b b 1 1 1 1 1 0 R R R R R bit 3 disp16 reg1 d d d d d d d d d d d d d d d...

Page 809: ...GR reg1 GR reg3 GR reg2 GR reg1 34 34 34 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 EI 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 PSW ID 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 HALT 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 Stop 1...

Page 810: ...1 1 1 1 R R R R R reg1 reg2 reg3 w w w w w 0 1 0 0 0 1 0 0 0 1 0 GR reg3 GR reg2 GR reg2 GR reg1 reg1 reg2 reg3 reg3 r0 1 2 Note 14 2 r r r r r 1 1 1 1 1 1 i i i i i MULU imm9 reg2 reg3 w w w w w 0 1...

Page 811: ...eg2 saturated GR reg1 GR reg2 1 1 1 r r r r r 1 1 1 1 1 1 0 c c c c SETF cccc reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H 1 1 1 0 0 b...

Page 812: ...r r r 0 0 1 1 0 1 R R R R R GR reg2 GR reg2 GR reg1 1 1 1 SUBR reg1 reg2 r r r r r 0 0 1 1 0 0 R R R R R GR reg2 GR reg1 GR reg2 1 1 1 SWITCH reg1 0 0 0 0 0 0 0 0 0 1 0 R R R R R adr PC 2 GR reg1 log...

Page 813: ...n this instruction although the source register is regarded as reg2 for convenience of the mnemonic description the reg1 field is used in the opcode Therefore the meanings of register specifications a...

Page 814: ...mple timer 4 411 application examples timer 3 396 applications 33 arbitration field 533 area 73 area number 748 ASCK1 ASCK2 51 ASIF0 422 ASIM0 418 ASIM10 ASIM20 449 ASIM11 ASIM21 451 ASIS0 421 ASIS1 A...

Page 815: ...to H31 558 CAN message search start result register 577 CAN message status registers 00 to 31 562 CAN message time stamp registers 00 to 31 555 CAN sleep mode 541 614 CAN status set clear registers 00...

Page 816: ...CM110 304 CM101 CM111 304 CM10IC0 CM10IC1 179 CM11IC0 CM11IC1 179 CM4 406 CM4IC0 179 CMSE050 350 CMSE120 351 CMSE340 353 command register 215 communication commands 738 communication mode 731 compare...

Page 817: ...02 231 DTM10 to DTM12 231 DTRR0 DTRR1 231 DWC0 DWC1 124 E ECR 65 edge detection function 171 electrical specifications 763 element pointer 64 end of frame 536 entry program 740 EP 196 error active 537...

Page 818: ...t of pin functions 41 lock register 211 LOCKR 211 LWR 54 M M_CONF00 to M_CONF31 560 M_CTRL00 to M_CTRL31 552 M_DATAn0 to M_DATAn7 n 00 to 31 556 M_DLC00 to M_DLC31 550 M_IDL00 to M_IDL31 and M_IDH00 t...

Page 819: ...gister 210 PFC1 695 PFC2 698 PHCMD 207 PHS 210 pin configuration 35 pin I O circuits 61 pin status 47 PLL lockup 211 PLL mode 206 212 PM1 693 PM2 696 PM3 699 PM4 701 PMC1 694 PMC2 697 PMC3 700 PMC4 70...

Page 820: ...STO1 248 PSW 66 PWM mode 0 259 PWM mode 1 267 PWM mode 2 280 PWM output enable registers 0 1 247 PWM software timing output registers 0 1 248 Q quantization error 674 R r0 to r31 64 RAM 38 RAM access...

Page 821: ...0L 346 TCUD10 TCUD11 49 text pointer 64 TI2 TI3 50 TID0 to TID2 636 time base counter 225 time stamp function 524 timer 0 226 timer 0 clock selection register 234 timer 1 298 timer 10 noise eliminatio...

Page 822: ...015 56 TO10 TO11 49 TO21 to TO24 50 TO3 50 TOMR write enable registers 0 1 257 TOMR0 TOMR1 242 transfer mode 154 transfer object 158 transfer type and transfer object 158 transfer types 157 transmissi...

Page 823: ...in 2 4 Types of Pin I O Circuit and Connection of Unused Pins Modification of I O circuit type from 5 K to 5 AC in 2 5 Pin I O Circuits CHAPTER 2 PIN FUNCTIONS Modification of description in 3 4 5 1 a...

Page 824: ...and addition of bit names and bit description in 6 3 8 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 Addition of description in 6 5 1 Single transfer mode Addition of description in 6 5 2 Single...

Page 825: ...fication of description and modification of timing chart in 8 6 1 1 Securing the time using an on chip time base counter Modification of timing chart in 8 6 1 2 Securing the time according to the sign...

Page 826: ...control edge selection register 0 CSE0 Modification of description on bits that can be manipulated in 9 3 4 4 Timer 2 sub channel input event edge selection register 0 SESE0 Modification of descriptio...

Page 827: ...ion of description in table in Figure 10 5 Continuous Transmission Starting Procedure Modification of description in table in Figure 10 6 Continuous Transmission End Procedure Addition of Caution in F...

Page 828: ...11 8 7 1 Prescaler Modification of description in 11 8 7 2 Nominal bit time 8 to 25 time quantum Addition of Caution and modification of bit description in 11 10 2 CAN message data length registers 00...

Page 829: ...n 11 17 Cautions on Use CHAPTER 11 FCAN CONTROLLER Addition of description in 12 1 2 Event detection function Modification of Figure 12 1 Image of NBD Space Addition of description in 12 4 1 1 b Read...

Page 830: ...lock type in 14 3 10 1 Operation in control mode Addition of Caution and addition of Caution in bit description in 14 4 3 1 Timer 2 input filter mode registers 0 to 5 FEM0 to FEM5 CHAPTER 14 PORT FUNC...

Page 831: ...A destination address registers 0H to 3H DDA0H to DDA3H Addition of description to 6 3 3 DMA transfer count registers 0 to 3 DBC0 to DBC3 Addition of description to 6 3 4 DMA addressing control regist...

Page 832: ...each port Modification of description in Figure 14 14 Example of Noise Elimination Timing CHAPTER 14 PORT FUNCTIONS Addition of CHAPTER 18 ELECTRICAL SPECIFICATIONS CHAPTER 18 ELECTRICAL SPECIFICATIO...

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