CHAPTER 11 FCAN CONTROLLER
562
User’s Manual U14492EJ3V0UD
(8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)
The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to
31).
These registers are read-only in 8-bit units.
Cautions 1. Writing directly to M_STATn register cannot be performed. Writing must be performed
using CAN status set/clear register n (SC_STATn).
2. Messages are transmitted only when the M_STATn register’s TRQ and RDY bits have
been set (to 1).
7
0
M_STATn
(n = 00 to 31)
6
0
5
0
4
0
3
0
2
DN
1
TRQ
0
RDY
Note
Address
See
Table 11-21
Initial value
Undefined
Note
The FCAN controller incorporated in the V850E/IA1 can receive messages even if RDY bit is not set.
However, there are some products other than the V850E/IA1 that cannot receive messages without the
RDY setting. Be sure to set RDY bit before a receive operation even when using the V850E/IA1’s
FCAN controller to retain software compatibility.
Bit Position
Bit Name
Function
2
DN
This is the message update flag.
0: No message was received after DN bit was cleared.
1: At least one message was received after DN bit was cleared.
•
When the DN bit has been set (to 1) by the transmit message buffer, it indicates that the
message buffer has received a remote frame.
When this message is sent, the DN bit is automatically cleared (to 0).
•
When a frame is again received in the receive message buffer for which the DN bit has
been set (to 1), an overwrite condition occurs and the M_CTRLn register’s MOVR bit is
set (to 1) (n = 00 to 31).
1
TRQ
This is the transmit request flag.
0: Message transmission disabled
1: Message transmission enabled
A remote frame is transmitted for the receive message buffer in which the TRQ bit is set to 1.
0
RDY
This is the transmit message ready flag.
0: Transmit message is not ready.
1: Transmit message is ready.
•
A receive operation is performed only for a message buffer in which the RDY bit is set to
1 during reception.
•
A transmit operation is performed only for a message buffer in which the RDY bit is set to
1 and the TRQ bit is set to 1 during transmission.
