CHAPTER 3 CPU FUNCTION
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User’s Manual U14492EJ3V0UD
3.4.5
Area
(1) Internal ROM/internal flash memory area
(a) Memory map
Up to 1 MB of internal ROM/internal flash memory area is reserved.
256 KB are provided in the following addresses as physical internal ROM (mask ROM/flash memory).
•
In single-chip mode 0: Addresses 000000H to 03FFFFH
(addresses 040000H to 0FFFFFH are undefined)
•
In single-chip mode 1: Addresses 0100000H to 013FFFFH
(addresses 0140000H to 01FFFFFH are undefined)
Figure 3-4. Internal ROM/Internal Flash Memory Area
Undefined
Undefined
Internal ROM/
internal flash
memory area
Internal ROM/
internal flash
memory area
Single-chip mode 0
Single-chip mode 1
0FFFFFH
040000H
000000H
03FFFFH
1FFFFFH
140000H
100000H
13FFFFH
(b) Interrupt/exception table
The V850E/IA1 increases the interrupt response speed by assigning handler addresses corresponding to
interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the
internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the
handler address, and the program written at that memory is executed. Table 3-3 shows the sources of
interrupts/exceptions, and the corresponding addresses.
Remark
When in ROMless modes 0, 1, or in single-chip mode 1, in order to resume correct operation
after reset, provide a handler address to the reset routine in address 0 of the external memory.
