CHAPTER 15 RESET FUNCTION
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User’s Manual U14492EJ3V0UD
Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/6)
On-Chip Hardware
Register Name
Initial Value After Reset
Signal edge selection register n (SESA1n) (n = 10, 11)
00H
Valid edge selection register (SESC)
00H
Timer 2 input filter mode register n (FEMn) (n = 0 to 5)
00H
Interrupt/exception
control function
Interrupt control registers (P0IC0 to P0IC6, DETIC0, DETIC1,
TM0IC0, CM03IC0, TM0IC1, CM03IC1, CC10IC0, CC10IC1,
CM10IC0, CM10IC1, CC11IC0, CC11IC1, CM11IC0, CM11IC1,
TM2IC0, TM2IC1, CC2IC0 to CC2IC5, TM3IC0, CC3IC0, CC3IC1,
CM4IC0, DMAIC0 to DMAIC3, CANIC0 to CANIC3, CSIIC0, CSIIC1,
SRIC0 to SRIC2, STIC0 to STIC2, SEIC0, ADIC0, ADIC1)
47H
Command register (PRCMD)
Undefined
Power save control register (PSC)
00H
Clock control register (CKC)
00H
Power save mode register (PSMR)
00H
Power save
control function
Lock register (LOCKR)
0000000xB
Peripheral command register (PHCMD)
Undefined
System control
Peripheral status register (PHS)
00H
Dead-time timer reload register n (DTRRn) (n = 0, 1)
0FFFH
Buffer registers CM0n, CM1n (BFCM0n, BFCM1n) (n = 0 to 3)
FFFFH
Timer control register 0n (TMC0n) (n = 0, 1)
0508H
Timer control register 0nL (TMC0nL) (n = 0, 1)
08H
Timer control register 0nH (TMC0nH) (n = 0, 1)
05H
Timer unit control register 0n (TUC0n) (n = 0, 1)
01H
Timer output mode register n (TOMRn) (n = 0, 1)
00H
PWM software timing output register n (PSTOn) (n = 0, 1)
00H
PWM output enable register n (POERn) (n = 0, 1)
00H
TOMR write enable register n (SPECn) (n = 0, 1)
0000H
Timer 0
Timer 0 clock selection register (PRM01)
00H
Timer 1n (TM1n) (n = 0, 1)
0000H
Compare register 1n (CM1n) (n = 00, 01, 10, 11)
0000H
Capture/compare register 1n (CC1n) (n = 00, 01, 10, 11)
0000H
Capture/compare control register n (CCRn) (n = 0, 1)
00H
Timer unit mode register n (TUMn) (n = 0, 1)
00H
Timer control register 1n (TMC1n) (n = 0, 1)
00H
Signal edge selection register 1n (SESA1n) (n = 0, 1)
00H
Prescaler mode register 1n (PRM1n) (n = 0, 1)
07H
Status register n (STATUSn) (n = 0, 1)
00H
Timer connection selection register 0 (TMIC0)
00H
Timer 1/timer 2 clock selection register (PRM02)
00H
CC1n1 capture input selection register (CSL1n) (n = 0, 1)
00H
On-chip
peripheral
I/O
Timer 1
Timer 1n noise elimination time selection register (NRC1n) (n = 0, 1)
00H
