NEC V850E/IA1 mPD703116, User Manual

Page: 81 / 832

CHAPTER 3 CPU FUNCTION
81
User’s Manual U14492EJ3V0UD
3.4.8 On-chip peripheral I/O registers
(1/11)
Bit Units for Manipulation Address Function Register Name Symbol R/W
1 Bit 8 Bits 16 Bits
Initial Value
FFFFF004H Port DL PDL R/W
√
Undefined
FFFFF004H Port DLL PDLL R/W
√ √
Undefined
FFFFF005H Port DLH PDLH R/W
√ √
Undefined
FFFFF006H Port DH PDH R/W
√ √
Undefined
FFFFF008H Port CS PCS R/W
√ √
Undefined
FFFFF00AH Port CT PCT R/W
√ √
Undefined
FFFFF00CH Port CM PCM R/W
√ √
Undefined
FFFFF024H Port DL mode register PMDL R/W
√
FFFFH
FFFFF024H Port DL mode register L PMDLL R/W
√ √
FFH
FFFFF025H Port DL mode register H PMDLH R/W
√ √
FFH
FFFFF026H Port DH mode register PMDH R/W
√ √
FFH
FFFFF028H Port CS mode register PMCS R/W
√ √
FFH
FFFFF02AH Port CT mode register PMCT R/W
√ √
FFH
FFFFF02CH Port CM mode register PMCM R/W
√ √
FFH
FFFFF044H Port DL mode control register PMCDL R/W
√
0000H/FFFFH
FFFFF044H Port DL mode control register L PMCDLL R/W
√ √
00H/FFH
FFFFF045H Port DL mode control register H PMCDLH R/W
√ √
00H/FFH
FFFFF046H Port DH mode control register PMCDH R/W
√ √
00H/FFH
FFFFF048H Port CS mode control register PMCCS R/W
√ √
00H/FFH
FFFFF04AH Port CT mode control register PMCCT R/W
√ √
00H/53H
FFFFF04CH Port CM mode control register PMCCM R/W
√ √
00H/0FH
FFFFF060H Chip area selection control register 0 CSC0 R/W
√
2C11H
FFFFF062H Chip area selection control register 1 CSC1 R/W
√
2C11H
FFFFF064H Peripheral area selection control register BPC R/W
√
0000H
FFFFF066H Bus size configuration register BSC R/W
√
0000H/5555H
FFFFF06EH System wait control register VSWC R/W
√
77H
FFFFF080H DMA source address register 0L DSA0L R/W
√
Undefined
FFFFF082H DMA source address register 0H DSA0H R/W
√
Undefined
FFFFF084H DMA destination address register 0L DDA0L R/W
√
Undefined
FFFFF086H DMA destination address register 0H DDA0H R/W
√
Undefined
FFFFF088H DMA source address register 1L DSA1L R/W
√
Undefined
FFFFF08AH DMA source address register 1H DSA1H R/W
√
Undefined
FFFFF08CH DMA destination address register 1L DDA1L R/W
√
Undefined
FFFFF08EH DMA destination address register 1H DDA1H R/W
√
Undefined
FFFFF090H DMA source address register 2L DSA2L R/W
√
Undefined
FFFFF092H DMA source address register 2H DSA2H R/W
√
Undefined