CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
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User’s Manual U14492EJ3V0UD
(2) Compare registers 100, 110 (CM100, CM110)
CM1n0 is a 16-bit register that always compares its value with the value of TM1n. When the value of a
compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing
in the various modes is described below.
•
In the general-purpose timer mode (CMD bit of TUMn register = 0) and UDC mode A (MSEL bit of TUMn
register = 0), an interrupt signal (INTCM1n0) is always generated upon occurrence of a match.
•
In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM1n0) is generated only upon
occurrence of a match during up count operation.
CM1n0 can be read/written in 16-bit units.
Caution
When the TM1CEn bit of the TMC1n register is “1”, it is prohibited to overwrite the value of
the CM1n0 register.
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CM100
Address
FFFFF5E2H
Initial value
0000H
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CM110
Address
FFFFF602H
Initial value
0000H
(3) Compare registers 101, 111 (CM101, CM111)
CM1n1 is a 16-bit register that always compares its value with the value of TM1n. When the value of a
compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing
in the various modes is described below.
•
In the general-purpose timer mode (CMD bit of TUMn register = 0) and UDC mode A (MSEL bit of TUMn
register = 0), an interrupt signal (INTCM1n1) is always generated upon occurrence of a match.
•
In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM1n1) is generated only upon
occurrence of a match during down count operation.
CM1n1 can be read/written in 16-bit units.
Caution
When the TM1CEn bit of the TMC1n register is “1”, it is prohibited to overwrite the value of
the CM1n1 register.
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CM101
Address
FFFFF5E4H
Initial value
0000H
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CM111
Address
FFFFF604H
Initial value
0000H
