APPENDIX E REVISION HISTORY
User’s Manual U14492EJ3V0UD
831
(9/10)
Edition
Major Revision from Previous Edition
Applied to:
Addition of 16.7.16 Internal verify flow
Addition of 16.7.17 Acquiring flash information flow
Addition of 16.7.18 Self-programming library
Modification of Caution in 16.8 How to Distinguish Flash Memory and Mask ROM
Versions
CHAPTER 16
FLASH MEMORY
(
µ
PD70F3116)
Addition of CHAPTER 17 TURNING ON/OFF POWER
CHAPTER 17
TURNING ON/OFF
POWER
2nd
edition
Modification of description in B.2 Instruction Set (Alphabetical Order)
APPENDIX B
INSTRUCTION
SET LIST
Modification of description in 4.2.1 Pin status during internal ROM, internal RAM, and on-
chip peripheral I/O access
CHAPTER 4 BUS
CONTROL
FUNCTION
Addition of description to 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
Addition of description to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to
DSA3H)
Addition of description to 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
Addition of description to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H
to DDA3H)
Addition of description to 6
.
3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
Addition of description to 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to
DADC3)
Addition of description to 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
Addition and modification of description in 6.3.6 DMA disable status register (DDIS)
Addition of description to 6.3.7 DMA restart register (DRST)
Addition of description to 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
Modification of description in Table 6-1 Relationship Between Transfer Type and Transfer
Object
Modification of description in Remark in 6.7.1 Transfer type and transfer object
Modification and addition of description in 6.9 Next Address Setting Function
Modification of description in 6.11 Forcible Interruption
Modification of description in 6.14 (4) Bus arbitration for CPU
Addition of 6.14 (6) Execution of program and DMA transfer in internal RAM
CHAPTER 6 DMA
FUNCTIONS (DMA
CONTROLLER)
Addition of Caution to 7.3.4 Interrupt control register (xxICn)
3rd
edition
Addition of Caution to 7.3.6 In-service priority register (ISPR)
CHAPTER 7
INTERRUPT/
EXCEPTION
PROCESSING
FUNCTION
