CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
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User’s Manual U14492EJ3V0UD
(3) Operation in UDC mode
(a) Overview of operation in UDC mode
The count clock input to TM1n in the UDC mode (CMD bit of TUMn register = 1) can only be external
input from the TIUD1n and TCUD1n pins. Up/down count judgment in the UDC mode is determined
based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register
setting (there is a total of four choices).
Table 9-7. List of Count Operations in UDC Mode
PRM1n Register
PRM12
PRM11
PRM10
Operation
Mode
TM1n Operation
1
0
0
Mode 1
Down count when TCUD1n = high level
Up count when TCUD1n = low level
1
0
1
Mode 2
Up count upon detection of valid edge of TIUD1n input
Down count upon detection of valid edge of TCUD1n input
1
1
0
Mode 3
Automatic judgment in TCUD1n input level upon detection of
valid edge of TIUD1n input
1
1
1
Mode 4
Automatic judgment upon detection of both edges of TIUD1n
input and both edges of TCUD1n input
The UDC mode is further divided into two modes according to the TM1n clear conditions (count operation
is performed only with TIUD1n, TCUD1n input in both modes).
•
UDC mode A (TUMn register’s CMD bit = 1, MSEL bit = 0)
The TM1n clear source can be selected as only external clear input (TCLR1n), a match signal
between the TM1n count value and the CM1n0 set value during up count operation, or logical sum
(OR) of the two signals, using bits CLR1 and CLR0 of the TMC1n register.
TM1n can transfer the value of CM1n0 upon occurrence of TM1n underflow.
•
UDC mode B (TUMn register’s CMD bit = 1, MSEL bit = 1)
The status of TM1n after match of the TM1n count value and CM1n0 set value is as follows.
<1> In the case of up count operation, TM1n is cleared (0000H), and the INTCM1n0 interrupt is
generated.
<2> In the case of down count operation, the TM1n count value is decremented (
−
1).
The status of TM1n after match of the TM1n count value and CM1n1 set value is as follows.
<1> In the case of up count operation, the TM1n count value is incremented (+1).
<2> In the case of down count operation, TM1n is cleared (0000H), and the INTCM1n1 interrupt is
generated.
