CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U14492EJ3V0UD
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10.3 Asynchronous Serial Interfaces 1, 2 (UART1, UART2)
10.3.1 Features
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Clocked (synchronous) mode/asynchronous mode can be selected
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Operation clock
Synchronous mode: Baud rate generator/external clock selectable
Asynchronous mode: Baud rate generator
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Transfer rate
600 bps to 153600 bps (in asynchronous mode, f
XX
= 50 MHz)
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Full-duplex communications (LSB first)
On-chip reception buffer register n (RXBn)
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Three-pin configuration
TXDn: Transmit data output pin
RXDn: Receive data input pin
ASCKn: Synchronous serial clock I/O
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Reception error detection function
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Parity error
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Framing error
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Overrun error
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Interrupt sources: 2 types
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Reception completion interrupt (INTSRn):
Interrupt is generated when receive data is transferred from the
shift register to the reception buffer register n (RXBn) after serial
transfer is completed during a reception enabled state.
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Transmission completion interrupt (INTSTn): Interrupt is generated when the serial transmission of trans-
mit data (8/7 bits) from the shift register is completed.
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The character length of transmit/receive data is specified with the ASIMn0 register (extension bits are specified
with the ASIMn1 register)
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Character length:
7 or 8 bits
9 bits (when extension bit is added)
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Parity functions: Odd, even, 0, or no parity
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Transmission stop bits: 1 or 2 bits
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Communication mode: 1-frame transfer or 2-frame continuous transfer enabled
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On-chip dedicated baud rate generator
Remarks 1.
n = 1, 2
2.
f
XX
: Internal system clock
