CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
341
User’s Manual U14492EJ3V0UD
(3) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4)
The CVPEn0 register is a sub-channel n 16-bit main capture/compare register.
In the capture register mode, this register captures the value of TM21 when the BFEEn bit of the CMSEm0
register = 0 (m = 12, 34). When the BFEEn bit = 1, this register holds the value of TM20 or TM21.
In the compare register mode, a match between this register and TM2x is detected (TM2x = timer/counter
selected by TB1En and TB0En bits).
If the capture register mode is selected in the 32-bit mode (value of TB1En, TB0En bits of CMSEm0 register
= 11B), this register captures the contents of TM21 (higher 16 bits).
This register is read-only in 16-bit units.
Caution
When the BFEEn bit = 1, a compare match occurs on starting the timer in the compare
register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset
(TM2x = timer/counter selected by TB1En and TB0En bits, n = 1 to 4). After that, the value
of the sub register (CVSEn0) is written to the main register (CVPEn0).
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CVPE10
Address
FFFFF652H
Initial value
0000H
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CVPE20
Address
FFFFF656H
Initial value
0000H
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CVPE30
Address
FFFFF65AH
Initial value
0000H
14
13
12
2
3
4
5
6
7
8
9
10
11
15
1
0
CVPE40
Address
FFFFF65EH
Initial value
0000H
