NEC MuPD70F3187, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
11.6.10 Offset trigger generation mode
In the offset trigger generation mode, the count value is saved to the capture register (TTnCCR0) upon
detection of the valid edge of the TITn0 pin, and a capture interrupt (INTTTnCC0) is output. The
counter is cleared to 0000H by capture input. (Counter clear operation is not performed using the
TTnCCR1 register.)
The TTnCCR0 register and the TTnCCR1 register have their functions fixed as a capture register and a
compare register, respectively. The TTnCCR1 register can be rewritten during count operation. Regard-
ing compare register reload, the capture & clear timing upon detection of TITn0 pin input serves as the
reload timing.
During count operation, a capture interrupt (INTTTnCC0) is output upon capture to the TTnCCR0
register through TITn0 pin input, and a compare match interrupt (INTTTnCC1) is output upon a match
between the counter and the TTnCCR1 register.
The TOTn0 pin becomes the level set with bit TTnOL0. If TTnOL0 = 0, a low level is output a and if
TTnOL0 = 1, a high level is output.
The TOTn1 pin is reset upon a match between the counter and the TTnCCR1 register, and is set when
the counter is cleared to 0000H.
Cautions: 1. In the offset trigger generation mode the external event clock input (TEVTTn) is
prohibited (TTnCTL1.TTnEEE = 0).
2. When an internal count clock
≤
f
XX
/16 (TTnCTL0.TTnCKS2-0) is selected in offset
trigger generation mode, and a valid signal edge is input to TITn0 before the first
count up, the a value of FFFFH will be captured in the TTnCCR0 register.