NEC MuPD70F3187, User Manual

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Chapter 6 DMA Functions (DMA Controller)
User’s Manual U16580EE3V1UD00
6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1)
The DMAC has two dedicated channels to support DMA transfer for both PWM timers TMRn
independently, DMA channel 2 for TMR0 and DMA channel 3 for TMR1. As DMA trigger factor, which
requests and starts the DMA transfer, two corresponding timer interrupt signals are pre-defined
(INTTRnOD or INTTRnCD). These are the same signals as for reloading the internal buffer compare
registers by the contents of the capture/compare registers TRnCCRm (n = 0, 1)(m = 0 to 5).
For each DMA trigger data will be transferred from internal RAM to the capture/compare registers of
corresponding timer TMRn. The destination start address of the TMRn register (TRnCC0, TRnCC2 to
TRnCC5) can be set up by the SARx register, as well as the source start address in the internal RAM
by the MARx register. The destination end address is always fixed to TRnCC1 register, which also
enables the buffer reload in the timer TMRn period (ref. to Table 6-1).
The DMA transfer count is defined by the destination start and end address. However, an additionally
DMA trigger count is available, which can be specified in the DTCRx register from 1 to 256. After
decrementing the DTCRx register the DMAC will be prepared for a new DMA transfer from internal
RAM to the timer TMRn registers until the DMA trigger count terminates (DTCRx register = 0).
Remark: n = 0, 1
m = 0 to 5
x = n + 2
Table 6-1: Timer TMR Address Mapping for DMA Transfer
DMA Transfer Destination Address DMA Transfer Source
Address
TMRn registers Address Offset
TRnCCR5 00H Selectable as start
address Any even address in internal
RAM area
TRnCCR4 02H
TRnCCR0 08H
TRnCCR3 0AH
TRnCCR2 0CH
TRnCCR1 0EH Always end address