NEC MuPD70F3187, User Manual

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Chapter 11 16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
Figure 11-8: TMTn Control Register 2 (TTnCTL2) (2/2)
Remarks: 1. When bits TTnUDS1 and TTnUDS0 are set to 10B or 11B, the settings of bits TTnEIS1
and TTnEIS0 of the TTnIOC3 register are invalid, and these bits are fixed to the setting
for detection of both edges.
2. n = 0, 1
TTnECM0 Encoder Clear Mode on Match of Counter and TTnCCR0 Register
0 No clear condition
1
When the counter and TTnCCR0 register match, clear the counter if the next
count is a down count (TTnESF = 0)
Remark: The setting of bit TTnECM0 is valid in the encoder compare mode.
TTnUDS1 TTnUDS0 Encoder Operation Mode
0 0 Upon detection of the valid edge of the A phase of encoder input
(TENCTn0 pin), the following count operation is performed in the B
phase of encoder input.
• When "high", count down.
• When "low", count up.
0 1 Count up upon detection of valid edge of A phase of encoder input
(TENCTn0 pin).
Count down upon detection of valid edge of B phase of encoder
input (TENCTn1 pin).
1 0 Count up at rising edge of A phase of encoder input (TENCTn0
pin). Count down at falling edge of A phase of encoder input.
However, count operation is performed only when B phase of
encoder input (TENCTn1 pin) is “low”.
1 1 Detection of both edges of phase A of encoder input (TENCTn0
pin)/phase B of encoder input (TENCTn1 pin).
Judgment of count operation based on combination of detection
edge and input level.