NEC MuPD70F3187, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
Remark: d1: TRnDTC1 setting value
The counter loads the TRnCCR0 value minus “d1” upon occurrence of reload in the high-accuracy
T-PWM mode. As a result, the expected waveform can be output even if the cycle value is changed
at the peak reload timing.
Rewrite in <2> interval (rewrite during down count)
Since the next reload timing becomes the valley point, the cycle value changes from the next cycle
and the asymmetrical triangular waveform output is held. Since the cycle changes, be sure to set
again the duty value as required.
Remark: d1: TRnDTC1 setting value
Counter
TRnCCR0
“i”
TRnCCR0
buffer
INTTRnCD
“k”
TORn1
TRnCCR1
TRnCCR1
buffer
“k”
INTTRnOD
“m” d1
“r d1”
Reloadable timing
“r d1” value loaded to counter
TORn2
“i”
“i”
“k”
“k”
“m”
“m”
“r”
“r”
Counter
TRnCCR0
“i”
TRnCCR0
buffer
INTTRnCD
“k”
TORn1
TRnCCR1
TRnCCR1
buffer
“k” “k” “k”
INTTRnOD
“n d1”
“m d1”
“i”
Reloadable timing
TORn2
“i”
“i”
“k”
“k”
“m”
“m”
“n”
“n”