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234

Chapter 7

Interrupt/Exception Processing Function

User’s Manual U16580EE3V1UD00

Figure 7-8:

Example of Processing in which Another Interrupt Request Is Issued

while an Interrupt is being Processed (2/2)

Notes: 1.

Lower default priority

2.

Higher default priority

Caution:

The values of the EIPC and EIPSW registers must be saved before executing multiple
interrupts. When returning from multiple interrupt servicing, restore the values of
EIPC and EIPSW after executing the DI instruction.

Main routine

EI

Interrupt request i

(level 2)

Processing of i

Processing of k

Interrupt
request j
(level 3)

Processing of j

Interrupt request l

(level 2)

EI

EI

EI

Interrupt request o

(level 3)

Interrupt request s

(level 1)

Interrupt request k
(level 1)

Processing of l

Processing of n

Processing of m

Processing of s

Processing of u

Processing of t

Interrupt

request m

(level 3)

Interrupt request n
(level 1)

Processing of o

Interrupt

request p

(level 2)

Interrupt

request q

(level 1)

Interrupt

request r

(level 0)

Interrupt request u
(level 2)

Note 2

Interrupt
request t
(level 2)

Note 1

Processing of p

Processing of q

Processing of r

EI

If levels 3 to 0 are acknowledged

Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.

Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.

Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.

Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.

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Summary of Contents for MuPD70F3187

Page 1: ...User s Manual V850E PH2TM 32 Bit Single Chip Microcontroller Hardware μPD70F3187 μPD70F3447 Document No U16580EE3V1UD00 Date Published January 2007 NEC Electronics Corporation 2007 Printed in Germany ...

Page 2: ... insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to b...

Page 3: ...ereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Speci...

Page 4: ...vena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com For further information please contact G06 Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 Düsseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B...

Page 5: ... as follows Weight in data notation Left is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXXX o...

Page 6: ...6 Preface User s Manual U16580EE3V1UD00 ...

Page 7: ... 3 3 1 Operating modes outline 96 3 3 2 Operation mode specification 97 3 4 Address Space 98 3 4 1 CPU address space 98 3 4 2 Images 99 3 4 3 Wrap around of CPU address space 100 3 4 4 Memory map 101 3 4 5 Areas 103 3 4 6 Peripheral I O registers list 107 3 4 7 Programmable peripheral I O area 121 3 4 8 Specific registers 139 3 4 9 System wait control register VSWC 142 3 4 10 DMA wait control regi...

Page 8: ...n Processing Function 219 7 1 Features 219 7 2 Non maskable Interrupt 224 7 2 1 Operation 225 7 2 2 Restore 227 7 2 3 Non maskable interrupt status flag NP 228 7 2 4 Edge Detection Function 228 7 3 Maskable Interrupts 229 7 3 1 Operation 229 7 3 2 Restore 231 7 3 3 Priorities of maskable interrupts 232 7 3 4 Interrupt control register PICn 236 7 3 5 Interrupt mask registers 0 to 6 IMR0 to IMR6 240...

Page 9: ... 6 3 Reload hold flag 370 10 7 Interrupt Thinning Out Function 371 10 7 1 Operation of interrupt thinning out function 372 10 7 2 Operation examples when peak interrupts and valley interrupts occur alternately 374 10 7 3 Interrupt thinning out function during counter saw tooth wave operation 375 10 8 A D Conversion Trigger Function 376 10 8 1 A D conversion trigger operation 377 10 9 Error Interru...

Page 10: ...upon occurrence of compare match 567 12 6 3 Transfer operation 567 12 6 4 Interrupt signal output upon compare match 568 12 6 5 TM1UBD flag bit 0 of STATUS register operation 568 Chapter 13 Auxiliary Frequency Output Function AFO 569 13 1 Features 569 13 2 Configuration 569 13 3 Control Registers 570 13 4 Operation 572 13 4 1 Auxiliary frequency output 572 13 4 2 Auxiliary frequency generation 572...

Page 11: ...ode master mode transmission mode 656 16 4 3 Single transfer mode master mode reception mode 657 16 4 4 Continuous mode master mode transmission reception mode 658 16 4 5 Continuous mode master mode transmission mode 659 16 4 6 Continuous mode master mode reception mode 660 16 4 7 Continuous reception mode error 661 16 4 8 Continuous mode slave mode transmission reception mode 662 16 4 9 Continuou...

Page 12: ...tive mode in slave mode and transmission reception mode 736 17 7 Cautions 738 Chapter 18 AFCAN Controller 739 18 1 Features 739 18 1 1 Overview of functions 740 18 1 2 Configuration 741 18 2 CAN Protocol 742 18 2 1 Frame format 742 18 2 2 Frame types 743 18 2 3 Data frame and remote frame 743 18 2 4 Error frame 750 18 2 5 Overload frame 751 18 3 Functions 752 18 3 1 Determining bus priority 752 18...

Page 13: ...it Operation in Each Operation Mode 830 18 14 Time Stamp Function 831 18 14 1 Time stamp function 831 18 15 Baud Rate Settings 832 18 15 1 Baud rate setting conditions 832 18 15 2 Representative examples of baud rate settings 836 18 16 Operation of CAN Controller 840 Chapter 19 Random Number Generator μPD70F3187 only 865 19 1 Features 865 19 2 Configuration 865 19 3 Operation 866 19 3 1 Access tim...

Page 14: ... 2 Communication mode 992 24 4 3 Flash memory control 995 24 4 4 Selection of communication mode 996 24 4 5 Communication commands 997 24 4 6 Pin connection 998 24 5 Rewriting by Self Programming 1003 24 5 1 Overview 1003 24 5 2 Features 1004 Chapter 25 Electrical Specifications 1007 25 1 Absolute Maximum Ratings 1007 25 2 General Characteristics 1008 25 2 1 Capacitance 1008 25 2 2 Operating condi...

Page 15: ...15 User s Manual U16580EE3V1UD00 Chapter 27 Recommended Soldering Conditions 1035 Appendix A Index 1037 Appendix B Revision History 1047 ...

Page 16: ...16 User s Manual U16580EE3V1UD00 ...

Page 17: ...ea 106 Figure 3 23 Programmable Peripheral I O Area Outline 121 Figure 3 24 Programmable Peripheral Area Control Register BPC 122 Figure 3 25 Processor Command Register PRCMD 140 Figure 3 26 System Status Register Format PHS 141 Figure 4 1 Memory Block Function 146 Figure 4 2 Chip Area Select Control Registers 0 1 1 2 147 Figure 4 3 Bus Cycle Configuration Registers 0 1 BCT0 BCT1 150 Figure 4 4 Bu...

Page 18: ...4 Maskable interrupt status flag ID 243 Figure 7 15 Interrupt Mode Register 0 INTM0 245 Figure 7 16 Interrupt Mode Register 1 INTM1 246 Figure 7 17 Interrupt Mode Register 2 INTM2 247 Figure 7 18 Interrupt Mode Register 3 INTM3 248 Figure 7 19 Software Exception Processing 249 Figure 7 20 RETI Instruction Processing 250 Figure 7 21 Exception Status Flag EP 251 Figure 7 22 Illegal Opcode 252 Figure...

Page 19: ...TMRn Counter Read Register TRnCNT 322 Figure 10 9 TMRn Sub Counter Read Register TRnSBC 322 Figure 10 10 TMRn Dead Time Setting Register 0 TRnDTC0 323 Figure 10 11 TMRn Dead Time Setting Register 1 TRnDTC1 323 Figure 10 12 TMRn Control Register 0 TRnCTL0 1 2 324 Figure 10 13 TMRn Control Register 1 TRnCTL1 1 2 326 Figure 10 14 TMRn I O Control Register 0 TRnIOC0 328 Figure 10 15 TMR1 I O Control R...

Page 20: ... 1 3 429 Figure 10 64 Timer Output Change after Compare Register Updating Timings 1 3 433 Figure 10 65 Compare Register Value After Trough Reload Timing 1 3 436 Figure 10 66 Compare Register Value After Trough Reload TRnDTC1 TRnDTC0 1 3 439 Figure 10 67 Compare Register Value After Trough Reload 1 3 442 Figure 10 68 Output Waveform Example When Dead Time Is Set 445 Figure 10 69 Dead Time Control i...

Page 21: ... 10 TUM10 545 Figure 12 8 Timer Control Register 10 TMC10 1 2 546 Figure 12 9 Capture Compare Control Register 10 CCR10 548 Figure 12 10 Signal Edge Selection Register 10 SESA10 1 2 549 Figure 12 11 Prescaler Mode Register 10 PRM10 551 Figure 12 12 Status Register 10 STATUS10 553 Figure 12 13 TMENC10 Block Diagram During PWM Output Operation 556 Figure 12 14 PWM Signal Output Example When ALVT10 B...

Page 22: ...trol Register 2 UCnCTL2 615 Figure 15 5 UARTCn Option Control Register 0 UCnOPT0 1 2 616 Figure 15 6 UARTCn Option Control Register 1 UCnOPT1 618 Figure 15 7 UARTCn Status Register UCnSTR 1 2 620 Figure 15 8 UARTCn Status Register 1 UCnSTR1 622 Figure 15 9 UARTCn Receive Data Register UCnRX UCnRXL 623 Figure 15 10 UARTCn Transmit Data Register UCnTX UCnTXL 624 Figure 15 11 UARTC Transmit Receive D...

Page 23: ...f CSI Data Buffer Register n CSIBUFn 696 Figure 17 12 Data Transfer Direction Specification MSB first 697 Figure 17 13 Data Transfer Direction Specification LSB first 698 Figure 17 14 Transfer Data Length Changing Function 699 Figure 17 15 Clock Timing 700 Figure 17 16 Master Mode 701 Figure 17 17 Slave Mode 702 Figure 17 18 Single Mode 704 Figure 17 19 Consecutive Mode 706 Figure 17 20 Delay Cont...

Page 24: ... during Transmission 844 Figure 18 40 Message transmit processing 845 Figure 18 41 ABT Message transmit processing 846 Figure 18 42 Transmission via interrupt using CnLOPT register 847 Figure 18 43 Transmission via interrupt using CnTGPT register 848 Figure 18 44 Transmission via software polling 849 Figure 18 45 Transmission abort processing Except Normal Operation Mode with ABT 850 Figure 18 46 ...

Page 25: ...15 Figure 20 39 Port Emergency Shut Off Control Register 5 PESC5 916 Figure 20 40 Port Emergency Shut Off Status Register 5 ESOST5 917 Figure 20 41 Port Register 6 P6 919 Figure 20 42 Port Mode Register 6 PM6 919 Figure 20 43 Port Mode Control Register 6 PMC6 1 2 920 Figure 20 44 Port Emergency Shut Off Control Register 6 PESC6 922 Figure 20 45 Port Emergency Shut Off Status Register 6 ESOST6 923 ...

Page 26: ...th Dedicated Flash Programmer CSIB0 HS 993 Figure 24 7 Procedure for Manipulating Flash Memory 995 Figure 24 8 Selection of Communication Mode 996 Figure 24 9 Communication Commands 997 Figure 24 10 FLMD0 Pin Connection Example 998 Figure 24 11 FLMD1 Pin Connection Example 999 Figure 24 12 Conflict of Signals Serial Interface Input Pin 1000 Figure 24 13 Malfunction of Other Device 1001 Figure 24 1...

Page 27: ... 1028 Figure 25 23 CSI3 Chip Select Timing Master Mode only CSIT 1 CSWE 1 CSMD 0 1029 Figure 25 24 CSI3 Chip Select Timing Master Mode only CSIT 1 CSWE 1 CSMD 1 1029 Figure 25 25 Equivalent Circuit of Analog Inputs 1030 Figure 25 26 Serial Write Operation Characteristics 1032 Figure 26 1 208 Pin Plastic QFP Fine Pitch 28 x 28 1033 Figure 26 2 256 Pin Plastic BGA Fine Pitch 21 x 21 1034 ...

Page 28: ...28 User s Manual U16580EE3V1UD00 ...

Page 29: ...eak Interrupts and Valley Interrupts in Each Mode 363 Table 10 1 Positive Phase Operation Condition List 432 Table 10 2 Negative Phase Operation Condition List 432 Table 10 3 Compare Register Value After Trough Reload TRnDTC0 TRnDTC1 433 Table 10 4 Compare Register Value After Trough Reload 436 Table 10 5 Compare Register Value After Trough Reload TRnDTC1 TRnDTC0 438 Table 10 6 Compare Register Va...

Page 30: ...etting 746 Table 18 6 Operation in error status 750 Table 18 7 Definition of error frame fields 750 Table 18 8 Definition of overload frame fields 751 Table 18 9 Determining bus priority 752 Table 18 10 Bit stuffing 752 Table 18 11 Error types 753 Table 18 12 Output timing of error frame 754 Table 18 13 Types of error states 755 Table 18 14 Error counter 756 Table 18 15 Segment setting 759 Table 1...

Page 31: ...e 24 1 Rewrite Method 988 Table 24 2 Basic Functions 989 Table 24 3 Protection Functions 990 Table 24 4 Signal Connections of Dedicated Flash Programmer PG FP4 994 Table 24 5 Communication Commands 997 Table 24 6 Relationship Between FLMD0 and FLMD1 Pins and Operation Mode when Reset is Released 999 Table 24 7 Pins Used by Serial Interfaces 1000 Table 25 1 Absolute Maximum Ratings 1007 Table 25 2 ...

Page 32: ...32 User s Manual U16580EE3V1UD00 ...

Page 33: ...and data conversion This enhances the performance of both data processing and control It is possible to use the software resources of the V850 CPU integrated system since the instruction codes of the V850E1 are upwardly compatible at the object code level with those of the V850 CPU In addition the V850E1 CPU NU85EFC incorporates a single precision floating point unit which supports high speed floa...

Page 34: ...pace common program data Chip select output function 4 spaces Memory block division function 2 4 or 8 MB block Programmable wait function Idle state insertion function External bus interfaceNote1 32 bit data bus address data separated 22 bit address bus 4 programmable chip select areas 32 16 8 bit bus sizing function External wait function Internal memory μPD70F3187 μPD70F3447 Flash ROM 512 KB 384...

Page 35: ... interface CSI3 up to 2 channelsNote 2 FCAN interface AFCAN up to 2 channelsNote 2 A D converters 10 bit resolution 2 10 channels Random number generator Automatic seed generation Fips Maurer test passing Clock generator 16 MHz clock oscillator 4 fold PLL synthesizer for internal system clock Power save modes HALT mode Auxiliary frequency output Programmable by user software Supply voltage 1 5 V i...

Page 36: ...ther applications where a combination of general purpose inverter control functions and CAN network support is required 1 4 Ordering Information Part Number Package μPD70F3187GD 64 LML 208 pin plastic LQFP fine pitch 28 28 μPD70F3187GD A1 64 LML 208 pin plastic LQFP fine pitch 28 28 μPD70F3187GD A2 64 LML 208 pin plastic LQFP fine pitch 28 28 μPD70F3187F1 A2 64 JN4 256 pin plastic BGA 21 21 μPD70F...

Page 37: ...ESO0 178 PDL15 D15 205 PCT4 RD 50 P23 TIP51 TEVTP4 TOP51 175 PDL12 D12 197 PDH14 D30 83 RESET 100 P36 FCRXD1 2 PCM0 WAIT 1 PCD5 BEN3 30 P00 NMI 49 P22 TIP50 TTRGP4 TOP50 174 PDL11 D11 196 PDH13 D29 99 P35 FCTXD0 202 PCT5 WR 104 P32 RXDC1 INTP5 208 PCD4 BEN2 48 P21 TIP41 TTRGP5 TOP41 193 PDH12 D28 173 PDL10 D10 98 P34 FCRXD0 103 P31 TXDC0 207 PCD3 BEN1 79 CVSS 5 AV SS0 47 P20 TIP40 TEVTP5 TOP40 172...

Page 38: ...A 21 21 μPD70F3187F1 A2 JN4 μPD70F3447F1 A2 JN4 Figure 1 2 Pin Configuration 256 pin Plastic BGA 21 21 Top View Bottom View Index mark Index mark A B C D E F G H J K L M N P R T U V W Y Y W V U T R P N M L K J H G F E D C B A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 39: ...15 B13 PDL13 D13 PDL13 A14 PDL14 D14 PDL14 B14 PDL12 D12 PDL12 A15 PDL9 D9 PDL9 B15 PDL8 D8 PDL8 A16 PDL5 D5 PDL5 B16 PDL4 D4 PDL4 A17 PDL1 D1 PDL1 B17 PDL3 D3 PDL3 A18 PDL0 D0 PDL0 B18 PCS4 CS4 PCS4 A19 NC NC B19 NC NC A20 NC NC B20 NC NC C1 AVSS0 AVSS0 D1 AVSS0 AVSS0 C2 MODE1 MODE1 D2 AVSS0 AVSS0 C3 MODE2 MODE2 D3 AVSS0 AVSS0 C4 PCD4 BEN2 PCD4 D4 PCM0 WAIT PCM0 C5 PCM7 PCM7 D5 PCD3 BEN1 PCD3 C6 ...

Page 40: ...I13 ANI13 J2 ANI14 ANI14 K2 ANI10 ANI10 J3 ANI15 ANI15 K3 ANI11 ANI11 J4 ANI16 ANI16 K4 ANI12 ANI12 J17 PAL5 A5 PAL5 K17 VDD13 VDD13 J18 PAL8 A8 PAL8 K18 VSS13 VSS13 J19 PAL7 A7 PAL7 K19 PAL4 A4 PAL4 J20 MODE0 MODE0 K20 PAL2 A2 PAL2 L1 AVSS1 AVSS1 M1 P01 INTP0 ESO0 P01 INTP0 ESO0 L2 AVSS1 AVSS1 M2 P00 NMI P00 NMI L3 AVSS1 AVSS1 M3 VSS10 VSS10 L4 AVSS1 AVSS1 M4 VDD10 VDD10 L17 VDD13 VDD13 M17 P95 S...

Page 41: ...1 P17 TIP31 TEVTP2 TOP31 V2 P23 TIP51 TEVTP4 TOP51 P23 TIP51 TEVTP4 TOP51 U3 P22 TIP50 TTRGP4 TOP50 P22 TIP50 TTRGP4 TOP50 V3 P24 TIP60 TEVTP7 TOP60 P24 TIP60 TEVTP7 TOP60 U4 P25 TIP61 TTRGP7 TOP61 P25 TIP61 TTRGP7 TOP61 V4 P70 TIT00 TEVTT1 TOT00 TENCT00 P70 TIT00 TEVTT1 TOT00 TENCT00 U5 P71 TIT01 TTRGT1 TOT01 TENCT01 P71 TIT01 TTRGT1 TOT01 TENCT01 V5 P74 TIT11 TEVTT0 TOT11 TENCT11 P74 TIT11 TEVTT...

Page 42: ...W8 P55 TOR05 P55 TOR05 Y8 P56 TOR06 P56 TOR06 W9 P57 TOR07 P57 TOR07 Y9 P60 TOR10 TTRGR 1 P60 TOR10 TTRGR 1 W10 VSS31 VSS31 Y10 VSS31 VSS31 W11 X2 X2 Y11 CVSS CVSS W12 X1 X1 Y12 CVDD CVDD W13 DMS DMS Y13 DRST DRST W14 DDO DDO Y14 DDI DDI W15 P65 TOR15 P65 TOR15 Y15 P63 TOR13 TIR12 P63 TOR13 TIR12 W16 P66 TOR16 P66 TOR16 Y16 P64 TOR14 TIR13 P64 TOR14 TIR13 W17 P34 FCRXD0 P34 FCRXD0 Y17 P35 FCTXD0 P...

Page 43: ...rt CD PCM0 PCM1 PCM6 PCM7 Port CM PCS0 PCS1 PCS3 PCS4 Port CS PCT4 PCT5 Port CT PDL0 to PDL15 Port DH PDH0 to PDH15 Port DL RD Read strobe RESET Reset RXDC0 RXDC1 Receive data input SCK30 SCK31 SCKB0 SCKB1 Serial clock SCS300 to SCS303 SCS310 to SCS313 Serial chip select SI30 SI31 SIB0 SIB1 Serial data input SO30 SO31 SOB0 SOB1 Serial data output SSB0 SSB1 Serial slave select input TCLR1 Timer cle...

Page 44: ...15 PAH0 to PAH5 P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P45 P50 to P57 P60 to P67 P70 to P75 P80 to P86 P90 to P96 P100 to P102 PCS0 PCS1 PCS3 PCS4 PCM0 PCM1 PCM6 PCM7 PCT4 PCT5 PCD2 to PCD5 INTC NMI INTP0 to INTP12 RPU TMR 2ch TMENC10 1ch TMP 9ch TMT 2ch TOR00 to TOR07 TOR10 to TOR17 ESO0 ESO1 TOP00 to TOP70 TOP01 1 to TOP8 TIP00 to TIP70 TIP01 to TIP71 TEVTP0 to TEVTP8 TTRGP0 to TTRGP...

Page 45: ... P04 P10 to P17 P20 to P27 P30 to P37 P40 to P45 P50 to P57 P60 to P67 P70 to P75 P80 to P86 P90 to P96 P100 to P102 PCS0 PCS1 PCS3 PCS4 PCM0 PCM1 PCM6 PCM7 PCT4 PCT5 PCD2 to PCD5 INTC NMI INTP0 to INTP12 RPU TMR 2ch TMP 9ch TMT 2ch TOR00 to TOR07 TOR10 to TOR17 ESO0 ESO1 TOP00 to TOP70 TOP01 1 to TOP8 TIP00 to TIP70 TIP01 to TIP71 TEVTP0 to TEVTP8 TTRGP0 to TTRGP8 TECRT0 TECRT1 TIT00 TIT01 TIT10 ...

Page 46: ...ace Supports access to SRAM external ROM and external I O b DMA controller DMAC The DMAC performs data transfers b w internal on chip RAM and peripheral I O For this purpose eight DMA channels are provided for particular transfer functions of serial I O interfaces real time pulse unit TMR and A D converter 3 ROM There is on chip flash memory of 512 KB provided in the μPD70F3187 and 384 KB in the μ...

Page 47: ...ial interface B CSIB up to 2 channels clocked serial interface 3 CSI3 and up to 2 channels FCAN interface AFCAN The UARTC performs data transfer using pins TXDCn and RXDCn n 0 1 The CSIB performs data transfer using pins SOBn SIBn SCKBn SSIn and SSOnNote1 The CSI3 performs data transfer using pins SO3n SI3n SCK3n SCS3n0 to SCS3Note1 The AFCAN performs data transfer using pins FCTXDn and FCRXDnNote...

Page 48: ...se unit I O Port 6 8 bit I O Real time pulse unit I O Port 7 6 bit I O Real time pulse unit I O external interrupt input Port 8 7 bit I O Serial interface I O external interrupt input Port 9 7 bit I O Serial interface I O external interrupt input External interrupt input Port 10 3 bit I O Real time pulse unit I O Port AL 16 bit I O External address bus None Port AH 6 bit I O External address bus N...

Page 49: ...nput or output direction can be specified in 1 bit units TIP00 TEVTP1 TOP00 P11 TIP01 TTRGP1 TOP01 P12 TIP10 TTRGP0 TOP10 P13 TIP11 TEVTP0 TOP11 P14 TIP20 TEVTP3 TOP20 P15 TIP21 TTRGP3 TOP21 P16 TIP30 TTRGP2 TOP30 P17 TIP31 TEVTP2 TOP31 P20 I O Port 2 8 bit I O port Input or output direction can be specified in 1 bit units TIP40 TEVTP5 TOP40 P21 TIP41 TTRGP5 TOP41 P22 TIP50 TTRGP4 TOP50 P23 TIP51 ...

Page 50: ...in 1 bit units TOR10 TTRGR1 P61 TOR11 TIR10 P62 TOR12 TIR11 P63 TOR13 TIR12 P64 TOR14 TIR13 P65 TOR15 P66 TOR16 P67 TOR17 TEVTR1 P70 I O Port 7 6 bit I O port Input or output direction can be specified in 1 bit units TIT00 TEVTT1 TOT00 TENCT00 P71 TIT01 TTRGT1 TOT01 TENCT01 P72 TECRT0 INTP12 P73 TIT10 TTRGT0 TOT10 TENCT10 P74 TIT11 TEVTT0 TOT11 TENCT11 P75 TECRT1 AFO P80 I O Port 8 7 bit I O port ...

Page 51: ...fied in 1 bit units TCLR1 TICC10 TOP81 TOP81 P101 TCUD1 TICC11 P102 TIUD1 TO1 PAL0 I O Port AL 16 bit I O port Input or output direction can be specified in 1 bit units A0 PAL1 A1 PAL2 A2 PAL3 A3 PAL4 A4 PAL5 A5 PAL6 A6 PAL7 A7 PAL8 A8 PAL9 A9 PAL10 A10 PAL11 A11 PAL12 A12 PAL13 A13 PAL14 A14 PAL15 A15 PAH0 I O Port AH 6 bit I O port Input or output direction can be specified in 1 bit units A16 PA...

Page 52: ...DL14 D14 PDL15 D15 PDH0 I O Port DH 16 bit I O port Input or output direction can be specified in 1 bit units D16 PDH1 D17 PDH2 D18 PDH3 D19 PDH4 D20 PDH5 D21 PDH6 D22 PDH7 D23 PDH8 D24 PDH9 D25 PDH10 D26 PDH11 D27 PDH12 D28 PDH13 D29 PDH14 D30 PDH15 D31 PCD2 I O Port CD 4 bit I O port Input or output direction can be specified in 1 bit units BEN0 PCD3 BEN1 PCD4 BEN2 PCD5 BEN3 Table 2 1 Port Pins ...

Page 53: ...bit units WAIT PCM1 PCM6 PCM7 PCS0 I O Port CS 4 bit I O port Input or output direction can be specified in 1 bit units CS0 PCS1 CS1 PCS3 CS3 PCS4 CS4 PCT4 I O Port CT 2 bit I O port Input or output direction can be specified in 1 bit units RD PCT5 WR Table 2 1 Port Pins 5 5 Pin Name I O Function Alternate Function μPD70F3187 μPD70F3447 ...

Page 54: ... input ADC1 AVSS0 Power supply ground ADC0 AVSS1 Power supply ground ADC1 BEN0Note O External byte enable output PCD2 BEN1Note PCD3 BEN2Note PCD4 BEN3Note PCD5 CS0Note O Chip select signal output PCS0 CS1Note PCS1 CS3Note PCS3 CS4Note PCS4 CVDD Oscillator power supply 1 5 V CVSS Oscillator power supply ground D0 to D15Note I O 32 bit external data bus PDL0 to PDL15 D16 to D31Note PDH0 to PDH15 DCK...

Page 55: ...al output PCT4 RESET I System reset input RXDC0 I Receive input UARTC0 P30 INTP4 RXDC1 I Receive input UARTC1 P32 INTP5 SCK30 I O Serial shift clock I O CSI30 P82 SCK31Note I O Serial shift clock I O CSI31 P92 SCKB0 I O Serial shift clock I O CSIB0 P42 SCKB1Note I O Serial shift clock I O CSIB1 P45 SCS300 O Serial peripheral chip select CSI30 P83 INTP7 SCS301 P84 INTP8 SCS302 P85 INTP9 SCS303 P86 ...

Page 56: ... TIP11 TOP11 TEVTP1 I Timer event input TMP1 P10 TIP00 TOP00 TEVTP2 I Timer event input TMP2 P17 TIP31 TOP31 TEVTP3 I Timer event input TMP3 P14 TIP20 TOP20 TEVTP4 I Timer event input TMP4 P23 TIP51 TOP51 TEVTP5 I Timer event input TMP5 P20 TIP40 TOP40 TEVTP6 I Timer event input TMP6 P27 TIP71 TOP71 TEVTP7 I Timer event input TMP7 P24 TIP60 TOP60 TEVTR1 I Timer event input TMR1 P67 TOR17 TEVTT0 I ...

Page 57: ...ote I External count clock input TMENC10 P102 TO1 P102 TO1Note O Pulse signal output TMENC10 P102 TIUD1 P102 TOP00 O Pulse signal output TMP0 P10 TIP00 TEVTP1 TOP01 P11 TIP01 TTRGP1 TOP10 O Pulse signal output TMP1 P12 TIP10 TTRGP0 TOP11 P13 TIP11 TEVTP0 TOP20 O Pulse signal output TMP2 P14 TIP20 TEVTP3 TOP21 P15 TIP21 TTRGP3 TOP30 O Pulse signal output TMP3 P16 TIP30 TTRGP2 TOP31 P17 TIP31 TEVTP2...

Page 58: ... P16 TIP30 TOP30 TTRGP3 Timer trigger input TMP3 P15 TIP21 TOP21 TTRGP4 Timer trigger input TMP4 P22 TIP50 TOP50 TTRGP5 Timer trigger input TMP5 P21 TIP41 TOP41 TTRGP6 Timer trigger input TMP6 P26 TIP70 TOP70 TTRGP7 Timer trigger input TMP7 P25 TIP61 TOP61 TTRGR1 I Timer trigger input TMR1 P60 TOR10 TTRGT0 I Timer trigger input TMT0 P73 TIT10 TOT10 TENCT10 TTRGT1 I Timer trigger input TMT1 P71 TIT...

Page 59: ...3V1UD00 Note Not available on μPD70F3447 WAITNote I External wait control signal input PCM0 WRNote O Write strobe signal output PCT5 X1 I Crystal connection X2 Table 2 2 Non Port Pins 6 6 Pin Name I O Function Alternate Function μPD70F3187 μPD70F3447 ...

Page 60: ... Operating CS3 PCS3 Hi Z Hi Z Operating Operating CS4 PCS4 Hi Z Hi Z Operating Operating RD PCT4 Hi Z Hi Z Operating Operating WR PCT5 Hi Z Hi Z Operating Operating WAIT PCM0 Hi Z Hi Z Operating Operating PCM1 PCM6 PCM7 Hi Z Hi Z Hi Z Operating DCK Operating Operating Operating Operating DDI Operating Operating Operating Operating DDO Operating Operating Operating Operating DMS Operating Operating...

Page 61: ...ort cannot be switched with the NMI input pin external interrupt request input pin RPU emergency shut off signal input pin and A D converter ADC external trigger input pin Read the status of each pin by reading the port a Port mode P00 to P04 are input only b Control mode P00 to P04 also serve as NMI INTP0 to INTP3 ESO0 ESO1 ADTRG0 and ADTRG1 pins but the control function cannot be disabled i NMI ...

Page 62: ...t pins iv TOP00 TOP01 TOP10 TOP11 TOP20 TOP21 TOP30 TOP31 Timer output Output These pins output timer TMP0 to TMP3 pulse signals 3 P20 to P27 Port 2 Input Output Port 2 is an 8 bit I O port in which input or output can be set for each port pin individually Besides functioning as an I O port in control mode P20 to P27 operate as RPU input or output The operation mode can be specified by the port 2 ...

Page 63: ... 1 bit units using the port 3 mode register PM3 i INTP4 INTP5 Interrupt request from peripherals Input These are external interrupt request input pins which are simultaneously enabled in port input mode b Control mode P30 to P37 can be set to port or control mode in 1 bit units using the PMC3 register i TXDC0 TXDC1 Transmit data Output These pins output serial transmit data of UARTC0 and UARTC1 ii...

Page 64: ... port or control mode for each port pin individually a Port mode P40 to P45 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P45 can be set to port or control mode in 1 bit units using the PMC4 register i SOB0 SOB1Note Serial output Output These pins output CSIB0 and CSIB1Note serial transmit data ii SIB0 SIB1Note Serial input Input These pins i...

Page 65: ...0 to P67 Port 6 Input Output Port 6 is an 8 bit I O port in which input or output can be set for each port pin individually Besides functioning as an I O port in control mode P60 to P67 operate as RPU input or output The operation mode can be specified by the port 6 mode control register PMC6 to port or control mode for each port pin individually a Port mode P60 to P67 can be set to input or outpu...

Page 66: ...l interrupt request input pin which is simultaneously enabled in port input mode b Control mode P70 to P75 can be set to port or control mode in 1 bit units using the PMC7 register i TIT00 TIT01 TIT10 TIT11 Timer capture input Input These are timer TMT0 and TMT1 capture trigger input pins ii TEVTT0 TEVTT1 Timer event input Input These are timer TMT0 and TMT1 external event counter input pins iii T...

Page 67: ...6 can be set to input or output in 1 bit units using the port 8 mode register PM8 i INTP6 INTP7 INTP8 Interrupt request from peripherals Input These are external interrupt request input pins which are simultaneously enabled in port input mode b Control mode P80 to P86 can be set to port or control mode in 1 bit units using the PMC8 register i SO30 Serial output Output This pin outputs CSI30 serial...

Page 68: ...r output in 1 bit units using the port 9 mode register PM9 i INTP9 INTP10 INTP11 Interrupt request from peripherals Input These are external interrupt request input pins which are simultaneously enabled in port input mode b Control mode P90 to P96 can be set to port or control mode in 1 bit units using the PMC9 register i SO31 Serial output OutputNote This pin outputs CSI31 serial transmit data ii...

Page 69: ...clear signal input pin to the up down counter TMENC10 iv TICC10 TICC11 Timer capture input InputNote These are timer TMENC10 external capture trigger input pins v TO1 Timer output OutputNote This pin outputs timer TMENC10 pulse signals vi TOP80 Timer output Output This pin outputs timer TMP8 pulse signals 12 PAL0 to PAL15 Port AL I O Port AL is an 8 bit or a 16 bit I O port in which input or outpu...

Page 70: ...e are the address output pins of the higher 6 bits of the 22 bit address bus when the external memory is accessed 14 PDL0 to PDL15 Port DL I O Port DL is an 8 bit or a 16 bit I O port in which input or output can be set for each port pin individually Besides functioning as a port in control mode these pins operate as the data bus D0 to D15 when memory is expanded externally The operation mode can ...

Page 71: ...te These are the data I O pins of the higher 16 bits of the 32 bit data bus when the external memory is accessed 16 PCD2 to PCD5 Port CD I O Port CD is a 4 bit I O port in which input or output can be set for each port pin individually Besides functioning as a port in control mode these pins operate as control signal outputsNote when memory is expanded externally The operation mode can be specifie...

Page 72: ... or hold time is terminated within the sampling timing wait insertion may not be executed 18 PCS0 PCS1 PCS3 PCS4 Port CS I O Port CS is a 4 bit I O port in which input or output can be set for each port pin individually Besides functioning as a port in control mode these pins operate as control signal outputsNote when memory is expanded externally The operation mode can be specified by the port CS...

Page 73: ... can be set to input or output in 1 bit units using the port CT mode register PMCT b Control mode PCT4 and PCT5 can be set to port or control mode in 1 bit units using the PMCCT register i RD Read strobe 3 state outputNote This is a strobe signal output pin that shows whether the bus cycle currently being executed is a read cycle for the external memory or peripheral I O extension area In the idle...

Page 74: ...ug reset Input This pin inputs a debug reset signal that is a negative logic signal to initialize the DCU asynchronously When this signal goes low the DCU is reset invalidated Keep this pin low when the debug function is not used 25 MODE0 to MODE2 Mode Input These are input pins used to specify the operating mode 26 FLMD0 FLMD1 flash programming mode These are input pins used to specify the flash ...

Page 75: ...tor 34 CVSS Ground for clock oscillator This is the ground pin for the clock generator 35 VDD10 to VDD15 Power supply These are the positive power supply pins for the internal CPU 36 VDD30 to VDD37 Power supply These are the positive power supply pins for the peripheral interface 37 VSS10 to VSS15 Ground These are the ground pins for the internal CPU 38 VSS30 to VSS37 Ground These are the ground p...

Page 76: ...ntly to VDD3 or VSS3 via a resistor Output leave open P11 TIP01 TTRGP1 TOP01 P12 TIP10 TTRGP0 TOP10 P13 TIP11 TEVTP0 TOP11 P14 TIP20 TEVTP3 TOP20 P15 TIP21 TTRGP3 TOP21 P16 TIP30 TTRGP2 TOP30 P17 TIP31 TEVTP2 TOP31 P20 TIP40 TEVTP5 TOP40 P21 TIP41 TTRGP5 TOP41 P22 TIP50 TTRGP4 TOP50 P23 TIP51 TEVTP4 TOP51 P24 TIP60 TEVTP7 TOP60 P25 TIP61 TTRGP7 TOP61 P26 TIP70 TTRGP6 TOP70 P27 TIP71 TEVTP6 TOP71 P...

Page 77: ...1 P72 TECRT0 INTP12 P73 TIT10 TTRGT0 TOT10 TENCT10 P74 TIT11 TEVTT0 TOT11 TENCT11 P75 TECRT1 AFO P80 SI30 P81 SO30 P82 SCK30 P83 SCS300 INTP6 P84 SCS301 INTP7 P85 SCS302 INTP8 P86 SCS303 SSB0 P90 SI31 P90 P91 SO31 P91 P92 SCK31 P92 P93 SCS310 INTP9 P93 INTP9 P94 SCS311 INTP10 P94 INTP10 P95 SCS312 INTP11 P95 INTP11 P96 SCS313 SSB1 P96 P100 TCLR1 TICC10 TOP80 P100 TOP80 P101 TCUD1 TICC11 P101 P102 ...

Page 78: ...via a resistor Output leave open PCT5 WR PCT5 PCM0 WAIT PCM0 PCM1 PCM1 PCM6 PCM6 PCM7 PCM7 RESET 2 Pin must be used in the intended way X1 X2 MODE0 FLMD0 2 MODE1 FLMD1 2 MODE2 2 DCK 1 Connect independently to VDD3 via a resistor DRST 2 I Leave open on chip pull down resistor DMS 1 Connect independently to VDD3 via a resistor DDI DDO 3 Leave open always level output during reset ANI00 to ANI09 7 Co...

Page 79: ...U16580EE3V1UD00 AVDD Pin must be used in the intended way AVSS0 AVSS1 VDD10 to VDD15 VSS10 to VSS15 VDD30 to VDD37 VSS30 to VSS37 CVDD CVSS Table 2 4 I O Circuit Types 4 4 Terminal I O circuit type Recommended termination μPD70F3187 μPD70F3447 ...

Page 80: ... 2 Type 5 K Type 2 I Type 7 Type 3 Schmitt trigger input with hysteresis characteristics IN Schmitt trigger input with hysteresis characteristics IN P ch N ch OUT VDD VDD P ch N ch IN OUT data output disable input enable VDD P ch N ch IN OUT data output disable input enable P ch N ch IN comparator threshold voltage VREF ...

Page 81: ...ay 60ns to 200ns INTP2 to INTP11 ADTRG0 ADTRG1 4 to 5 clocks fXX 16 or fXX 64 set by NCR1 bit of NRC register INTP12 TICC00Note TICC01Note TCLR0Note TCUD0Note TIUD0Note TIT00 TIT01 TIT10 TIT11 TECRT0 TECRT1 TEVTT0 TEVTT1 TTRGT0 TTRGT1 TENCT00 TENCT01 TENCT10 TENCT11 4 to 5 clocks fXX 16 or fXX 64 set by NCR2 bit of NRC register TIP00 TIP01 TIP10 TIP11 TEVTP0 TEVTP1 TTRGP0 TTRGP1 4 to 5 clocks fXX ...

Page 82: ...k setting for input pins TIR10 to TIR13 TEVTR1 TTRGR1 0 fXX 16 1 fXX 64 NCR6 Noise removal clock setting for input pins TIP60 TIP61 TIP70 TIP71 TEVTP6 TEVTP7 TTRGP6 TTRGP7 0 fXX 16 1 fXX 64 NCR5 Noise removal clock setting for input pins TIP40 TIP41 TIP50 TIP51 TEVTP4 TEVTP5 TTRGP4 TTRGP5 0 fXX 16 1 fXX 64 NCR4 Noise removal clock setting for input pins TIP20 TIP21 TIP30 TIP31 TEVTP2 TEVTP3 TTRGP2...

Page 83: ...anual U16580EE3V1UD00 Figure 2 2 Noise Removal Time Control Register 2 2 NCR1 Noise removal clock setting for input pins INTP2 to INTP11 ADTRG0 ADTRG1 0 fXX 16 1 fXX 64 NCR0 Noise removal clock setting for NMI input pin 0 fXX 16 1 fXX 64 ...

Page 84: ...84 Chapter 2 Pin Functions User s Manual U16580EE3V1UD00 MEMO ...

Page 85: ...6 ns 64 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear General purpose registers 32 bits 32 Internal 32 bit architecture 5 stage pipeline control Multiply divide instructions 32 bits 32 bits 64 bits in 1 to 2 clocks Saturated operation instructions Floating point arithmetic unit single precision 32 bits IEEE754 85 standard 32 bit shift instruction 1 clock Load store i...

Page 86: ...r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r0 Zero register r1 Assembler reserved register r3 Stack pointer SP r4 Global pointer GP r5 Text pointer TP r30 Element pointer EP r31 Link pointer LP PC Program counter PSW Program status word ECR Interrrupt source register FEPC FEPSW Status saving register during NMI Status saving register during NMI EIPC EIPSW Status sa...

Page 87: ...r2 is not used by the real time OS r2 can be used as a variable register 2 Program counter PC This register holds the address of the instruction under execution The lower 26 bits of this register are valid and bits 31 to 26 are fixed to 0 If a carry occurs from bit 25 to bit 26 it is ignored Bit 0 is fixed to 0 and branching to an odd address cannot be performed Figure 3 2 Program Counter PC Table...

Page 88: ...rupt servicing because bit 0 of PC is fixed to 0 If setting a value to EIPC FEPC and CTPC set an even number bit 0 0 Table 3 2 System Register Numbers System Register Operand Specification Enabled for instruction No Name Function LDSR STSR 0 EIPC PC value at Interrupt handler entry Note 1 Yes Yes 1 EIPSW PSW value at Interrupt handler entry Note 1 Yes Yes 2 FEPC PC value at NMI handler entry Yes Y...

Page 89: ...on or maskable interrupt occurs is saved to EIPC except for the DIVH instruction see Chapter 7 Interrupt Exception Processing Function on page 219 Since there is only one set of interrupt status saving registers the contents of these registers must be saved by the program when multiple interrupt servicing is enabled Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved fixed to 0 for future...

Page 90: ...ing execution of a RETI instruction 3 Exception cause register ECR Upon occurrence of an interrupt or an exception the Exception Cause Register ECR holds the source of the interrupt or the exception The value held by ECR is an exception code coded for each interrupt source This register is a read only register and thus data cannot be written to it using the LDSR instruction Figure 3 5 Interrupt So...

Page 91: ...ervicing not in progress 1 NMI servicing in progress 6 EP Indicates that exception processing is in progress This flag is set to 1 when an exception occurs Moreover interrupt requests can be acknowledged even when this bit is set 0 Exception processing not in progress 1 Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled 0 Interrupt enabled ...

Page 92: ...o 8 of CTPSW are reserved fixed to 0 for future function expansion Figure 3 7 CALLT Execution Status Saving Registers CTPC CTPSW The values of CTPC and CTPSW are restored to PC and PSW during execution of the CTRET instruction Operation result status Flag status Saturated operation result SAT OV S Maximum positive value exceeded 1 1 0 7FFFFFFFH Maximum negative value exceeded 1 1 1 80000000H Posit...

Page 93: ...8 of DBPSW are reserved fixed to 0 for future function expansion Figure 3 8 Exception Debug Trap Status Saving Registers DBPC DBPSW The values of DBPC and DBPSW are restored to PC and PSW during execution of the DBRET instruction 7 CALLT base pointer CTBP The CALLT base pointer CTBP is used to specify CALLT table start address and generate target addresses bit 0 is fixed to 0 Bits 31 to 26 are res...

Page 94: ... UT PT 0 0 0 0 0 0 0 0 Bit position Bit name Description 31 to 13 RFU Reserved field Fixed to 0 12 IT Enables invalid operation detection in the TR value calculation 0 IV is set when an invalid operation is detected 1 IV and TR are set when an invalid operation is detected 11 ZT Enables zero divide operation detection in the TR value calculation 0 ZD is set when a zero divide operation is detected...

Page 95: ...t operation has overflowed 0 no overflow generated 1 overflow generated 9 UD Undervalue indicates that the result of executing a floating point operation has underflowed 0 no underflow generated 1 underflow generated 8 PR PRecision error indicates that an accuracy failure occurred 0 no accuracy failure occurred 1 accuracy failure occurred 7 to 5 0 Reserved field Fixed to 0 4 TR This flag summarize...

Page 96: ...p mode 1Note after the system reset is released each pin related to the bus interface enters the control mode program execution branches to the external device s memory reset entry address and instruction processing starts The internal ROM area is mapped from address 100000H c ROM less mode μPD70F3187 only After the system reset is released each pin related to the bus interface enters the control ...

Page 97: ...n Remark L Low level input H High level input Notes 1 Single chip mode 1 is not available on μPD70F3447 2 ROM less mode is not available on μPD70F3447 MODE2 MODE1 MODE0 Mode Remark L L L Single chip mode 0 Internal ROM area is allocated from address 00000000H L L H Flash memory programming mode CSIB0 IUARTC0 selected by MODE0 pin toggling L H L ROM less modeNote 2 External 32 bit data bus L H H Si...

Page 98: ...essing data access When addressing instructions a linear address space program space of up to 64 MB is supported However both the program and data spaces include areas whose use is prohibited For details refer to Figure 3 13 Address Space Image on page 99 Figure 3 12 shows the CPU address space Figure 3 12 CPU Address Space FFFFFFFFH 04000000H 03FFFFFFH 00000000H Data area 4 GB linear Program area...

Page 99: ...n this 4 GB address space however 256 MB physical address spaces can be seen as an image Therefore whatever the values of bits 31 to 29 of an address may be a physical address space of the same 256 MB is accessed Figure 3 13 Address Space Image FFFFFFFFH F0000000H EFFFFFFFH 00000000H Internal ROM Image Image Image Internal RAM Peripheral I O External memory Physical address space FFFFFFFH 0000000H...

Page 100: ... No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is a peripheral I O area Therefore do not execute any branch operation instructions in which the destination address will reside in any part of this area Figure 3 14 Program Space 2 Data space The result of an operand address calculation that exceeds 32 bits is truncated to 32 bits Therefore the lower li...

Page 101: ...eripheral I O area Internal RAM area On chip peripheral I O area Internal RAM area Access prohibitedNote 1 External memory area Internal ROM area External memory area Internal ROM area External memory area Single chip mode 0 Single chip mode 1 ROMless mode Program area 64 MB 1 MB 1 MB 4 KB x0200000H x01FFFFFH x0100000H x00FFFFFH x0000000H 32 KB xFFFF000H xFFFEFFFH xFFF0000H xFFEFFFFH On chip perip...

Page 102: ...ess prohibited area is accessed xFFFFFFFH On chip peripheral I O area Internal RAM area Internal ROM area Single chip mode 0 x0100000H x00FFFFFH x0000000H xFFFF000H xFFFEFFFH xFFF0000H xFFEFFFFH On chip peripheral I O area mirrorNote 1 x3FF0000H x3FEFFFFH Access prohibitedNote 2 xFFF6000H xFFF5FFFH x3FF6000H x3FF5FFFH Internal RAM area mirror x3FFF000H x3FFEFFFH x4000000H x3FFFFFFH Access prohibit...

Page 103: ...gle chip mode 1 Addresses 0100000H to 017FFFFH addresses 0180000H to 01FFFFFH are undefined Figure 3 18 Internal ROM Internal Flash Memory Area of μPD70F3187 In case of μPD70F3447 internal flash memory of 384 KB are physically provided in the following addresses as internal ROM flash memory In single chip mode 0 Addresses 000000H to 05FFFFH addresses 060000H to 0FFFFFH are undefined Remark Single ...

Page 104: ... handler addresses is called an interrupt exception table which is located in the inter nal ROM area When an interrupt exception request is acknowledged execution jumps to the han dler address and the program written in that memory is executed For detailed list of the interrupt exception sources and the corresponding handler addresses please refer to Table 7 1 Interrupt Exception Source List on pa...

Page 105: ...nal RAM The 32 KB area of 3FF0000H to 3FF7FFFH can be seen as an image of FFF0000H to FFF7FFFH Figure 3 20 Internal RAM Area of μPD70F3187 In case of μPD70F3447 internal RAM of 24 KB are physically provided at addresses FFF0000H to FFF5FFFH as internal RAM The 32 KB area of 3FF0000H to 3FF5FFFH can be seen as an image of FFF0000H to FFF5FFFH Figure 3 21 Internal RAM Area of μPD70F3447 FFF7FFFH FFF...

Page 106: ...ned with functions such as on chip peripheral I O operation mode specification and state monitoring are mapped to the on chip peripheral I O area Program fetches are not allowed in this area Cautions 1 For registers in which byte access is possible if half word access is executed the higher 8 bits become undefined during a read operation and the lower 8 bits of data are written to the register dur...

Page 107: ...e register ALH R W R W FFH FFFFF022H PMAH Port mode register AH R W R W FFH FFFFF024H PMDL Port mode register DL R W FFFFH FFFFF024H PMDLL Port mode register DLL R W R W FFH FFFFF025H PMDLH Port mode register DLH R W R W FFH FFFFF026H PMDH Port mode register DH R W FFFFH FFFFF026H PMDHL Port mode register DHL R W R W FFH FFFFF027H PMDHH Port mode register DHH R W R W FFH FFFFF028H PMCS Port mode r...

Page 108: ...R W FFFFH FFFFF104H IMR2L Interrupt mask register 2L R W R W FFH FFFFF105H IMR2H Interrupt mask register 2H R W R W FFH FFFFF106H IMR3 Interrupt mask register 3 R W FFFFH FFFFF106H IMR3L Interrupt mask register 3L R W R W FFH FFFFF107H IMR3H Interrupt mask register 3H R W R W FFH FFFFF108H IMR4 Interrupt mask register 4 R W FFFFH FFFFF108H IMR4L Interrupt mask register 4L R W R W FFH FFFFF109H IMR...

Page 109: ...47H FFFFF140H PIC24 Interrupt control register 24 R W R W 47H FFFFF142H PIC25 Interrupt control register 25 R W R W 47H FFFFF144H PIC26 Interrupt control register 26 R W R W 47H FFFFF146H PIC27 Interrupt control register 27 R W R W 47H FFFFF148H PIC28 Interrupt control register 28 R W R W 47H FFFFF14AH PIC29 Interrupt control register 29 R W R W 47H FFFFF14CH PIC30 Interrupt control register 30 R ...

Page 110: ... Interrupt control register 64 R W R W 47H FFFFF192H PIC65 Interrupt control register 65 R W R W 47H FFFFF194H PIC66 Interrupt control register 66 R W R W 47H FFFFF196H PIC67 Interrupt control register 67 R W R W 47H FFFFF198H PIC68 Interrupt control register 68 R W R W 47H FFFFF19AH PIC69 Interrupt control register 69 R W R W 47H FFFFF19CH PIC70 Interrupt control register 70 R W R W 47H FFFFF19EH...

Page 111: ...FFFFF1E0H PIC104 Interrupt control register 104 R W R W 47H FFFFF1E2H PIC105 Interrupt control register 105 R W R W 47H FFFFF1FAH ISPR Interrupt service priority register R R 00H FFFFF1FCH PRCMD Command register W undefined FFFFF200H ADM00 A D converter 0 mode register 0 R W R W 00H FFFFF201H ADM01 A D converter 0 mode register 1 R W R W 00H FFFFF202H ADM02 A D converter 0 mode register 2 R W R W ...

Page 112: ... conversion result register 14H R undefined FFFFF25AH ADCR15 A D conversion result register 15 R undefined FFFFF25BH ADCR15H A D conversion result register 15H R undefined FFFFF25CH ADCR16 A D conversion result register 16 R undefined FFFFF25DH ADCR16H A D conversion result register 16H R undefined FFFFF25EH ADCR17 A D conversion result register 17 R undefined FFFFF25FH ADCR17H A D conversion resu...

Page 113: ...FR6 DMA trigger factor register 6 R W R W 00H FFFFF34EH DTFR7 DMA trigger factor register 7 R W R W 00H FFFFF400H P0 Port register 0 R R undefined FFFFF402H P1 Port register 1 R W R W undefined FFFFF404H P2 Port register 2 R W R W undefined FFFFF406H P3 Port register 3 R W R W undefined FFFFF408H P4 Port register 4 R W R W undefined FFFFF40AH P5 Port register 5 R W R W undefined FFFFF40CH P6 Port ...

Page 114: ...TMR0 control register 0 R W R W 00H FFFFF581H TR0CTL1 TMR0 control register 1 R W R W 00H FFFFF582H TR0IOC0 TMR0 I O control register 0 R W R W 00H FFFFF585H TR0IOC3 TMR0 I O control register 3 R W R W 00H FFFFF586H TR0IOC4 TMR0 I O control register 4 R W R W 00H FFFFF587H TR0OPT0 TMR0 option register 0 R W R W 00H FFFFF588H TR0OPT2 TMR0 option register 2 R W R W 00H FFFFF589H TR0OPT3 TMR0 option ...

Page 115: ...W 0000H FFFFF5E2H TR1DTC1 TMR1 dead time set register 1 R W 0000H FFFFF5E4H TR1CNT TMR1 timer counter read register R 0000H FFFFF5E6H TR1SBC TMR1 timer sub counter read register R 0000H FFFFF600H TP0CTL0 TMP0 timer control register 0 R W R W 00H FFFFF601H TP0CTL1 TMP0 timer control register 1 R W R W 00H FFFFF602H TP0IOC0 TMP0 I O control register 0 R W R W 00H FFFFF603H TP0IOC1 TMP0 I O control r...

Page 116: ... R W 00H FFFFF641H TP4CTL1 TMP4 timer control register 1 R W R W 00H FFFFF642H TP4IOC0 TMP4 I O control register 0 R W R W 00H FFFFF643H TP4IOC1 TMP4 I O control register 1 R W R W 00H FFFFF644H TP4IOC2 TMP4 I O control register 2 R W R W 00H FFFFF645H TP4OPT0 TMP4 option register R W R W 00H FFFFF646H TP4CCR0 TMP4 capture compare register 0 R W 0000H FFFFF648H TP4CCR1 TMP4 capture compare registe...

Page 117: ... W 00H FFFFF685H TP8OPT0 TMP8 option register R W R W 00H FFFFF686H TP8CCR0 TMP8 capture compare register 0 R W 0000H FFFFF688H TP8CCR1 TMP8 capture compare register 1 R W 0000H FFFFF68AH TP8CNT TMP8 count register R 0000H FFFFF690H TT0CTL0 TMT0 timer control register 0 R W R W 00H FFFFF691H TT0CTL1 TMT0 timer control register 1 R W R W 00H FFFFF692H TT0CTL2 TMT0 timer control register 2 R W R W 0...

Page 118: ...FFF6BFH STATUS10 Status register 10 R R 00H Note 2 FFFFF6F0H TPIC0 TMP input source control register 0 R W R W 00H FFFFF6F2H TPIC1 TMP input source control register 1 R W R W 00H FFFFF6F4H TPIC2 TMP input source control register 2 R W R W 00H FFFFF700H RNG Random number register R undefined FFFFF7A0H NRC Noise removal time control register R W R W 00H FFFFF802H PHS Peripheral status register R W R...

Page 119: ...trol register 1 R W R W 00H FFFFFD02H CB0CTL2 CSIB0 control register 2 R W 00H FFFFFD03H CB0STR CSIB0 state register R W R W 00H FFFFFD04H CB0RX0 CSIB0 receive data register R 0000H FFFFFD04H CB0RX0L CSIB0 receive data register L R 00H FFFFFD06H CB0TX0L CSIB0 transmit data register L R W 00H FFFFFD06H CB0TX0 CSIB0 transmit data register R W 0000H FFFFFD20H CB1CTL0 CSIB1 control register 0 R W R W ...

Page 120: ...e 2 FFFFFD64H SFCS31L CSI31 chip selection CSI buffer register L R W R W FFH Note 2 FFFFFD64H SFCS31 CSI31 chip selection CSI buffer register R W FFFFH Note 2 FFFFFD65H SFCS31H CSI31 chip selection CSI buffer register H R R FFH Note 2 FFFFFD66H SFDB31L CSI31 transmit data CSI buffer register L R W 00H Note 2 FFFFFD66H SFDB31 CSI31 transmit data CSI buffer register R W 0000H Note 2 FFFFFD67H SFDB31...

Page 121: ...to this area the written contents are reflected on the on chip peripheral I O area Therefore access to this area is prohibited To access the on chip peripheral I O area be sure to specify addresses FFFF000H to FFFFFFFH Figure 3 23 Programmable Peripheral I O Area Outline Remark M xx00B N M 11B P M 10B Cautions 1 It is recommended to locate the programmable peripheral area in the first 32 Mbyte of ...

Page 122: ...le the programmable peripheral I O area is 87FFH This setting assigns the programmable peripheral I O area to addresses from 1FFC000H to 1FFFFFFH After reset 0000H R W Address FFFFF064H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BPC PA15 0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 n 0 1 PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of programmable peripheral I O area...

Page 123: ...W Undefined 0000044H C0MASK2L CAN0 module mask 2 register L R W Undefined 0000046H C0MASK2H CAN0 module mask 2 register H R W Undefined 0000048H C0MASK3L CAN0 module mask 3 register L R W Undefined 000004AH C0MASK3H CAN0 module mask 3 register H R W Undefined 000004CH C0MASK4L CAN0 module mask 4 register L R W Undefined 000004EH C0MASK4H CAN0 module mask 4 register H R W Undefined 0000050H C0CTRL ...

Page 124: ...r 00 R W Undefined 000010AH C0MIDL00 CAN0 message identifier L register 00 R W Undefined 000010CH C0MIDH00 CAN0 message identifier H register 00 R W Undefined 000010EH C0MCTRL00 CAN0 message control register 00 R W Undefined 0000120H C0MDATA0101 CAN0 message data byte 0 and 1 register 01 R W Undefined 0000120H C0MDATA001 CAN0 message data byte 0 register 01 R W Undefined 0000121H C0MDATA101 CAN0 m...

Page 125: ...A103 CAN0 message data byte 1 register 03 R W Undefined 0000162H C0MDATA2303 CAN0 message data byte 2 and 3 register 03 R W Undefined 0000162H C0MDATA203 CAN0 message data byte 2 register 03 R W Undefined 0000163H C0MDATA303 CAN0 message data byte 3 register 03 R W Undefined 0000164H C0MDATA4503 CAN0 message data byte 4 and 5 register 03 R W Undefined 0000164H C0MDATA403 CAN0 message data byte 2 r...

Page 126: ...A505 CAN0 message data byte 3 register 05 R W Undefined 00001A6H C0MDATA6705 CAN0 message data byte 6 and 7 register 05 R W Undefined 00001A6H C0MDATA605 CAN0 message data byte 6 register 05 R W Undefined 00001A7H C0MDATA705 CAN0 message data byte 7 register 05 R W Undefined 00001A8H C0MDLC05 CAN0 message data length code register 05 R W Undefined 00001A9H C0MCONF05 CAN0 message configuration regi...

Page 127: ...register 07 R W Undefined 00001EAH C0MIDL07 CAN0 message identifier L register 07 R W Undefined 00001ECH C0MIDH07 CAN0 message identifier H register 07 R W Undefined 00001EEH C0MCTRL07 CAN0 message control register 07 R W Undefined 0000200H C0MDATA0108 CAN0 message data byte 0 and 1 register 08 R W Undefined 0000200H C0MDATA008 CAN0 message data byte 0 register 08 R W Undefined 0000201H C0MDATA108...

Page 128: ...A110 CAN0 message data byte 1 register 10 R W Undefined 0000242H C0MDATA2310 CAN0 message data byte 2 and 3 register 10 R W Undefined 0000242H C0MDATA210 CAN0 message data byte 2 register 10 R W Undefined 0000243H C0MDATA310 CAN0 message data byte 3 register 10 R W Undefined 0000244H C0MDATA4510 CAN0 message data byte 4 and 5 register 10 R W Undefined 0000244H C0MDATA410 CAN0 message data byte 2 r...

Page 129: ...A512 CAN0 message data byte 3 register 12 R W Undefined 0000286H C0MDATA6712 CAN0 message data byte 6 and 7 register 12 R W Undefined 0000286H C0MDATA612 CAN0 message data byte 6 register 12 R W Undefined 0000287H C0MDATA712 CAN0 message data byte 7 register 12 R W Undefined 0000288H C0MDLC12 CAN0 message data length code register 12 R W Undefined 0000289H C0MCONF12 CAN0 message configuration regi...

Page 130: ...register 14 R W Undefined 00002CAH C0MIDL14 CAN0 message identifier L register 14 R W Undefined 00002CCH C0MIDH14 CAN0 message identifier H register 14 R W Undefined 00002CEH C0MCTRL14 CAN0 message control register 14 R W Undefined 00002E0H C0MDATA0115 CAN0 message data byte 0 and 1 register 15 R W Undefined 00002E0H C0MDATA015 CAN0 message data byte 0 register 15 R W Undefined 00002E1H C0MDATA115...

Page 131: ...H CAN1 module mask 4 register H R W Undefined 0000650H C1CTRL CAN1 module control register R W 0000H 0000652H C1LEC CAN1 module last error code register R W 00H 0000653H C1INFO CAN1 module information register R 00H 0000654H C1ERC CAN1 module error counter R W 0000H 0000656H C1IE CAN1 module interrupt enable register R W 0000H 0000656H C1IEL CAN1 module interrupt enable register L R W 00H 0000657H...

Page 132: ...trol register 00 R W Undefined 0000720H C1MDATA0101 CAN1 message data byte 0 and 1 register 01 R W Undefined 0000720H C1MDATA001 CAN1 message data byte 0 register 01 R W Undefined 0000721H C1MDATA101 CAN1 message data byte 1 register 01 R W Undefined 0000722H C1MDATA2301 CAN1 message data byte 2 and 3 register 01 R W Undefined 0000722H C1MDATA201 CAN1 message data byte 2 register 01 R W Undefined ...

Page 133: ...A303 CAN1 message data byte 3 register 03 R W Undefined 0000764H C1MDATA4503 CAN1 message data byte 4 and 5 register 03 R W Undefined 0000764H C1MDATA403 CAN1 message data byte 2 register 03 R W Undefined 0000765H C1MDATA503 CAN1 message data byte 3 register 03 R W Undefined 0000766H C1MDATA6703 CAN1 message data byte 6 and 7 register 03 R W Undefined 0000766H C1MDATA603 CAN1 message data byte 6 r...

Page 134: ...ATA705 CAN1 message data byte 7 register 05 R W Undefined 00007A8H C1MDLC05 CAN1 message data length code register 05 R W Undefined 00007A9H C1MCONF05 CAN1 message configuration register 05 R W Undefined 00007AAH C1MIDL05 CAN1 message identifier L register 05 R W Undefined 00007ACH C1MIDH05 CAN1 message identifier H register 05 R W Undefined 00007AEH C1MCTRL05 CAN1 message control register 05 R W ...

Page 135: ...R W Undefined 0000800H C1MDATA0108 CAN1 message data byte 0 and 1 register 08 R W Undefined 0000800H C1MDATA008 CAN1 message data byte 0 register 08 R W Undefined 0000801H C1MDATA108 CAN1 message data byte 1 register 08 R W Undefined 0000802H C1MDATA2308 CAN1 message data byte 2 and 3 register 08 R W Undefined 0000802H C1MDATA208 CAN1 message data byte 2 register 08 R W Undefined 0000803H C1MDATA3...

Page 136: ...A310 CAN1 message data byte 3 register 10 R W Undefined 0000844H C1MDATA4510 CAN1 message data byte 4 and 5 register 10 R W Undefined 0000844H C1MDATA410 CAN1 message data byte 2 register 10 R W Undefined 0000845H C1MDATA510 CAN1 message data byte 3 register 10 R W Undefined 0000846H C1MDATA6710 CAN1 message data byte 6 and 7 register 10 R W Undefined 0000846H C1MDATA610 CAN1 message data byte 6 r...

Page 137: ...ATA712 CAN1 message data byte 7 register 12 R W Undefined 0000888H C1MDLC12 CAN1 message data length code register 12 R W Undefined 0000889H C1MCONF12 CAN1 message configuration register 12 R W Undefined 000088AH C1MIDL12 CAN1 message identifier L register 12 R W Undefined 000088CH C1MIDH12 CAN1 message identifier H register 12 R W Undefined 000088EH C1MCTRL12 CAN1 message control register 12 R W ...

Page 138: ... 14 R W Undefined 00008CCH C1MIDH14 CAN1 message identifier H register 14 R W Undefined 00008CEH C1MCTRL14 CAN1 message control register 14 R W Undefined 00008E0H C1MDATA0115 CAN1 message data byte 0 and 1 register 15 R W Undefined 00008E0H C1MDATA015 CAN1 message data byte 0 register 15 R W Undefined 00008E1H C1MDATA115 CAN1 message data byte 1 register 15 R W Undefined 00008E2H C1MDATA2315 CAN1 ...

Page 139: ...t 6 on page 918 1 Setting data to specific registers Setting data to a specific registers is done in the following sequence 1 Prepare the data to be set to the special register in a general purpose register 2 Write the data prepared in 1 to the command register PRCMD 3 Write the data to the specific register using the following instructions Store instruction ST SST instruction Bit manipulation ins...

Page 140: ...gister is valid As a result register values can be overwritten only using a preset sequence preventing invalid write operations PRCMD register must be written with store instruction execution by CPU only not with DMA transfer If an illegal store operation to a command or specific register takes place it is reported by the PRERR flag of the system status register PHS This register can be written in...

Page 141: ...anipulation instruction is performed on an on chip peripheral I O register other than a specific register after a write operation to the PRCMD register when 4 in the example 3 4 8 1 Setting data to specific registers is not performed for a specific register Remark Even if an on chip peripheral I O register is read including a bit manipulation instruction between writing the PRCMD register and writ...

Page 142: ...ation frequency used This register can be read or written in 1 bit or 8 bit units 3 4 10 DMA wait control registers 0 and 1 DMAWC0 DMAWC1 The DMA wait control registers 0 and 1 DMAWC0 DMAWC1 are a registers that control the bus access wait and signal timing for DMA transfers Set the values described in the table below to the DMAWC0 and DMAWC1 registers in accordance with the operation frequency us...

Page 143: ... the following registers immediately after reset signal release in the following sequence System wait control register VSWC refer to 3 4 9 System wait control register VSWC DMA wait control registers 0 and 1 DMAWC0 DMAWC1 refer to 3 4 10 DMA wait control registers 0 and 1 DMAWC0 DMAWC1 ...

Page 144: ...144 Chapter 3 CPU Functions User s Manual U16580EE3V1UD00 MEMO ...

Page 145: ... bus control port alternate function pins Programmable Endian format Little Endian Big Endian 4 2 Bus Control Pins The following pins are used for connecting to external devices Note Even if the port mode control registers for the μPD70F3447 exist it is prohibited to write other values to these registers than the reset values Bus Control Pin Function when in Control Mode Function when in Port Mode...

Page 146: ...FFFFFH 3A00000H 39FFFFFH 3800000H 37FFFFFH 3400000H 33FFFFFH 3000000H 2FFFFFFH 2800000H 27FFFFFH 1000000H 0FFFFFFH 0C00000H 0BFFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 Mbytes Block 0 2 Mbytes Block 3 2 Mbytes Block 13 2 Mbytes Block 14 2 Mbytes Block 12 2 Mbytes Block 15 2 Mbytes CS7 CS5 CS6 CS4 CS6 CS4 CS4 CS3 Block 11 4 Mbytes Block 10 4 Mbytes Block 9 8 Mbytes Block 8 8 Mbyt...

Page 147: ...to the same block the priority order is controlled as follows CSC0 Peripheral I O area CS0 CS2 CS1 CS3 Note CSC1 Peripheral I O area CS7 CS5 CS6 CS4 Note Note Not all the chip area select signals are externally available on output pins Even so enabling chip area select signals other than CS0 CS1 CS3 or CS4 the setting for the corresponding memory blocks will be effective too regardless of an exter...

Page 148: ...uring block 4 or 5 access CS32 CS3 active during block 6 access CS33 CS3 active during block 7 access CS40 CS4 active during block 12 13 14 or 15 access CS41 CS4 active during block 10 or 11 access CS42 CS4 active during block 9 access CS43 CS4 active during block 8 access CS50 CS5 active during block 15 access CS51 CS5 active during block 14 access CS52 CS5 active during block 13 access CS53 CS5 ...

Page 149: ...EE3V1UD00 4 4 Bus Cycle Type Control Function In the V850E PH2 the following external devices can be connected directly to each memory block SRAM external ROM external I O Connected external devices are specified by the bus cycle type configuration registers 0 1 BCT0 BCT1 ...

Page 150: ...ver it is possible to access external memory areas whose initialization has been finished 2 The bits marked as 0 and 1 are reserved The values of these bits must not be changed Otherwise the operation of the external bus interface cannot be ensured Figure 4 3 Bus Cycle Configuration Registers 0 1 BCT0 BCT1 After reset CCCCH R W Address FFFFF480H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCT0 ME3 1 0 0...

Page 151: ...ource is as follows Notes 1 The instruction fetch becomes 2 clocks in case of contention with data access 2 This is the minimum value Table 4 1 Number of Bus Access Clocks Resources Bus width Internal RAM 32 bits Peripheral I O 16 bits External memory 16 bits Bus Cycle Configuration Instruction fetch Normal access 1Note 1 2Note 2 Branch 1 2Note 2 Operand data access 1 3Note 2 2Note 2 ...

Page 152: ... not change the set value Also do not access an external memory area other than that for this initialization routine until initial setting of the BSC register is finished However it is possible to access external memory areas whose initialization has been finished Figure 4 4 Bus Size Configuration Register BSC After reset AAAAH R W Address FFFFF066H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BSC BS71 B...

Page 153: ...ndian method for each CS area selected with the chip select signal CS0 to CS7 Switching of the Endian method is specified with the Endian configuration register BEC Figure 4 5 Big Endian Addresses within Word Figure 4 6 Little Endian Addresses within Word 0008H 0009H 000AH 000BH 0004H 0005H 0006H 0007H 0000H 0001H 0002H 0003H 31 24 23 16 17 8 7 0 000BH 000AH 0009H 0008H 0007H 0006H 0005H 0004H 000...

Page 154: ... area to Little Endian format n 0 to 7 3 In the following areas the data processing method is fixed to Little Endian method Any setting of Big Endian method for these areas according to the BEC register is invalid On chip peripheral I O area Internal RAM area Fetch area of external memory Figure 4 7 Endian Configuration Register BEC After reset 0000H R W Address FFFFF068H 15 14 13 12 11 10 9 8 7 6...

Page 155: ...4n 2 Access to address 4n 1 3 Access to address 4n 2 4 Access to address 4n 3 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 1 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 2 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 3 1 Access to address 4n 2 Access to address 4n 1 3 Access to ...

Page 156: ... data bus 7 0 7 0 4n 1 Address Byte data External data bus 7 0 7 0 4n 2 Address Byte data External data bus 7 0 7 0 4n 3 Address Byte data External data bus 1 Access to address 4n 2 Access to address 4n 1 3 Access to address 4n 2 4 Access to address 4n 3 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 7 0 7 0 15 8 23 16 31 24 Byte data External data bus Address 4n 1 7 0 7 0 15 8 23...

Page 157: ... Address Byte data External data bus 7 0 7 0 Byte data 15 8 External data bus 4n 1 Address 7 0 7 0 15 8 4n 2 Address Byte data External data bus 7 0 7 0 Byte data 15 8 External data bus 4n 3 Address 1 Access to address 4n 2 Access to address 4n 1 3 Access to address 4n 2 4 Access to address 4n 3 7 0 7 0 4n Address Byte data External data bus 7 0 7 0 4n 1 Address Byte data External data bus 7 0 7 0...

Page 158: ... Access to address 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 4n 1 Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 1 4n 2 Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 2 4n 3 Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 4 Halfword data Ha...

Page 159: ... 7 0 7 0 15 8 15 8 External data bus 4n 4n 1 Address Halfword data 7 0 7 0 15 8 15 8 External data bus 4n 1 Address 7 0 7 0 15 8 15 8 External data bus 4n 2 Address Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 15 8 External data bus 4n 2 4n 3 Address Halfword data 7 0 7 0 15 8 15 8 External data bus 4n 3 Address 7 0 7 0 15 8 15 8 External data bus 4n 4 Address Halfword data Halfw...

Page 160: ...4n Address Address 7 0 7 0 15 8 External data bus 4n 1 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 1 Address Address 7 0 7 0 15 8 External data bus 4n 2 Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 2 Address Address 7 0 7 0 15 8 External data bus 4n 3 Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 3 Address Add...

Page 161: ...ress 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 1 4n Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 2 4n 1 Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 3 4n 2 Halfword data 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 External data bus Address 4n 4 Halfword data Halfword data 1s...

Page 162: ...7 0 7 0 15 8 15 8 External data bus 4n 1 4n Address Halfword data 7 0 7 0 15 8 15 8 External data bus 4n 1 Address 7 0 7 0 15 8 15 8 External data bus 4n 2 Address Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 15 8 External data bus 4n 3 4n 2 Address Halfword data 7 0 7 0 15 8 15 8 External data bus 4n 3 Address 7 0 7 0 15 8 15 8 External data bus 4n 4 Address Halfword data Halfwo...

Page 163: ...8 External data bus 4n 1 Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 1 Address Address 7 0 7 0 15 8 External data bus 4n 2 Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 2 Address Address 7 0 7 0 15 8 External data bus 4n 3 Halfword data Halfword data 1st access 2nd access 7 0 7 0 15 8 External data bus 4n 3 Address Addre...

Page 164: ...31 24 23 16 31 24 Word data External data bus Address Address 4n 1 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus 4n 4 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus Address Address 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus 4n 4 4n 5 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 2...

Page 165: ... 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 4n 1 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 3 4n 2 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 1 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 3 4n 2 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 4 ...

Page 166: ...31 24 Word data External data bus Address 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 5 4n 4 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 5 4n 4 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 6 ...

Page 167: ...data bus 4n 1 Address 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 2 Address 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 3 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 Word data External data bus Address Address Address Address 4n 1 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 2 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 3 7 0 ...

Page 168: ...s 4n 3 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 4 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 5 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 Word data External data bus Address Address Address Address 4n 3 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 4 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 5 7 0 7 0 15 8 23 16 31 24 Wo...

Page 169: ...6 31 24 Word data External data bus Address Address 4n 1 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus 4n 4 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus Address 4n 5 4n 4 Address 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 Word data External data bus 4n 3 4n 2 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31...

Page 170: ...7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 4n 1 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 3 4n 2 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 1 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 4...

Page 171: ...31 24 Word data External data bus Address 4n 2 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 5 4n 4 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 3 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 4 4n 5 7 0 7 0 15 8 15 8 23 16 31 24 Word data External data bus Address 4n 6 ...

Page 172: ...data External data bus 4n 1 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 2 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 3 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 Word data External data bus Address Address Address Address 4n 1 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 2 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 3 7 0 7 ...

Page 173: ...s 4n 3 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 4 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 5 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 Word data External data bus Address Address Address Address 4n 3 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 4 7 0 7 0 15 8 23 16 31 24 Word data External data bus 4n 5 7 0 7 0 15 8 23 16 31 24 Wo...

Page 174: ...mable wait states with wait control performed only by each peripheral function 2 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than that for this initialization routine until initial setting of the DWC0 and DWC1 registers is finished However it is possible to access external memory areas whose initialization ...

Page 175: ...y each peripheral function 2 Write to the AWC registers after reset and then do not change the set values Also do not access an external memory area other than that for this initialization routine until initial setting of the AWC registers is finished However it is possible to access external memory areas whose initialization has been finished Figure 4 9 Address Wait Control Register AWC Remark n ...

Page 176: ...e following the T2 state starts after the idle state is inserted An idle state is inserted after read write cycles for SRAM external I O or external ROM In the following cases an idle state is inserted in the timing after read write cycles for SRAM external I O or external ROM The idle state insertion setting can be specified by program using the bus cycle control register BCC and the bus clock di...

Page 177: ...l setting of the BCC register is finished However it is possible to access external memory areas whose initialization has been finished 3 Do not change the settings of bits that are 0 after reset Otherwise the operation of the external bus interface cannot be ensured Figure 4 10 Bus Cycle Control Register BCC Remark n 0 to 7 After reset AAAAH R W Address FFFFF48AH 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 178: ...s initialization routine until initial setting of the DVC register is finished However it is possible to access external memory areas whose initialization has been finished 3 Do not change the settings of bits 0 to 6 Otherwise the operation of the external bus interface cannot be ensured Figure 4 11 Bus Clock Dividing Control Register DVC After reset 01H R W Address FFFFF48EH 7 6 5 4 3 2 1 0 DVC B...

Page 179: ...r the highest priority has the instruction fetch than operand data access An instruction fetch may be inserted between read access and write access during read modify write access Also an instruction fetch may be inserted between bus access and bus access during CPU bus clock Table 4 2 Bus Priority Order Priority Order External Bus Cycle Bus Master Low High Operand data access CPU Instruction fetc...

Page 180: ...ycle will be generated at least 2 times and bus efficiency will drop 1 External bus width 16 bits a In the case of halfword length data access When the address s LSB is 1 a byte length bus cycle will be generated 2 times b In the case of word length data access When the address s LSB is 1 bus cycles will be generated in the order of byte length bus cycle halfword length bus cycle and byte length b...

Page 181: ...7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers Data wait can be controlled via WAIT pin input An idle state can be inserted after a read write cycle by setting the BCC and DVC registers An address setup wait state and an address hold state can be inserted by setting the ASC register Remark The memory access control function is not available on μPD70F3447...

Page 182: ... Size of SRAM is 8 Bits Remark n 0 1 3 4 V850E PH2 A2 to A20 D24 to D31 CSn RD WR D16 to D23 D8 to D15 D0 to D7 BEN3 1 1 1 1 BEN2 BEN1 BEN0 A0 to A18 I O1 to I O8 CS OE WE SRAM PD444008L 512 Kwords 8 bits μ A0 to A18 I O1 to I O8 CS OE WE SRAM PD444008L 512 Kwords 8 bits μ A0 to A18 I O1 to I O8 CS OE WE SRAM PD444008L 512 Kwords 8 bits μ A0 to A18 I O1 to I O8 CS OE WE SRAM PD444008L 512 Kwords 8...

Page 183: ...Bus Width is 16 Bits and Data Size of SRAM is 16 Bits Remark n 0 1 3 4 V850E PH2 A2 to A19 D16 to D31 CSn RD BEN3 BEN2 WR D0 to D15 BEN1 BEN0 A0 to A17 I O1 to I O16 CS OE UB LB WE SRAM PD444016L 256 Kwords 16 bits μ A0 to A17 I O1 to I O16 CS OE UB LB WE SRAM PD444016L 256 Kwords 16 bits μ V850E PH2 A1 to A18 CSn RD BEN1 BEN0 WR D0 to D15 A0 to A17 I O1 to I O16 CS OE UB LB WE SRAM PD444016L 256 ...

Page 184: ...o BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output D0 to D31 input CSn output BEN0 BEN3 to output RD output WR output WAIT input T1 T2 T1 TW T2 wi...

Page 185: ...CT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output T1 T2 TI H Address Note 1 D0 to D...

Page 186: ...y BCT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output H TI T1 TW T2 Address Note 1 D...

Page 187: ...en enabled by BCT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output T1S T1 T1H T2 H Ad...

Page 188: ...epend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output T1 T2 T1 TW T2 H Address Note 1 Address D0 to D31 input BEN0 BEN3 to output WAIT input...

Page 189: ...CT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output T1 T2 TI H Address Note 1 D0 to D...

Page 190: ...by BCT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output H TI T1 TW T2 Address Note 1 ...

Page 191: ...en enabled by BCT0 and BCT1 registers 2 BEN0 to BEN3 output levels depend on the accessed type byte half word or word and the external bus size 8 16 or 32 bits specified by the BSC register Remarks 1 n 0 1 3 4 2 Bus clock fXX 2 3 The circle indicates the sampling timing 4 The dashed line indicates the high impedance state Bus clock A0 to A21 output CSn output RD output WR output T1S T1 T1H T2 H Ad...

Page 192: ...192 Chapter 5 Memory Access Control Function μPD70F3187 only User s Manual U16580EE3V1UD00 MEMO ...

Page 193: ...fer channels for ADC0 and ADC1 2 channels for DMA transfer to PWM timer TMR0 TMR1 Transfer object iRAM I O Transfer size 16 bits Dedicated transfer channels for TMR0 and TMR1 2 channels for DMA transfer from serial interfaces on reception completion Transfer object I O iRAM Transfer size 8 or 16 bits DMA request for each channel selectable Clocked serial interfaces CSIB0 CSIB1 CSI30 CSI31 Asynchro...

Page 194: ...sters 0 to 7 MAR0 to MAR7 Cautions 1 Since the internal RAM area is mapped between 3FF0000H and 3FF7FFFH the value written to the MARn register has to be in the range from 0000H to 7FFFH 2 The value set to the MARn register is increased by each DMA transfer of chan nels It does not keep the initial value after the DMA transfer ends After reset undefined R W Address MAR0 FFFFF300H MAR1 FFFFF302H MA...

Page 195: ...ed when SARn2 to SARn0 bits are equal to 011B or less Caution During DMA transfer DEn 1 the contents of the SARn register may change After each DMA transfer the contents is incremented by 1 until the final value 07H is reached When the SARn register contents becomes 07H the initial set value is reloaded After reset undefined R W Address SAR2 FFFFF314H SAR3 FFFFF316H 7 6 5 4 3 2 1 0 SARn 0 0 0 0 0 ...

Page 196: ...ter the DMA transfer ends Therefore after DMA transfer end the DTCRn register values becomes 00H 2 A DMA request becomes only effective after the DTCRn register was written Even if 00H means a transfer count of 256 is the initial value the DTRCn register must be rewritten in order to enable a new DMA transfer Remark n 0 to 7 After reset undefined R W Address DTCR0 FFFFF320H DTCR1 FFFFF322H DTCR2 F...

Page 197: ...t units Reset input clears this register to 00H Figure 6 5 DMA Status Register DMAS Remark n 0 to 7 After reset 00H R W Address DMAMC FFFFF330H 7 6 5 4 3 2 1 0 DMAMC DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DEn Control Bit of DMA Channel n 0 DMA transfer operation of channel n disabled 1 DMA transfer operation of channel n enabled After reset 00H R W Address DMAMC FFFFF332H 7 6 5 4 3 2 1 0 DMAS DMAS7 DMAS6...

Page 198: ...4 to 7 The data size of DMA channels 0 to 3 is fixed and therefore not selectable This register can be read or written in 8 bit units Reset input clears this register to 00H Figure 6 6 DMA Data Size Control Register DMDSC Remark n 4 to 7 After reset 00H R W Address DMAMC FFFFF334H 7 6 5 4 3 2 1 0 DMADSC DMADSC7 DMADSC6 DMADSC5 DMADSC4 0 0 0 0 DMADSCn Transfer Data Size of DMA Channel n 0 8 bits 1 ...

Page 199: ...er ends corresponding DTCRn register value is 00H 3 Write the DTFRn register before setting the corresponding DTCRn register According to the present transfer start factor in the DTFRn register a DMA might be started when the DTCRn register is written previously Figure 6 7 DMA Trigger Factor Registers 4 to 7 DTFR4 to DTFR7 Note Not available on μPD70F3447 Remark n 4 to 7 After reset 00H R W Addres...

Page 200: ...h DMA trigger the data will be transferred from the A D conversion result register for DMA ADDMAn into the internal RAM specified as destination While the source transfer address is fixed to the ADDMAn register of the corresponding A D converter ADCn the destination start address can be set up to any even address in the internal RAM When the DMA transfer count of a DMA channel terminates the DMA t...

Page 201: ...t of ADCn DMA channel 0 or 1 Set up A D conversion scan range in the ADMn2 register Set up the MARx register with destination start address within iRAM in Specify the DMA transfer count in the DTCRx register 1 to 256 Enable DMA transfer channel x DEx bit 1 Enable operation of A D converter n ADCEn bit 1 ADCSn bit 1 Disable operation of A D converter n ADCEn bit 0 End of initialization Clear status...

Page 202: ...pt Remark n 0 1 number of ADC channel x n number of DMA transfer channel Operation of DMA channel 0 1 DEx bit 1 DEx bit newly written ADDMARQn occured Transfer content from ADDMAn register to iRAM MARx ADDMAn Increment source pointer MARx MARx 2 Decrement DMA transfer count register DTCRx DTCRx 1 DTCRx 0 Set DMA transfer status bit DMASx 1 Generate interrupt signal INTDMAxNote yes no yes yes no no...

Page 203: ...ally Write 1 in the corresponding DEx bit of the DMAMC register again to enable the next transfer of DMA channel x The DEx bit is not cleared by hardware 2 n 0 1 number of the A D converter channel x n number of the DMA channel Setup MARx DTCRx DMAMC register 1000H 1002H 1004H 1006H 1008H 0003H 0002H 0001H 0000H 0000H 100CH 100EH 1010H 0002H 0001H 0000H 100AH 0003H Re setup DTCRx DMAMC register wr...

Page 204: ...nCC5 can be set up by the SARx register as well as the source start address in the internal RAM by the MARx register The destination end address is always fixed to TRnCC1 register which also enables the buffer reload in the timer TMRn period ref to Table 6 1 The DMA transfer count is defined by the destination start and end address However an additionally DMA trigger count is available which can b...

Page 205: ...DMA channel Set up SARx register with TMRn start address offset TRnCCR0 TRnCCR2 to TRnCCR5 Set up the MARx register with source start address in iRAM Specify the DMA transfer count in the DTCRx register 1 to 256 Clear status bit of DMA channel x DMASx bit 0 Enable DMA transfer channel x DEx bit 1 Initialization of DMA transfer for TMRn compare registers DMA channel 2 or 3 End of initialization ...

Page 206: ...DEx bit newly written INTTRnOD occurred INTTRnCD occurred Increment destination pointer m m 2 Transfer content from iRAM to TMRn compare register m MARx Increment source pointer MARx MARx 2 m Address of TRnCCR0 Decrement DMA transfer count register DTCRx DTCRx 1 DTCRx 0 Set DMA transfer status bit DMASx 1 Generate interrupt signal INTDMAx no yes no yes yes yes no no yes yes no no DMA transfer will...

Page 207: ...ransfer is not restarted automatically Write 1 in the corresponding DEx bit of the DMAMC register again to enable the next transfer of DMA channel x The DEx bit is not cleared by hardware 2 n 0 1 number of the TMR channel x n 2 number of the DMA channel 1000H 1002H 1004H 1006H 1008H 100EH 1010H 04H 02H 05H 06H 07H 04H 07H 04H 01H 0H 100AH 05 H Setup MARx DTCRx SARx register DMA transfer MARx SARx ...

Page 208: ... is incremented by 1 for each occurrence of DMA trigger When selecting 16 bits transfer data size the destination address must be even and is incremented by 2 for each DMA trigger When the DMA transfer count of a DMA channel terminates the DMA transfer is stopped and a DMA completion interrupt is generated The maximum DMA transfer count is 256 Note Not available on μPD70F3447 Table 6 2 DMA Configu...

Page 209: ... Initialization of DMA transfer for serial data reception DMA channel 4 or 5 Set up MARx register with the destination start address in iRAM Specify the DMA transfer count in the DTCRx register 1 to 256 Clear status bit of DMA channel x DMASx bit 0 Enable DMA transfer channel x DEx bit 1 End of initialization Specify the DMA trigger factor in the DTFRx register depending on the used serial interfa...

Page 210: ...A trigger factor occurred Transfer content from serial receive buffer depending on DTFRx register to iRAM MARx SIRBn or CBnRX Increment source pointer MARx MARx 2 Decrement DMA transfer count register DTCRx DTCRx 1 DTCRx 0 Set DMA transfer status bit DMASx 1 Generate interrupt signal INTDMAxNote yes no yes yes no no yes no DMA transfer will be enabled by write access to the corresponding DEn bit D...

Page 211: ... Channel 4 and 5 Trigger Signal Timing Remark m 4 5 n 0 1 1000H 1002H 1004H 1006H 1008H 0003H 0002H 0001H 0000H 0000H 100CH 100EH 1010H 0002H 0001H 0000H 100AH 0003H MARm DTCRm DTRFm DMAMCm DTCRm DMAMCm Trigger signal by DTFRm register DMA transfer MARm DTCRm INTUCnR or INTCBnR or INTCSI3n ...

Page 212: ... bits transfer data size the source address must be even and is incremented by 2 for each DMA trigger When the DMA transfer count of a DMA channel terminates the DMA transfer is stopped and a DMA completion interrupt is generated The maximum DMA transfer count is 256 Notes 1 Not available on μPD70F3447 2 The serial peripheral chip select lines SCS0 to SCS3 will not be supported by DMA transfer Tab...

Page 213: ...nnel Initialization of DMA transfer for serial data transmission DMA channel 6 or 7 Set up MARx register with the source start address in iRAM Specify the DMA transfer count in the DTCRx register 1 to 256 Clear status bit of DMA channel x DMASx bit 0 Enable DMA transfer channel x DEx bit 1 End of initialization Specify the DMA trigger factor in the DTFRx register depending on the used serial inter...

Page 214: ... Channel 6 and 7 Trigger Signal Timing Remark m 6 7 n 0 1 1000H 1002H 1004H 1006H 1008H 0003H 0002H 0001H 0000H 0000H 100CH 100EH 1010H 0002H 0001H 0000H 100AH 0003H MARm DTCRm DTRFm DMAMCm DTCRm DMAMCm Trigger signal by DTFRm register DMA transfer MARm DTCRm INTUCnT or INTCBnT or INTCSI3n ...

Page 215: ... DMA trigger factor occurred Transfer content from iRAM to serial transmit buffer spec by DTFRx register SFDBn or CBnTX MARx Increment source pointer MARx MARx 2 Decrement DMA transfer count register DTCRx DTCRx 1 DTCRx 0 Set DMA transfer status bit DMASx 1 Generate interrupt signal INTDMAx Note yes no yes yes no no yes no DMA transfer will be enabled by write access to the corresponding DEn bit D...

Page 216: ...irst after it has been finished see Figure 6 20 Figure 6 20 CPU and DMA Controller Processing of DMA Transfer Termination Example SAR2 0AH DTCR2 8 DMAS2 0 DE2 1 DMA transfer channel 2 enabled DMA transfer channel 2 forcibly disabled DMA transfer to TR0CCR3 DMA transfer to TR0CCR3 DMA transfer to TR0CCR2 DMA transfer to TR0CCR2 DMA transfer to TR0CCR1 DMA transfer to TR0CCR1 DTCR2 7 DTCR2 6 DE2 0 C...

Page 217: ...age 219 Table 6 4 shows the relations between DMA trigger factors and DMA completion interrupts Notes 1 Not available on μPD70F3447 2 An interrupt request is not generated for a signal which serves as DMA trigger factor Instead of this the defined DMA completion interrupt request is executed on the same inter rupt entry address of the DMA trigger factor Table 6 4 Relations Between DMA Trigger Fact...

Page 218: ... interface Interrupt signals without quote mark are provided to the interrupt controller INTUC0R INTUC1R INTUC0R INTUC1R INTUC0R INTUC1R INTCB0R INTCB1R INTCSI30 INTCSI31 INTCB0R INTCB1R INTCB0R INTCB1R INTCSI31 INTCSI30 INTCSI30 INTCSI31 INTUC0T INTUC1T INTUC0T INTUC1T INTUC0T INTUC1T INTCB0T INTCB1T INTCSI30 INTCSI31 INTCB0T INTCB1T INTCB0T INTCB1T INTCSI31 INTCSI30 DMA channel 4 DMA channel 5 D...

Page 219: ... priority Mask can be specified to each maskable interrupt request Valid edge for detection of external interrupt request signal can be specified Exceptions Software exceptions 32 sources Exception trap 1 source illegal op code exception Interrupt exception sources are listed in Table 7 1 Table 7 1 Interrupt Exception Source List 1 5 Type Classification Interrupt Exception Source Default Priority ...

Page 220: ... 000001E0H nextPC Interrupt INTTR1OV PIC23 TR1CNT overflow TMR1 23 01F0H 000001F0H nextPC Interrupt INTTR1CC0 PIC24 TIR10 capture input TR1CCR0 match TMR1 24 0200H 00000200H nextPC Interrupt INTTR1CC1 PIC25 TIR11 capture input TR1CCR1 match TMR1 25 0210H 00000210H nextPC Interrupt INTTR1CC2 PIC26 TIR12 capture input TR1CCR2 match TMR1 26 0220H 00000220H nextPC Interrupt INTTR1CC3 PIC27 TIR13 captu...

Page 221: ...h TMP4 54 03E0H 000003E0H nextPC Interrupt INTP4CC1 PIC55 TIP41 capture input TP4CCR1 match TMP4 55 03F0H 000003F0H nextPC Interrupt INTP5OV PIC56 TMP5overflow TMP5 56 0400H 00000400H nextPC Interrupt INTP5CC0 PIC57 TIP50 capture input TP5CCR0 match TMP5 57 0410H 00000410H nextPC Interrupt INTP5CC1 PIC58 TIP51 capture input TP5CCR1 match TMP5 58 0420H 00000420H nextPC Interrupt INTP6OV PIC59 TMP6 ...

Page 222: ...CSIB1 reception completion DMA transfer completion CSIB1 Note DMAC 83 05B0H 000005B0H nextPC Interrupt INTCB1RE PIC84 Note CSIB1 receive error CSIB1 Note 84 05C0H 000005C0H nextPC Interrupt INTC30OVF PIC85 CSI30 overrun CSI30 85 05D0H 000005D0H nextPC Interrupt INTC30 PIC86 CSI30 transmission enable DMA transfer completion CSI30 DMAC 86 05E0H 000005E0H nextPC Interrupt INTC31OVF PIC87 Note CSI31 o...

Page 223: ...e illegal instruction when an illegal opcode exception occurs is calculated by Restored PC 4 Maskable Interrupt INTAD1 PIC96 ADC1 conversion completion DMA transfer completion ADC1 DMAC 96 0680H 00000680H nextPC Interrupt INTCC10 PIC97 Note CC10 capture input compare match TMENC1 Note 97 0690H 00000690H nextPC Interrupt INTCC11 PIC98 Note CC11capture input compare match TMENC1 Note 98 06A0H 000006...

Page 224: ... of the interrupt mode register 0 INTM0 is detected at the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed PSW NP 1 the acknowledgment of another non maskable interrupt request is held pending The pending NMI is acknowledged after the original service program of the non maskable interrupt under execution has been terminated by the RETI instruc...

Page 225: ...of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is shown in Figure 7 1 Figure 7 1 Processing Configuration of Non Maskable Interrupt Non maskable interrupt request FEPC Restored PC FEPSW PSW ECR FECC Exception co...

Page 226: ...request is generated twice while a NMI service program is being executed Main routine NMI request NMI request PSW NP 1 NMI request held pending because PSW NP 1 Pending NMI request processed Main routine NMI request NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two NMI requests are generated NMI request Held pending because...

Page 227: ... is 1 2 Transfers control back to the address of the restored PC and PSW Figure 7 3 illustrates how the RETI instruction is processed Figure 7 3 RETI Instruction Processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt processing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set...

Page 228: ...n be specified by the interrupt mode register 0 INTM0 The valid edge of the external NMI pin input can be specified by the ESN0 and ESN1 bits The INTM0 register can be read written in 8 bit or 1 bit units Figure 7 5 NMI Edge Detection Specification Interrupt Mode Register 0 INTM0 31 8 7 6 5 4 3 2 1 0 After reset 00000020H PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z N...

Page 229: ...ervicing of interrupts having a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose re...

Page 230: ...PSW ID 0 as set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing INT input xxIF 1 No xxMK 0 No Is the interrupt mask released Yes Yes No No No Maskable interrupt request Interrupt request held pending PSW NP PSW ID 1 1 Interrupt request held pending 0 0 Interrupt processing CPU processing INTC accepted Yes Yes Yes Priority higher than that of ...

Page 231: ...tored PC and PSW Figure 7 7 illustrates the processing of the RETI instruction Figure 7 7 RETI Instruction Processing Note For the ISPR register see 7 3 6 In service priority register ISPR on page 242 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt processing in order to restore the PC and PSW correctly during recovery by the RETI instru...

Page 232: ...more interrupts having the same priority level specified by the PRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 7 1 Interrupt Exception Source List on page 219 The programmable priority control customizes interrupt requests into eigh...

Page 233: ...s Main routine EI EI Interrupt request a level 3 Processing of a Processing of b Processing of c Interrupt request c level 3 Processing of d Processing of e EI Interrupt request e level 2 Processing of f EI Processing of g Interrupt request g level 1 Interrupt request h level 1 Processing of h Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are...

Page 234: ...level 3 Interrupt request n level 1 Processing of o Interrupt request p level 2 Interrupt request q level 1 Interrupt request r level 0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is ack...

Page 235: ...errupt servicing restore the values of EIPC and EIPSW after executing the DI instruction Default priority a b c Main routine EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt request b and c are acknowledged first according to their priorities Because...

Page 236: ...owledged Remark n 0 to 105 see Table 7 2 Addresses and Bits of Interrupt Control Registers After reset 47H R W Address Refer to Table 7 2 7 6 5 4 3 2 1 0 PICn IFn MKn 0 0 0 PRn2 PRn1 PRn0 IFn Interrupt Request Flag nNote 0 Interrupt request is not issued 1 Interrupt request issued MKn Interrupt Mask Flag n 0 Interrupt servicing enabled 1 Interrupt servicing disabled IFn flag hold pending PRn2 PRn1...

Page 237: ...K17 0 0 0 PR172 PR171 PR170 INTTR0CC3 FFFFF134H PIC18 IF18 MK18 0 0 0 PR182 PR181 PR180 INTTR0CC4 FFFFF136H PIC19 IF19 MK19 0 0 0 PR192 PR191 PR190 INTTR0CC5 FFFFF138H PIC20 IF20 MK20 0 0 0 PR202 PR201 PR200 INTTR0CD FFFFF13AH PIC21 IF21 MK21 0 0 0 PR212 PR211 PR210 INTTR0OD FFFFF13CH PIC22 IF22 MK22 0 0 0 PR222 PR221 PR220 INTTR0ER FFFFF13EH PIC23 IF23 MK23 0 0 0 PR232 PR231 PR230 INTTR1OV FFFFF1...

Page 238: ...NTP5CC0 FFFFF184H PIC58 IF58 MK58 0 0 0 PR582 PR581 PR580 INTP5CC1 FFFFF186H PIC59 IF59 MK59 0 0 0 PR592 PR591 PR590 INTP6OV FFFFF188H PIC60 IF60 MK60 0 0 0 PR602 PR601 PR600 INTP6CC0 FFFFF18AH PIC61 IF61 MK61 0 0 0 PR612 PR611 PR610 INTP6CC1 FFFFF18CH PIC62 IF62 MK62 0 0 0 PR622 PR621 PR620 INTP7OV FFFFF18EH PIC63 IF63 MK63 0 0 0 PR632 PR631 PR630 INTP7CC0 FFFFF190H PIC64 IF64 MK64 0 0 0 PR642 PR...

Page 239: ...0 0 PR902 PR901 PR900 INTUC0R FFFFF1C6H PIC91 IF91 MK91 0 0 0 PR912 PR911 PR910 INTUC0T FFFFF1C8H PIC92 IF92 MK92 0 0 0 PR922 PR921 PR920 INTUC1RE FFFFF1CAH PIC93 IF93 MK93 0 0 0 PR932 PR931 PR930 INTUC1R FFFFF1CCH PIC94 IF94 MK94 0 0 0 PR942 PR941 PR940 INTUC1T FFFFF1CEH PIC95 IF95 MK95 0 0 0 PR952 PR951 PR950 INTAD0 FFFFF1D0H PIC96 IF96 MK96 0 0 0 PR962 PR961 PR960 INTAD1 FFFFF1D2H PIC97 Note IF...

Page 240: ...it as a reserved word If a bit is manipulated using the name of MKn the contents of the PICn register instead of the IMRm register are rewritten as a result the contents of the IMRm register are also rewritten Figure 7 11 Interrupt Mask Registers 0 to 2 IMR0 to IMR2 Remark n 0 to 105 see Table 7 1 After reset FFFFH R W Address IMR0 FFFFF100H IMR0L FFFFF100H IMR0H FFFFF101H 15 14 13 12 11 10 9 8 IM...

Page 241: ...R W Address IMR4 FFFFF108H IMR4L FFFFF108H IMR4H FFFFF109H 15 14 13 12 11 10 9 8 IMR4 MK79 MK78 Note MK77 Note MK76 Note MK75 Note MK74 MK73 MK72 MK71 MK70 MK69 MK68 MK67 MK66 MK65 MK64 After reset FFFFH R W Address IMR5 FFFFF10AH IMR5L FFFFF10AH IMR5H FFFFF10BH 15 14 13 12 11 10 9 8 IMR5 MK95 MK94 MK93 MK92 MK91 MK90 MK89 MK88 Note MK87 Note MK86 MK85 MK84 Note MK83 Note MK82 Note MK81 MK80 After...

Page 242: ...e interrupt servicing or exception processing Reset input clears this register to 00H This register is read only in 8 bit or 1 bit units Caution In the interrupt enabled EI state if an interrupt is acknowledged during the reading of the ISPR register the value of the ISPR register may be read after the bit is set 1 by this interrupt acknowledgment To read the value of the ISPR register properly be...

Page 243: ...struction or LDSR instruction when referencing the PSW Non maskable interrupt and exceptions are acknowledged regardless of this flag When a maskable interrupt is acknowledged the ID flag is automatically set to 1 by hardware The interrupt request generated during the acknowledgement disabled period ID 1 can be acknowledged when the IFn bit of the interrupt control register PICn is set to 1 and th...

Page 244: ...askable external interrupt input pin INTPn can be selected by program n 0 to 12 The edge that can be selected as the valid edge is one of the following Rising edge Falling edge Both the rising and falling edges The edge detected INTPn signal becomes an interrupt source The valid edge is specified by interrupt mode registers 0 to 3 INTM0 to INTM3 ...

Page 245: ...the interrupt status flag after changing the bits ESn0 ESn1 of the interrupt channel n 0 to 2 After reset 00H R W Address FFFFF880H 7 6 5 4 3 2 1 0 INTM0 ES21 ES20 ES11 ES10 ES01 ES00 ESN1 ESN0 ES21 ES20 Valid Edge Specification of INTP2 pin input 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 Valid Edge Specification of INTP1 pin input 0 0 Fall...

Page 246: ...he interrupt status flag after changing the bits ESn0 ESn1 of the interrupt channel n 3 to 6 After reset 00H R W Address FFFFF882H 7 6 5 4 3 2 1 0 INTM1 ES61 ES60 ES51 ES50 ES41 ES40 ES31 ES30 ES61 ES60 Valid Edge Specification of INTP6 pin input 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES51 ES50 Valid Edge Specification of INTP5 pin input 0 0 Falli...

Page 247: ...interrupt status flag after changing the bits ESn0 ESn1 of the interrupt channel n 7 to 10 After reset 00H R W Address FFFFF884H 7 6 5 4 3 2 1 0 INTM1 ES101 ES100 ES91 ES90 ES81 ES80 ES71 ES70 ES101 ES100 Valid Edge Specification of INTP10 pin input 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES91 ES90 Valid Edge Specification of INTP9 pin input 0 0 Fa...

Page 248: ...0 ESn1 may trigger an unintended interrupt event for the respective interrupt channels Be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits ESn0 ESn1 of the interrupt channel n 11 12 After reset 00H R W Address FFFFF886H 7 6 5 4 3 2 1 0 INTM1 0 0 0 0 ES121 ES120 ES111 ES110 ES121 ES120 Valid Edge Specification of INTP12 pin input 0 0 Falling ...

Page 249: ... exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of PSW 5 Loads the handler address 00000040H or 00000050H of the software exception routine in the PC and transfers control The processing of a software exception is shown below Figure 7 19 Software Exception Processing Note TRAP instruction format TRAP vector the vector is a value from 0 to 1FH The handler...

Page 250: ...ol to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 7 20 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception process in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 0 using the LDSR ...

Page 251: ...flag used to indicate that exception processing is in progress This flag is set when an exception occurs Figure 7 21 Exception Status Flag EP 31 8 7 6 5 4 3 2 1 0 After reset 00000020H PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z EP Exception Processing Status 0 Exception processing not in progress 1 Exception processing in progress ...

Page 252: ... instruction applicable to this illegal instruction is executed Figure 7 22 Illegal Opcode Caution Caution Since it is possible that this instruction may be assigned to an illegal opcode in the future it is recommended that it not be used Remark x don t care 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine 1 Saves the re...

Page 253: ...and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 24 illustrates the restore processing from an exception trap Figure 7 24 Restore Processing from Exception Trap Exception trap ILGOP occurs DBPC DBPSW PSW NP PSW EP PSW ID PC restored PC PSW 1 1 1 00000060H Exception proces...

Page 254: ...he next instruction interrupt is held pending The interrupt request non sample instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the command register PRCMD The store or bit manipulation instructions excluding the tst1 instruction for the following interrupt related registers Interrupt control register PICn Interrupt mask registers...

Page 255: ...emark fX External resonator or external clock frequency fXX Internal system clock An external resonator or crystal is connected to X1 and X2 pins whose frequency is multiplied by the PLL synthesizer By this an internal system clock fXX is generated that is 4 times the frequency fX of the external resonator or crystal The clock controller enables PLL automatically and starts clock supply to the sys...

Page 256: ...eved due to a combination of HALT mode and normal operation mode The system is switched to HALT mode by a specific instruction the HALT instruction Figure 8 2 shows the operation of the clock generator in normal operation mode and HALT mode Figure 8 2 Power Save Mode State Transition Diagram Notes 1 Non maskable interrupt request signal NMI or unmasked maskable interrupt request signal 2 The oscil...

Page 257: ... power consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation Cautions 1 Insert five or more NOP instructions after the HALT instruction 2 If the HALT instruction is executed while an interrupt request is being held pending the HALT mode is set but is released immediately by the pending interrupt request Table 8 1 Op...

Page 258: ...r than or same as the interrupt currently being serviced is generated the HALT mode is released but the newly generated interrupt request signal is not acknowledged The interrupt request signal itself is retained If an interrupt request signal with a priority higher than that of the interrupt currently being serviced is issued including a non maskable interrupt request signal the HALT mode is rele...

Page 259: ... operations PWM output Interval timer External event counter operation not possible when clock is stopped One shot pulse output Pulse width measurement 9 2 Function Outline Capture trigger input signal 2 External trigger input signal 1 Clock select 8 External event count input 1 Readable counter 1 Capture compare reload register 2 Capture compare match interrupt 2 Timer output TOPn0 TOPn1 2 ...

Page 260: ...tion Timer register 16 bit counter Registers TMPn capture compare registers 0 1 TPnCCR0 TPnCCR1 TMPn counter register TPnCNT CCR0 buffer register CCR1 buffer register Timer input 2 8 TIPm0 TIPm1 TTRGPm TEVTPm Note Timer output 2 8 TOPm0 TOPm1 Note 1 1 TOP81 Control registers TMPn control registers 0 1 TPnCTL0 TPnCTL1 TMPn I O control registers 0 to 2 TPnIOC0 to TPnIOC2 TMPn option registers 0 1 TP...

Page 261: ...0 a Use as compare register TPnCCR0 can be rewritten when TPnCE 1 The timing at which the TPnCCR0 rewrite values become valid when TPnCE 1 is as follows b Use as capture register TMP0 to TMP7 The counter value is saved to TPnCCR0 upon capture trigger TIPn0 input edge detection TMP8 Since TMP8 has no external input pin the capture function can only be used internally for capturing the interrupt sig...

Page 262: ... a Use as compare register TPnCCR1 can be rewritten when TPnCE 1 The timing at which the TPnCCR1 rewrite values become valid when TPnCE 1 is as follows b Use as capture register TMP0 to TMP7 The counter value is saved to TPnCCR1 upon capture trigger TIPn1 input edge detection TMP8 Since TMP8 has no external input pin the capture function can only be used internally for capturing the interrupt sign...

Page 263: ...it is cleared to 0 Figure 9 4 TMPn Counter Register TPnCNT Remark The value of the TPnCNT register is cleared to 0000H when the TPnCE bit 0 If the TPnCNT register is read at this time the value of the 16 bit counter FFFFH is not read but 0000H is read After reset 0000H R Address TP0CNT FFFFF60AH TP1CNT FFFFF61AH TP2CNT FFFFF62AH TP3CNT FFFFF63AH TP4CNT FFFFF64AH TP5CNT FFFFF65AH TP6CNT FFFFF66AH T...

Page 264: ... FFFFF620H TP3CTL0 FFFFF630H TP4CTL0 FFFFF640H TP5CTL0 FFFFF650H TP6CTL0 FFFFF660H TP7CTL0 FFFFF670H TP8CTL0 FFFFF680H 7 6 5 4 3 2 1 0 TPnCTL0 TPnCE 0 0 0 0 TPnCKS2 TPnCKS1 TPnCKS0 n 0 to 8 TPnCE Timer Pn Operation Control 0 Internal operating clock operation disabled TMPn reset asynchronously 1 Internal operating clock operation enabled Internal operating clock control and TMPn asynchronous reset...

Page 265: ... Mode Selection 0 Timer Pn operates in single operation mode 1 Timer Pn operates in synchronous operation modeNote This bit supports synchronous operation of two or more timer P Two groups of timers exist which can be synchronized TMP0 to TMP3 with TMP0 as master and TMP4 to TMP7 with TMP4 as master Note Synchronous operation mode is not available for TMP8 n 8 TPnEST Software Trigger Control 0 No ...

Page 266: ...rnal clock selected by bits TPnCKS2 to TPnCKS0 1 Use external clock input TEVTPn input edge Note When TPnEEE 1 external clock input TEVTPn the valid edge is specified by bits TPnEES1 and TPnEES0 Note External clock input pin is not available for TMP8 n 8 TPnMD2 TPnMD1 TPnMD0 Timer Mode Selection 0 0 0 Interval timer mode Note 1 2 0 0 1 External event count mode Note 1 2 3 0 1 0 External trigger pu...

Page 267: ...OC0 FFFFF612H TP2IOC0 FFFFF622H TP3IOC0 FFFFF632H TP4IOC0 FFFFF642H TP5IOC0 FFFFF652H TP6IOC0 FFFFF662H TP7IOC0 FFFFF672H TP8IOC0 FFFFF682H 7 6 5 4 3 2 1 0 TPnIOC0 0 0 0 0 TPnOL1 TPnOE1 TPnOL0 TPnOE0 n 0 to 8 TPnOL1 Timer Output Level Setting TOPn1 pin 0 Normal output Low level when output is inactive 1 Inverted output High level when output is inactive TPnOE1 Timer Output Control TOPn1 pin 0 Time...

Page 268: ...e can be written when TPnCE 1 If rewriting was mistakenly performed set TPnCE 0 and then set the bits again 2 The TPnIS3 to TPnIS0 bits are valid only in the free running mode and the pulse width measurement mode In all other modes a capture operation is not possible Remark n 0 to 8 After reset 00H R W Address TP0IOC1 FFFFF603H TP1IOC1 FFFFF613H TP2IOC1 FFFFF623H TP3IOC1 FFFFF633H TP4IOC1 FFFFF643...

Page 269: ...TPnEES0 bits are valid only when TPnEEE 1 or when the external event count mode TPnMD2 to TPnMD0 001B of the TPnCTL1 register has been set Remark n 0 to 7 After reset 00H R W Address TP0IOC2 FFFFF604H TP1IOC2 FFFFF614H TP2IOC2 FFFFF624H TP3IOC2 FFFFF634H TP4IOC2 FFFFF644H TP5IOC2 FFFFF654H TP6IOC2 FFFFF664H TP7IOC2 FFFFF674H TP8IOC2 FFFFF684H 7 6 5 4 3 2 1 0 TPnIOC2 0 0 0 0 TPnEES1 TPnEES0 TPnETS1...

Page 270: ...nCCR1 register capture compare selection 0 Compare register selection 1 Capture register selection The TPnCCS1 bit settings are valid only in the free running mode TPnCCS0 TPnCCR0 register capture compare selection 0 Compare register selection 1 Capture register selection The TPnCCS0 bit settings are valid only in the free running mode TPnOVF Timer P overflow detection flag 0 No overflow occurrenc...

Page 271: ...FFFF6F0H 7 6 5 4 3 2 1 0 TPIC0 0 0 0 0 TPIC03 TPIC02 TPIC01 TPIC00 TPIC03 TP3CCR1 Register Capture Source Input Selection 0 Capture source input is pin P17 TIP31 1 Capture source input is pin P16 TIP30 TPIC02 TP2CCR1 Register Capture Source Input Selection 0 Capture source input is pin P15 TIP21 1 Capture source input is pin P14 TIP20 TPIC01 TP1CCR1 Register Capture Source Input Selection 0 Captur...

Page 272: ...ble After reset 00H R W Address FFFFF6F2H 7 6 5 4 3 2 1 0 TPIC1 0 0 TIP15 TIP14 TPIC13 TPIC12 TPIC11 TPIC10 TPIC15 Note TIPC14 TIPC13 Capture Source Input Selection of TP7CCR0 TP7CCR1 0 0 0 Pin P26 TIP70 Pin P27 TIP71 0 0 1 Pin P26 TIP70 0 1 0 AFCAN0 time trigger Pin P27 TIP71 0 1 1 Pin P26 TIP70 1 0 0 Pin P26 TIP70 AFCAN1 time triggerNote 1 0 1 1 1 0 AFCAN0 time trigger 1 1 1 TPIC12 TP6CCR1 Regis...

Page 273: ...egister 1 TPIC1 Note Setting TIPC22 to 1 is prohibited for μPD70F3447 since TMENC1 is not available After reset 00H R W Address FFFFF6F4H 7 6 5 4 3 2 1 0 TPIC2 0 0 0 0 0 TPIC22 TPIC21 TPIC20 TIPC22 Note Capture Source Input Selection of TP8CCR0 TP8CCR1 0 INTTT0CC0 signal of TMT0 INTTT1CC1 signal of TMT0 1 INTCM10 signal of TMENC1Note INTCM11 signal of TMENC1Note TPIC21 TT1CCR1 Register Capture Sou...

Page 274: ...on TPnCE 1 but the write method anytime rewrite reload differs depending on the mode 1 Anytime rewrite When the TPnCCRm register is written during timer operation the write data is transferred at that time to the CCRm buffer register and used as the 16 bit counter comparison value Remark n 0 to 8 m 0 1 Operation TPnEST Software Trigger Bit TTRGPn0 External Trigger Input Capture Compare Mode Compar...

Page 275: ...e operation in the interval timer mode 2 n 0 to 8 START Initial settings INTTPnCC0 output TPnCCR1 rewrite Transfer to CCR1 buffer register TPnCCR0 rewrite Transfer to CCR0 buffer register Match between CCR0 buffer register and 16 bit counter 16 bit counter clear start Timer operation enable TPnCE 1 Transfer of TPnCCR0 TPnCCR1 values to CCR0 buffer register and CCR1 buffer register ...

Page 276: ...R0 register 0000H to FFFFH D11 D12 Setting values of TPnCCR1 register 0000H to FFFFH 2 The above timing chart illustrates an example of the operation in the interval timer mode 3 n 0 to 8 16 bit counter TPnCCR0 TPnCCR1 INTTPnCC0 INTTPnCC1 CCR0 buffer register CCR1 buffer register D01 D01 D01 D01 0000H TPnCE 1 D02 D02 D11 D11 D11 D12 D12 D12 D02 D11 0000H D12 ...

Page 277: ... Thereafter the values of the TPnCCR0 and the TPnCCR1 register are reloaded upon TPnCCR0 register match Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register Thus even when wishing only to rewrite the value of the TPnCCR0 register also write the same value to the TPnCCR1 register Figure 9 16 Basic Operation Flow for Reload Batch Rewrite Caution Writin...

Page 278: ...g value of TPnCCR0 register 0000H to FFFFH D11 D12 Setting value of TPnCCR1 register 0000H to FFFFH 2 The above timing chart illustrates the operation in the PWM mode as an example 3 n 0 to 8 D01 D01 D02 D03 0000H D01 D11 D12 D12 D02 D03 0000H D11 D12 D12 TPnCE 1 Note D02 D02 D03 D11 D12 D12 D12 D12 16 bit counter TPnCCR0 TPnCCR1 INTTPnCC0 INTTPnCC1 CCR0 buffer register CCR1 buffer register Note S...

Page 279: ...r the setting value of the TPnCCR1 register is transferred to the CCR1 buffer register and compared with the value of the 16 bit counter and an interrupt request INTTPnCC1 is output if these values match Moreover TOPnm pin output is also possible by setting the TPnOEm bit to 1 When the TPnCCR1 register is not used it is recommended to set FFFFH as the setting value for the TPnCCR1 register Remark ...

Page 280: ...Note The 16 bit counter is not cleared when its value matches the value of TPnCCR1 Remarks 1 D1 D2 Setting values of TPnCCR0 register 0000H to FFFFH D3 Setting value of TPnCCR1 register 0000H to FFFFH 2 Interval time tDn Dn 1 count clock cycle 3 n 0 to 8 TPnCE 1 D1 D1 D2 D1 0000H 0000H D3 D3 D2 D1 D2 D3 D3 D3 FFFFH 16 bit counterNote TPnCCR0 TPnCCR1 INTTPnCC0 INTTPnCC1 TOPn0 TOPn1 tD1 tD1 tD2 L H ...

Page 281: ...utput TPnOE0 TPnOE1 1 TPnOL0 0 TPnOL1 1 Remarks 1 D1 Setting value of TPnCCR0 register 0000H to FFFFH D2 Setting value of TPnCCR1 register 0000H to FFFFH 2 Interval time tDn Dn 1 count clock cycle 3 n 0 to 8 0000H D1 D1 FFFFH TPnCCR0 TPnCCR1 INTTPnCC0 INTTPnCC1 TOPn0 TOPn1 0000H D2 D2 TPnCE 1 D1 D2 D1 D2 D1 D2 tD1 tD2 tD1 tD2 tD1 tD2 16 bit counter CCR0 buffer register CCR1 buffer register ...

Page 282: ... and the value of the CCR0 buffer register 16 bit counter clearing using the TPnCCR1 register is not performed However the setting value of the TPnCCR1 register is transferred to the CCR1 buffer register and compared with the value of the 16 bit counter and an interrupt request INTTPnCC1 is output if these values match Moreover TOPn1 pin output is also possible by setting the TPnOE1 bit to 1 The T...

Page 283: ... register Remark n 0 to 7 START Initial settings External event count mode setting TPnCTL0 TPnMD2 to TPnMD0 001 Note 1 Valid edge setting TPnIOC2 TPnEES1 TPnEES0 Compare register setting TPnCCR0 TPnCCR1 INTTPnCC1 output INTTPnCC0 output Timer operation enable TPnCE 1 Transfer of TPnCCR0 TPnCCR1 values to CCR0 buffer register and CCR1 buffer register Match between 16 bit counter and CCR1 buffer reg...

Page 284: ...D2 D3 rewrite of TPnCCR0 only no TOPn1 output Remarks 1 D1 D2 Setting values of TPnCCR0 register 0000H to FFFFH D3 Setting value of TPnCCR1 register 0000H to FFFFH 2 Event count Dn 1 3 n 0 to 7 16 bit counter INTTPnCC0 D1 D2 D1 FFFFH D3 D3 D3 INTTPnCC1 TPnCCR0 D1 TPnCE 1 TPnCCR1 D2 0000H D2 D1 D3 D3 0000H CCR0 buffer register CCR1 buffer register ...

Page 285: ...D1 D2 no TPnCCR0 TPnCCR1 rewrite TOPn1 output Remarks 1 D1 Setting value of TPnCCR0 register 0000H to FFFFH D2 Setting value of TPnCCR1 register 0000H to FFFFH 2 Event count Dn 1 3 n 0 to 7 16 bit counter D1 INTTPnCC0 D1 D2 FFFFH TPnCCR1 INTTPnCC1 TPnCCR0 D2 TPnCE 1 TOPn1 D1 D2 D1 D2 D1 0000H CCR0 buffer register CCR1 buffer register D2 0000H ...

Page 286: ...iming is controlled by writing to the TPnCCR1 register Thus even when wishing only to rewrite the value of the TPnCCR0 register also write the same value to the TPnCCR1 register Reload is disabled even when only the TPnCCR0 register is rewritten To stop timer P set TPnCE 0 If the external trigger TTRGPn pin input edge is detected several times in the external trigger pulse mode the 16 bit counter ...

Page 287: ...TPnEEE 0 TPnCTL0 TPnCKS2 to TPnCKS0 External trigger pulse output mode setting TPnCTL1 TPnMD2 to TPnMD0 010 Compare register setting TPnCCR0 TPnCCR1 Match between 16 bit counter and TPnCCR1Note INTTPnCC1 output INTTPnCC0 output External trigger TIPn0 pin input 16 bit counter start Match between 16 bit counter and TPnCCR0 16 bit counter clear start 16 bit counter clear start External trigger TIPn0 ...

Page 288: ...12 Setting value of TPnCCR1 register 0000H to FFFFH 2 TOPn1 output duty Setting value of TPnCCR1 register Setting value of TP0CCR0 register TOPn1 output cycle Setting value of TPnCCR0 register Count clock cycle 3 n 0 to 7 TPnCE 1 D11 D11 D12 D11 D12 D11 D12 D02 D12 D02 D01 D01 D01 D02 D02 FFFFH 16 bit counter External trigger TIPn0 pin TPnCCR0 TPnCCR1 TOPn0 TOPn1 CCR0 buffer register CCR1 buffer r...

Page 289: ...s when the 16 bit counter has stopped at 0000H In the one shot pulse mode the TPnCCR0 and TPnCCR1 registers can be rewritten when TPnCE 1 The setting values rewritten to the TPnCCR0 and TPnCCR1 registers become valid following execution of a write instruction from the CPU at which time they are transferred to the CCR0 buffer register and the CCR0 buffer register through anytime write and become th...

Page 290: ...er Remark n 0 to 8 START Initial settings Clock selection TPnCTL1 TPnEEE 0 TPnCTL0 TPnCKS2 to TPnCKS0 One shot pulse mode setting TPnCTL1 TPnMD2 to TPnMD0 011B Compare register setting TPnCCR0 TPnCCR1 Match between 16 bit counter and CCR1 buffer registerNote 2 INTTPnCC1 output INTTPnCC0 output External trigger TEVTPn pin inputNote 1 or TPnEST 1 16 bit counter start Match between 16 bit counter and...

Page 291: ...ailable for TMP8 n 8 Remarks 1 D0 Setting value of TPnCCR0 register 0000H to FFFFH D1 Setting value of TPnCCR1 register 0000H to FFFFH 2 Delay time of one shot pulse output TOPn1 when external pin edge detection trigger is used TPnCCR1 value 1 Selected count clock 2 fXX TTRGPn input filter delay 3 n 0 to 8 TPnCE 1 TPnEST 1 D1 D0 D1 D0 D1 D0 D0 D0 D1 D1 FFFFH 16 bit counter External trigger TTRGPn ...

Page 292: ... then write to the TPnCCR1 register before the 16 bit counter value and the TPnCCR0 register value match Thereafter the values of the TPnCCR0 register and the TPnCCR1 register are reloaded upon a TPnCCR0 register match Whether to enable or disable the next reload timing is controlled by writing to the TPnCCR1 register Thus even when wishing only to rewrite the value of the TPnCCR0 register also wr...

Page 293: ...ttings Clock selection TPnCTL0 TPnCKS2 to TPnCKS0 PWM mode settings TPnCTL1 TPnMD2 to TPnMD0 100B Compare register setting TPnCCR0 TPnCCR1 Match between 16 bit counter and CCR1 buffer register TOPn1 low level output Match between 16 bit counter and CCR0 buffer register 16 bit counter clear start TOPn1 high level output INTTPnCC1 output INTTPnCC0 output Timer operation enable TPnCE 1 Transfer of TP...

Page 294: ...M mode setting TPnCTL1 TPnMD2 to TPnMD0 100B Compare register setting TPnCCR0 TPnCCR1 Match between 16 bit counter and TPnCCR1 TOPn1 low level output Match between 16 bit counter and TPnCCR0 16 bit counter clear start TOPn1 high level output INTTPnCC1 output INTTPnCC0 output Reload enable INTTPnCC0 output TPnCCR1 rewrite TPnCCR0 rewrite Match between CCR0 buffer register and 16 bit counter 16 bit ...

Page 295: ...values of TPnCCR1 register 0000H to FFFFH 2 TOPn1 output duty factor Setting value of TPnCCR1 register Setting value of TP0CCR0 register 1 TOPn1 output cycle Setting value of TPnCCR0 register 1 Count clock cycle TOPn0 output toggle width Setting value of TPnCCR0 register 1 Count clock cycle 3 n 0 to 8 TPnCE 1 16 bit counter TPnCCR0 TPnCCR1 TOPn1 TOPn0 CCR0 buffer register CCR1 buffer register 0000...

Page 296: ...10 D11 D12 D13 Setting values of TPnCCR1 register 0000H to FFFFH 2 TOPn1 output duty factor Setting value of TPnCCR1 register Setting value of TP0CCR0 register 1 TOPn1 output cycle Setting value of TPnCCR0 register 1 Count clock cycle TOPn0 output toggle width Setting value of TPnCCR0 register 1 Count clock cycle 3 n 0 to 8 TPnCE 1 16 bit counter TPnCCR0 TPnCCR1 TOPn1 TOPn0 0000H 0000H D10 D11 D12...

Page 297: ...rrupt is output upon a match between the 16 bit counter and the CCR1 buffer register in the free running mode interval function Rewrite during compare timer operation is enabled and performed with anytime write Once the compare value has been written synchronization with the internal clock is done and this value is used as the 16 bit counter comparison value When timer output TOPn1 has been enable...

Page 298: ... of the 16 bit counter is saved to the TPnCCR0 register upon TIPn0 pinNote 1 edge detection Notes 1 Since TMP8 has no external input pin the capture function can only be used internally for capturing the interrupt signal INTTT0CC0 of TMT0 or INTCM10 of TMENC1 into the TP8CCR0 register or the interrupt signal INTTT0CC1 of TMT0 or INTCM11 of TMENC1 into the TP8CCR1 register respectively which is spe...

Page 299: ... of TPnCCR1 value to CCR1 buffer register TIPn1 edge detection capture of 16 bit counter value to TPnCCR1 TIPn0 edge detection capture of 16 bit counter value to TPnCCR0 16 bit counter overflow Timer operation enable TPnCE 1 TIPn0 edge detection capture of 16 bit counter value to TPnCCR0 16 bit counter overflow Match between CCR1 buffer register and 16 bit counter Timer operation enable TPnCE 1 Tr...

Page 300: ...se trigger is input Moreover when TPnOEm 1 is set TOPnm performs toggle output upon a match between the 16 bit counter and the CCRm buffer register Figure 9 29 Basic Operation Timing in Free Running Mode TPnCCS1 0 TPnCCS0 0 Note TOPn0 output pin is not available for TMP8 n 8 Remarks 1 D00 D01 Setting values of TPnCCR0 register 0000H to FFFFH D10 D11 Setting values of TPnCCR1 register 0000H to FFFF...

Page 301: ...sing the overflow flag TPnOVF However if overflow occurs twice 2 or more free running cycles the capture trigger interval cannot be judged with the TPnOVF flag In this case the system should be revised Figure 9 30 Basic Operation Timing in Free Running Mode TPnCCS1 1 TPnCCS0 1 Remarks 1 D00 D01 Values captured to TPnCCR0 register 0000H to FFFFH D10 D11 Values captured to TPnCCR1 register 0000H to ...

Page 302: ...he TPnCCR0 register as an interval function Even if TPnOE1 1 is set to realize the capture function the TPnCCR1 register cannot control TOPn1 Figure 9 31 Basic Operation Timing in Free Running Mode TPnCCS1 1 TPnCCS0 0 Remarks 1 D00 D01 Setting values of TPnCCR0 register 0000H to FFFFH D10 D11 D12 D13 D14 D15 Values captured to TPnCCR1 register 0000H to FFFFH 2 TIPn1 Set to detection of both rising...

Page 303: ...32 Basic Operation Timing in Free Running Mode TPnCCS1 0 TPnCCS0 1 Remarks 1 D00 D01 D02 D03 Values captured to TPnCCR0 register 0000H to FFFFH D10 D11 D12 Setting value of TPnCCR1 register 0000H to FFFFH 2 TIPn0 Set to falling edge detection TPnIS1 TPnIS0 10B 3 n 0 to 7 5 Overflow flag When the counter overflows from FFFFH to 0000H in the free running mode the overflow flag TPnOVF is set to 1 and...

Page 304: ...elected capture input sources and specified edge detection three different measurement methods can be applied 1 Pulse period measurement 2 Alternating pulse width and pulse space measurement This requires a fast interrupt handling in order to measure pulse width and pulse space correctly 3 Simultaneous pulse width and pulse space measurement Both capture inputs are required to measure pulse width ...

Page 305: ...unting Figure 9 33 Flowchart of Pulse Period Measurement Note External pulse input is possible for both TIPn0 and TIPn1 but only one should be selected for the pulse period measurement Specify either rising edge or falling edge for edge detection Specify the edge of the external input pulse that is not used as no edge detection Remark n 0 to 7 m 0 1 START Initial settings Clock selection TPnCTL0 T...

Page 306: ...ment Remarks 1 D00 D01 D02 Values captured to TPnCCR0 register 0000H to FFFFH 2 TIPn0 Set to detection of rising edge TPnIS1 TPnIS0 01B 3 TIPn1 Set to no edge detection TPnIS3 TPnIS2 00B 4 n 0 to 7 D00 D00 D01 D01 D02 D02 FFFFH 0000H 16 bit counter TIPn0 TPnCCR0 INTTPnCCR0 INTTPnOV TPnOVF FFFFH TPnCE 1 cleared by writing 0 from CPU ...

Page 307: ...chart of Alternating Pulse Width and Pulse Space Measurement Note External pulse input is possible for both TIPn0 and TIPn1 but only one should be selected for the alternating pulse width and pulse space measurement Specify both rising and the falling edges for edge detection Specify the edge of the external input pulse that is not used as no edge detection Remark n 0 to 7 m 0 1 START Initial sett...

Page 308: ...arks 1 D00 D01 D02 D03 D04 Values captured to TPnCCR0 register 0000H to FFFFH 2 TIPn0 Set to detection of both rising and falling edges TPnIS1 TPnIS0 11B 3 TIPn1 Set to no edge detection TPnIS3 TPnIS2 00B 4 n 0 to 7 D00 D00 D01 D01 D02 D02 FFFFH 0000H 16 bit counter TIPn0 TPnCCR0 INTTPnCCR0 INTTPnOV TPnOVF FFFFH TPnCE 1 D03 D03 D04 D04 cleared by writing 0 from CPU ...

Page 309: ...isters TPnCCR0 TPnCCR1 and the timer is cleared and restarts counting Figure 9 37 Flowchart of Simultaneous Pulse Width and Pulse Space Measurement Note External pulse input must be input to both TIPn0 and TIPn1 or to TIPn0 only if the internal connection between both inputs is selected Specify rising edge for edge detection of first input and falling edge for the second input or vice versa Remark...

Page 310: ...put on TIPn0 pin In case of internal connection the signal has to be input on TIPn0 pin Remarks 1 D00 D01 D02 Values captured to TPnCCR0 register 0000H to FFFFH 2 D10 D11 Values captured to TPnCCR1 register 0000H to FFFFH 3 TIPn0 Set detection to rising edge TPnIS1 TPnIS0 01B 4 TIPn1 Set detection to falling edge TPnIS3 TPnIS2 10B 5 n 0 to 7 D00 D10 D01 FFFFH 16 bit counter TIPn0 TIPn1 Note FFFFH ...

Page 311: ...e 1 Clear the synchronous mode selection bit TPmSYE of the master counter TMPm to 0 2 Disable the count operation of the master counter TMPm TPmCE 0 3 Enable the synchronous operation for each of the incorporated slave counters TMPs TPsSYE 1 4 Enable the operation of the master counter TMPm TPmCE 1 Master and incorporated slave counters of that group start and clock synchronously When the master c...

Page 312: ...312 Chapter 9 16 Bit Timer Event Counter P User s Manual U16580EE3V1UD00 MEMO ...

Page 313: ...unction ESO High impedance output of pins TORn0 to TORn7 possible during ESOn input Compare value setting Reload batch rewrite anytime rewrite mode selectable Note Reload mode Reload enabled by writing to TRnCCR1 register last multiple registers simultaneity maintained Peak valley peak and valley reload transfer possible at reload timing Note Provision of reload request flag TRnRSF DMA transferabl...

Page 314: ...compare registers 0 to 3 TRnCCR0 TRnCCR3 Timer Rn compare registers 4 5 TRnCCR4 TRnCCR5 TRnCCR0 to TRnCCR5 buffer registers TRnDTC0 TRnDTC1 buffer registers Timer input pins 3 TIR10 to TIR13 TTRGR1 TEVTR1 ESOn Note Timer output pins 8 TORn0 to TORn7 Note Timer input signal Timer output signal TRnADTRG0 TRnADTRG1 Control registers Timer Rn control registers 0 1 TRnCTL0 TRnCTL1 Timer Rn I O control ...

Page 315: ...buffer CCR5 buffer TRnSBC TRnCNT TRnCUF TRnCUF TRnADTRG0 TORn0 TIR10 TTRGR1 TEVTR1 TIR11 TIR12 TIR13 TORn1 TORn2 TORn3 TORn4 TORn5 TORn6 TORn7 TRnADTRG1 INTTRnO V INTTRnOD INTTRnCD INTTRnCC0 INTTRnCC1 INTTRnCC2 INTTRnCC3 INTTRnCC4 INTTRnCC5 load TRnSUF TRnSUF Counter control Counter control Edge detector 2 1024 256 64 32 16 8 4 Output control ADTRG control Internal bus Internal bus 16 bit TMRn cou...

Page 316: ...0 a Use as compare register When TRnCE 1 the TRnCCR0 register write access method is as follows Remarks 1 For details about the compare register rewrite operation refer to 10 4 2 Compare register rewrite operation 2 n 0 1 Caution To set the carrier frequency in the high accuracy T PWM mode set the TRnCCR0 reg ister as follows Number of count clocks of carrier frequency TRnDTC0 register value TRnDT...

Page 317: ...n in 16 bit units RESET input clears this register to 0000H Remarks 1 In the high accuracy T PWM mode when bit 0 is set to 1 the additional pulse control function is engaged For details about the additional pulse control function refer to 10 10 9 10 10 9 2 n 0 1 Figure 10 3 TMRn Capture Compare Register 1 TRnCCR1 a Use as compare register When TRnCE 1 the TRnCCR1 register write access method is as...

Page 318: ...to 1 the additional pulse control function is engaged For details about the additional pulse control function refer to 10 10 9 10 10 9 2 n 0 1 Figure 10 4 TMRn Capture Compare Register 2 TRnCCR2 a Use as compare register When TRnCE 1 the TRnCCR2 register write access method is as follows Remarks 1 For details about the compare register rewrite operation refer to 10 4 2 Compare register rewrite ope...

Page 319: ... to 1 the additional pulse control function is engaged For details about the additional pulse control function refer to 10 10 9 10 10 9 2 n 0 1 Figure 10 5 TMRn Capture Compare Register 3 TRnCCR3 a Use as compare register When TRnCE 1 the TRnCCR3 register write access method is as follows Remarks 1 For details about the compare register rewrite operation refer to 10 4 2 Compare register rewrite op...

Page 320: ... mode bit 0 of the TRnCCR4 register is ignored 2 n 0 1 Figure 10 6 TMRn Compare Register 4 TRnCCR4 When TRnCE 1 the TRnCCR4 register write access method is as follows Remarks 1 For details about the compare register rewrite operation refer to 10 4 2 Compare register rewrite operation 2 n 0 1 After reset 0000H R W Address TR0CCR4 FFFFF592H TR1CCR4 FFFFF5D2H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRn...

Page 321: ...the TRnCCR5 register is ignored 2 n 0 1 Figure 10 7 TMRn Compare Register 5 TRnCCR5 When TRnCE 1 the TRnCCR5 register write access method is as follows Remarks 1 For details about the compare register rewrite operation refer to 10 4 2 Compare register rewrite operation 2 n 0 1 After reset 0000H R W Address TR0CCR5 FFFFF590H TR1CCR5 FFFFF5D0H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRnCCR5 Timer Rn O...

Page 322: ...ode bit 0 is read as 0 Remark n 0 1 8 TMRn sub counter read register TRnSBC The TRnSBC register can read the value of the 16 bit counter This register can only be read in 16 bit units RESET input or setting TRnCE 0 clears this register to 0000H Remarks 1 In the high accuracy T PWM mode this register can be used only in the PWM mode with dead time 2 n 0 1 Figure 10 9 TMRn Sub Counter Read Register ...

Page 323: ...er 0 TRnDTC0 10 TMRn dead time setting register 1 TRnDTC1 The TRnDTC1 register is a 10 bit register that specifies the dead time value This register can be read and written in 16 bit units Reset input clears this register to 0000H The dead time counter operates in the high accuracy T PWM mode and the PWM mode with dead time In all other modes be sure to set the TRnDTC1 register to 0000H Cautions 1...

Page 324: ...ng clock operation disabled Reset timer Rn asynchronously 1 Internal operating clock operation enabled When bit TRnCE is set to 0 the internal operation clock of timer Rn stops fixed to low level and timer Rn is set asynchronously When bit TRnCE is set to 1 the internal operation of timer Rn is enabled from when bit TRnCE was set to 1 and count up is performed The time until count up is as listed ...

Page 325: ... fXX 8 0 1 1 fXX 16 1 0 0 fXX 32 1 0 1 fXX 64 1 1 0 fXX 256 1 1 1 fXX 1024 Caution Set bits TRnCKS2 to TRnCKS0 when TRnCE 0 When bit TRnCE is set from 0 to 1 bits TRnCKS2 to TRnCKS0 can be simultaneously set Remark fXX System clock Table 10 2 TMRn Count Clock and Count Delay Count Clocks TTnCKS2 TTnCKS1 TTnCKS0 Count Delay Minimum Maximum fXX 2 0 0 0 3 base clocks 4 base clocks fXX 4 0 0 1 fXX 8 0...

Page 326: ...ress TR0CTL1 FFFFF581H TR1CTL1 FFFFF5C1H 7 6 5 4 3 2 1 0 TRnCTL1 0 TRnEST TRnEEE 0 TRnMD3 TRnMD2 TRnMD1 TRnMD0 n 0 1 TRnEST Software Trigger Control 0 No operation 1 Enables software trigger control In one shot pulse mode One shot pulse software trigger In external trigger pulse output mode Pulse output software trigger The TRnEST bit functions as a software trigger in the one shot pulse mode and ...

Page 327: ...vent count mode Note 1 0 0 1 0 External trigger pulse output mode Note 2 0 0 1 1 One shot pulse mode 0 1 0 0 PWM mode 0 1 0 1 Free running mode 0 1 1 0 Pulse width measurement mode Note 1 0 1 1 1 Triangular wave PWM mode 1 0 0 0 High accuracy T PWM mode 1 0 0 1 PWM mode with dead time Other than above Setting prohibited Notes 1 Setting prohibited for TMR0 2 For TMR0 an output pulse can be triggere...

Page 328: ...e may occur on the output pin set the TRnIOC0 register when TRnCE 0 When TRnCE 1 the TRnIOC0 register can be write accessed using the same value Figure 10 14 TMRn I O Control Register 0 TRnIOC0 Remark n 0 1 m 0 to 3 After reset 00H R W Address TR0IOC0 FFFFF582H TR1IOC0 FFFFF5C2H 7 6 5 4 3 2 1 0 TRnIOC0 TRnOL3 TRnOE3 TRnOL2 TRnOE2 TRnOL1 TRnOE1 TRnOL0 TRnOE0 n 0 1 TRnOLm Timer Output Level Setting ...

Page 329: ... R W Address FFFFF5C3H 7 6 5 4 3 2 1 0 TR1IOC1 TR1IS7 TR1IS6 TR1IS5 TR1IS4 TR1IS3 TR1IS2 TR1IS1 TR1IS0 TR1IS7 TR1IS6 Capture Input TIR13 Valid Edge Setting 0 0 No edge detection capture operation invalid 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection TR1IS5 TR1IS4 Capture Input TIR12 Valid Edge Setting 0 0 No edge detection capture operation invalid...

Page 330: ...2 0 0 0 0 TR1EES1 TR1EES0 TR1ETS1 TR1ETS0 TR1EES1 TR1EES0 External Event Counter Input TEVTR1 Valid Edge Setting 0 0 No edge detection capture operation invalid 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection Remark Bits TR1EES1 and TR1EES0 are valid only when TR1CTL1 register bit TR1EEE 1 or when the external event count mode TR1CTL1 register bits T...

Page 331: ...may occur on the output pin set the TRnIOC3 register when TRnCE 0 When TRnCE 1 the TRnIOC0 register can be write accessed using the same value Figure 10 17 TMRn I O Control Register 3 TRnIOC3 Remark n 0 1 m 4 to 7 After reset 00H R W Address TR0IOC3 FFFFF585H TR1IOC3 FFFFF5C5H 7 6 5 4 3 2 1 0 TRnIOC3 TRnOL7 TRnOE7 TRnOL6 TRnOE6 TRnOL5 TRnOE5 TRnOL4 TRnOE4 n 0 1 TRnOLm Timer Output Level Setting of...

Page 332: ...s TORn5 and TORn6 Remark If simultaneous active state is detected when TRnTBA2 1 the TRnTBF flag is set 1 and an error interrupt INTTRnER is output TRnTBA1 Timer Outputs TORn3 TORn4 True Bar Active Detection Control 0 No detection of simultaneous active state of pins TORn3 and TORn4 1 Detection of simultaneous active state of pins TORn3 and TORn4 Remark If simultaneous active state is detected whe...

Page 333: ... 0 TR1CMS TR1CUF TR1OVF TR1CCS3 TR1CCR3 register capture compare selection 0 Select compare register 1 Select capture register Remark Bit TR1CCS3 is only valid in the free running mode In all other modes this bit is invalid TR1CCS2 TR1CCR2 register capture compare selection 0 Select compare register 1 Select capture register Remark Bit TR1CCS2 is only valid in the free running mode In all other mo...

Page 334: ...TRnCUF Timer R Counter Up Down Detection Flag 0 The timer counter is in up count state 1 The timer counter is in down count state Remark The TRnCUF bit is valid only in the high accuracy T PWM mode and triangular wave PWM mode In all other modes it is invalid TRnCUF 0 TRnOVF Timer R Overflow Detection Flag 0 No overflow occurrence after bit was cleared 1 Overflow occurrence Remarks 1 The TRnOVF bi...

Page 335: ...EH TR1OPT1 FFFFF5CEH 7 6 5 4 3 2 1 0 TRnOPT1 TRnICE TRnIOE TRnRDE TRnID4 TRnID3 TRnID2 TRnID1 TRnID0 n 0 1 TRnICE Peak Interrupts INTTRnCD Control 0 Disable peak interrupt INTTRnCD output in the counter s peak timing Interrupt thinning out is not performed Reload operation is disabled in the counter s peak timing 1 Enable peak interrupt INTTRnCD in the counter s peak timing Interrupt thinning out ...

Page 336: ...alid only in the PWM mode high accuracy T PWM mode triangular wave PWM output mode and PWM mode with dead time TRnID4 TRnID3 TRnID2 TRnID1 TRnID0 Interrupt Thinning Out Rate 0 0 0 0 0 No thinning out 0 0 0 0 1 1 2 0 0 0 1 0 1 3 0 0 0 1 1 1 4 1 1 1 0 1 1 30 1 1 1 1 0 1 31 1 1 1 1 1 1 32 Caution If when TRnCE 1 the TRnOPT1 register is write accessed including same value to bits TRnID4 to TRnID0 the ...

Page 337: ...iangular wave PWM mode when setting TRnAT02 1 set TRnOE4 0 Figure 10 21 TMRn Option Register 2 TRnOPT2 1 2 Remark n 0 1 After reset 00H R W Address TR0OPT2 FFFFF588H TR1OPT2 FFFFF5C8H 7 6 5 4 3 2 1 0 TRnOPT2 0 0 TRnAT05 TRnAT04 TRnAT03 TRnAT02 TRnAT01 TRnAT00 n 0 1 TRnAT05 TRnAT04 A D Converter Trigger Signal TRnADTRG0 Generation with Occurrence of Compare Match Interrupt INTTRnCCR5 0 0 No trigger...

Page 338: ...nverter Trigger Signal TRnADTRG0 Generation with Occurrence of Peak Interrupt INTTRnCD 0 No trigger signal is generated when peak interrupt INTTRnCD occurs 1 Trigger signal is generated when peak interrupt INTTRnCD occurs after thinning out Caution Bit TRnAT01 can be set to 1 only in the PWM mode high accuracy T PWM mode and PWM mode with dead time In all other modes be sure to set this bit to 0 R...

Page 339: ...ngular wave PWM mode when setting TRnAT12 1 set TRnOE4 0 Figure 10 22 TMRn Option Register 3 TRnOPT3 1 2 Remark n 0 1 After reset 00H R W Address TR0OPT3 FFFFF589H TR1OPT3 FFFFF5C9H 7 6 5 4 3 2 1 0 TRnOPT3 0 0 TRnAT15 TRnAT14 TRnAT13 TRnAT12 TRnAT11 TRnAT10 n 0 1 TRnAT15 TRnAT14 A D Converter Trigger Signal TRnADTRG1 Generation with Occurrence of Compare Match Interrupt INTTRnCCR5 0 0 No trigger s...

Page 340: ...D Converter Trigger Signal TRnADTRG1 Generation with Occurrence of Peak Interrupt INTTRnCD 0 No trigger signal is generated when peak interrupt INTTRnCD occurs 1 Trigger signal is generated when peak interrupt INTTRnCD occurs after thinning out Caution Bit TRnAT11 can be set to 1 only in the PWM mode high accuracy T PWM mode and PWM mode with dead time In all other modes be sure to set this bit to...

Page 341: ... Remarks 1 The TRnTBF flag is set 1 upon detection that any of the normal phases TORn1 TORn3 TORn5 and inverted phases TORn2 TORn4 TORn6 are simultaneously active and an error interrupt INTTRnER is output at such time 2 This flag can be cleared by writing 0 to it TRnSUF Timer R Sub Counter Up Down Detection Flag 0 Sub counter is counting up 1 Sub counter is counting down The TRnSUF flag detects su...

Page 342: ... Remark n 0 1 After reset 00H R W Address TR0OPT7 FFFFF58DH TR1OPT7 FFFFF5CDH 7 6 5 4 3 2 1 0 TRnOPT7 0 0 0 0 0 0 0 TRnTOS n 0 1 TRnTOS Timer Output TORn0 Switching Control 0 Output counter s TRnCNT up down count flag to TORn0 pin 1 Output sub counter s TRnSBC up down count flag to TORn0 pin When TRnTOS 0 the status of bit TRnCUF of the TRnOPT0 register is output to pin TORn0 When TRnTOS 1 the sta...

Page 343: ...er and the compare register Counting immediately following the start of count operation and counting from FFFFH to 0000H in the case of overflow are not detected as clear operations 3 Overflow operation 16 bit counter overflow occurs when the value of the 16 bit counter changes from FFFFH to 0000H When overflow occurs bit TRnOVF of the TRnOPT0 register is set to 1 and an interrupt INTTRnOV is outp...

Page 344: ...TRnCC3 Functions as TRnCCRn3 buffer register match interrupt INTTRnCC4 Functions as TRnCCRn4 buffer register match interrupt INTTRnCC5 Functions as TRnCCRn5 buffer register match interrupt INTTRnCD Functions as a peak interrupt at the timing when the counter switches from down count to up count INTTRnOD Functions as a valley interrupt at the timing when the counter switches from up count to down c...

Page 345: ...s written to the register is updated to the value written during anytime write access Reload mode batch rewrite When the TRnCCR1 register is written to all the registers are updated at the next reload timing reload Reload does not occur even if a register other than the TRnCCR1 register is written to A reload request flag TRnRSF is provided The compare register can be rewritten using DMA transfer ...

Page 346: ...interrupt 2 Set with TRnOPT0 register bit TRnCMS 0 TRnOPT1 register bit TRnRDE 0 Mode Rewrite Timing Interval mode Anytime rewrite External event count mode Anytime rewrite External trigger pulse output mode Reload One shot pulse mode Anytime rewrite PWM mode Reload Free running mode Anytime rewrite Pulse width measurement mode Reload Triangular wave PWM mode Reload Note 1 High accuracy T PWM mode...

Page 347: ...ce only the TRnCCR1 register has a 2 stage configuration the actual transfer timing is after the lapse of 5 clocks fTMRn Figure 10 25 Anytime Rewrite Timing Remarks 1 D01 D02 TRnCCR0 register setting value 0000H to FFFFH D11 D12 TRnCCR1 register setting value 0000H to FFFFH D21 TRnCCR2 register setting value 0000H to FFFFH D31 TRnCCR3 register setting value 0000H to FFFFH 2 Timing chart using inte...

Page 348: ...ferred to the TRnCCR0 buffer register at the next peak or at the valley timing Since TRnCMS 1 anytime rewrite the settings of bits TRnIOE TRnICE TRnRDE and TRnID4 to TRnID0 have no influence b Cautions related to rewriting of TRnCCR1 to TRnCCR3 registers Rewrite in 1 interval rewrite before match occurrence In the case of rewrite before a match between the TRnCCR1 to TRnCCR3 registers and the coun...

Page 349: ...tch occurrence In the case of rewrite after a match between the TRnCCR1 to TRnCCR3 registers and the counter occurs further match occurrences are ignored so the rewrite value is not reflected Counter TRnCCR1 i TRnCCR1 buffer TORn1 r r i Forced rise TORn2 i i r r Counter TRnCCR1 i k TRnCCR1 buffer INTTRnCC1 k k TORn1 k TORn2 Matches due to rewrite after match occurrence are ignored and the timer ou...

Page 350: ... rewrite and the rewrite value is instantly reflected If a value larger than the counter value is written before match occurrence no match occurs so the following output wave results If no match occurs the timer output remains unchanged However even if a match occurs the timer output is forcibly changed to normal phase inactive level at valleys Counter TRnCCR1 i k TRnCCR1 buffer TORn1 k k TORn2 i ...

Page 351: ...rewriting TRnOPT1 Since the internal interrupt thinning out counter is cleared when the TRnOPT1 register is written to the interrupt output interval may temporarily become longer Counter TRnCCR1 i k TRnCCR1 buffer INTTRnCC1 k k i TORn1 Matches due to rewrite after match occurrence are ignored and the timer output remains unchanged The INTTRnCC1 signal becomes valid from the next match after up dow...

Page 352: ...10 26 Basic Operation Flow during Batch Rewrite Caution Write access to the TRnCCR1 register includes also the reload enable operation Therefore rewrite the TRnCCR1 register after rewriting the other TRnCCR registers Remarks 1 This sample flow chart is for the PWM mode 2 n 0 1 START Initial settings Timer operation enable TRnCE 1 Transfer of values of TRnCCR0 to TRnCCR3 to buffers TRnCCR0 to TRnCC...

Page 353: ... TRnCCR0 buffer TRnCCR1 TRnCCR1 buffer TRnCCR2 TRnCCR2 buffer TRnCCR3 TRnCCR3 buffer TRnCCR4 TRnCCR4 buffer TRnCCR5 TRnCCR5 buffer TRnOPT1 TRnOPT1 buffer Reload rewrite timing Counter INTTRnOD INTTRnCD0 Reload upon TRnCCR1 write Batch update at reload timing TRnRSF Setting of reload hold flag Flag clearing following reload ...

Page 354: ...ing 2 2 Counter Reload upon TRnCCR1 write Batch update at reload timing Setting of reload hold flag Flag clearing following reload TRnCCR0 TSnCCR0 buffer TRnCCR1 TSnCCR1 buffer TRnCCR2 TSnCCR2 buffer TRnCCR3 TSnCCR3 buffer TRnCCR4 TSnCCR4 buffer TRnCCR5 TSnCCR5 buffer TRnOPT1 TSnOPT1 buffer INTTRnCD0 TRnRSF ...

Page 355: ... TRnICE 1 TRnIOE 1 settings Rewrite in 1 interval rewrite during up count Since the next reload timing becomes the peak point the cycle on the down count side changes and an asymmetrical triangular waveform is output Also since the cycle changes reset the duty value as necessary Remark d1 TRnDTC1 setting value Counter 1 2 1 2 Counter TRnCCR0 i k TRnCCR0 buffer INTTRnCD k k TORn1 TRnCCR1 TRnCCR1 bu...

Page 356: ...ount Since the next reload timing becomes the valley point the cycle value changes from the next cycle and the asymmetrical triangular waveform output is held Since the cycle changes be sure to set again the duty value as required Remark d1 TRnDTC1 setting value Counter TRnCCR0 i TRnCCR0 buffer INTTRnCD k TORn1 TRnCCR1 TRnCCR1 buffer k INTTRnOD m d1 r d1 Reloadable timing r d1 value loaded to coun...

Page 357: ...rite in 1 interval rewrite during up count Since reload is performed at the peak interrupt timing an asymmetric triangular waveform is output Rewrite in 2 interval rewrite during down count Since reload is performed at the valley interrupt timing an asymmetric triangular waveform is output Counter i INTTRnCC1 TORn1 TRnCCR1 TRnCCR1 buffer k r r Reloadable timing TORn2 1 2 1 2 i i k k r r ...

Page 358: ...ve upon TRnCCR1 match Inactive upon TRnCCR0 match Active upon TRnCCR2 match Inactive upon TRnCCR0 match Active upon TRnCCR3 match Inactive upon TRnCCR0 match PWM mode Toggle output upon TRnCCR0 compare match PWM output upon TRnCCR1 compare match PWM output upon TRnCCR2 compare match PWM output upon TRnCCR3 compare match Free running mode Toggle output upon TRnCCR0 compare match Toggle output upon ...

Page 359: ...gh upon TRnCCR5 match Inactive upon TRnCCR0 match PWM mode PWM output upon TRnCCR4 compare match PWM output upon TRnCCR5 compare match Pulse output upon A D conversion trigger Note Free running mode Toggle output upon TRnCCR4 compare match Toggle output upon TRnCCR5 compare match Pulse width measurement mode Triangular wave PWM mode PWM output upon TRnCCR4 compare match PWM output upon TRnCCR5 com...

Page 360: ... 1 its set 1 status is maintained If the TRnADTRG1 trigger occurs while pin TORn7 is reset 0 the 0 status is maintained If the TRnADTRG0 and TRnADTRG1 signal triggers occur simultaneously pin TORn7 is reset to 0 Figure 10 28 TORn7 Pin Output Timing 1 Remark Case 1 When TRnCCR4 TRnCCR5 TRnOPT2 04H TRnOPT3 10H Case 2 When TRnCCR4 TRnCCR5 TRnOPT2 04H TRnOPT3 20H Case 3 When TRnCCR4 TRnCCR5 TRnOPT2 08...

Page 361: ...al trigger pulse output mode TRnCCR0 compare match interrupt TRnCCR1 compare match interrupt TRnCCR2 compare match interrupt TRnCCR3 compare match interrupt One shot pulse mode TRnCCR0 compare match interrupt TRnCCR1 compare match interrupt TRnCCR2 compare match interrupt TRnCCR3 compare match interrupt PWM mode TRnCCR0 compare match interrupt TRnCCR1 compare match interrupt TRnCCR2 compare match ...

Page 362: ... TRnCCR4 compare match interrupt TRnCCR5 compare match interrupt External trigger pulse output mode TRnCCR4 compare match interrupt TRnCCR5 compare match interrupt One shot pulse mode TRnCCR4 compare match interrupt TRnCCR5 compare match interrupt PWM mode TRnCCR4 compare match interrupt TRnCCR5 compare match interrupt Error interrupt Free running mode TRnCCR4 compare match interrupt TRnCCR5 compa...

Page 363: ...mode PWM mode Select from interrupts INTTRnCD INTTRnCC4 INTTRnCC5 Select from interrupts INTTRnCD INTTRnCC4 INTTRnCC5 Peak interrupt at same timing as INTTRnCC0 interrupt Free running mode Pulse width measurement mode Triangular wave PWM mode Select from interrupts INTTRnCD INTTRnCC4 INTTRnCC5 Select from interrupts INTTRnCD INTTRnCC4 INTTRnCC5 Valley interrupt at counter valley upon switching fro...

Page 364: ... time If the counter is a triangular wave operation mode triangular wave PWM mode high accuracy PWM mode a peak interrupt is output when the counter switches from up count to down count If the counter is in a saw tooth wave operation mode PWM mode PWM mode with dead time a peak interrupt occurs upon a match between the counter and the TRnCCR0 register same timing as INTTRnCC0 interrupt Valley inte...

Page 365: ...ser s Manual U16580EE3V1UD00 Figure 10 29 Interrupt Signal Output Example 2 2 p FFFFH 0H TRnCCR0 TRnCCR1 TRnCCR2 TRnCCR3 p i j k p Counter INTTRnCD0 peak interrupt INTTRnOD valley interrupt INTTRnCC1 INTTRnCC2 INTTRnCC3 TRnCCR3 l INTTRnCC0 INTTRnCC4 ...

Page 366: ...ccuracy T PWM mode if set in the range of 0000H TRnCCRm TRnDTC0 TRnCCR0 TRnDTC1 TRnCCRm TRnCCR0 no interrupt occurs upon a match between the compare value and the counter Remark m 1 to 3 Restrictions related to TRnCCR4 and TRnCCR5 registers In the high accuracy T PWM mode if set in the range of 0000H TRnCCR4 TRnCCR5 TRnDTC0 TRnCCR0 TRnDTC1 TRnCCR4 TRnCCR5 TRnCCR0 no compare match interrupt is outp...

Page 367: ... conditions no compare interrupt is output Restrictions related to TRnCCRm In the PWM mode with dead time if setting is performed in the following range no match between the compare value and counter occurs and no compare match interrupt is output When TRnCCR0 TRnCCRm TRnCCR0 TRnDTC0 TRnCCR4 TRnCCR5 registers are used as trigger causes for A D triggers perform settings with TRnCCR4 TRnCCR5 TRnCCR0...

Page 368: ... is fixed to 0 in all other modes For both TRnCUF and TRnSUF 0 indicates the up count status and 1 indicates the down count status Figure 10 30 Up Count Flags Timings 1 2 In the triangular wave PWM mode the values of TRnCUF are as follows 0 counter TRnCCR0 1 0 up count TRnCCR0 1 counter 0 1 down count In the high accuracy T PWM mode the values of TRnCUF TRnSUF are as follows TRnCUF TRnDTC0 counter...

Page 369: ...PWM mode triangular wave PWM mode high accuracy T PWM mode and PWM mode with dead time Figure 10 31 Normal Phase Inverted Phase Simultaneous Active Detection Flag Timing TRnCUF TORn0 TRnSUF TORn0 TSnCCR0 0000H Counter Sub counter TRnDTC0 TRnTOS 1 sub counter up down status output to TORn0 TRnTOS 0 sub counter up down status output to TORn0 TRnCCR0 TRnDTC1 Counter TORn1 TORn2 TRnTBA0 1 TRnTBF Set a...

Page 370: ...g is cleared to 0 The TRnRSF flag is valid in the following operation modes External trigger pulse output mode PWM mode Triangular wave PWM mode High accuracy T PWM mode TRnCMS 0 PWM mode with dead time Caution The TRnRSF flag is set to 1 following the lapse of 4 base clocks after TRnCCR1 reg ister write completion Figure 10 32 Reload Hold Flag Timings x y x y TRnCCR1 TRnCCR1 buffers TRnRSF Reload...

Page 371: ...s interrupt output following thinning out If thinning out No is specified reload is executed at the reload timing after write access to the TRnCCR1 register The reload anytime rewrite method can be specified with TRnOPT0 register bit TRnCMS When TRnCMS 0 the register value is updated in synchronization with reload but when TRnCMS 1 the register value is updated immediately after write access Cauti...

Page 372: ...ng Out Operations 1 2 a when TRnICE 1 TRnIOE 1 peak valley interrupt output TRnID4 0 00H no th inning out TRnID4 0 01H mask 1 TRnID4 0 02H mask 2 TRnID4 0 03H mask 3 TRnID4 0 04H mask 4 TRnID4 0 05H mask 5 TRnID4 0 06H mask 6 Counter INTTRnCD INTTRnOD INTTRnCD INTTRnOD INTTRnCD INTTRnOD INTTRnCD INTTRnOD INTTRnCD INTTRnOD INTTRnCD INTTRnOD INTTRnCD INTTRnOD ...

Page 373: ...nly output Counter TRnID4 0 00H no th inning out INTTRnCD INTTRnOD TRnID4 0 01H mask 1 INTTRnCD INTTRnOD TRnID4 0 02H mask 2 INTTRnCD INTTRnOD TRnID4 0 03H mask 3 INTTRnCD INTTRnOD TRnID4 0 04H mask 4 INTTRnCD INTTRnOD Counter TRnID4 0 00H no thinning out INTTRnCD INTTRnOD TRnID4 0 01H mask 1 INTTRnCD INTTRnOD TRnID4 0 02H mask 2 INTTRnCD INTTRnOD TRnID4 0 03H mask 3 INTTRnCD INTTRnOD TRnID4 0 04H...

Page 374: ... TRnCMS 0 TRnRDE 1 Reload Thinning Out Control Recommended Settings b when TRnCMS 0 TRnRDE 0 No Reload Control Counter INTTRnCD INTTRnOD TRnIDS4 to 0 TRnID4 to 0 Reload Clear Interrupt thinning out counter Reload is executed at the thinned out interrupt output timing All other reload timings are ignored 00 01 02 02 04 00 01 02 02 04 00 01 02 03 04 00 01 02 03 04 Counter INTTRnCD INTTRnOD TRnIDS4 t...

Page 375: ... used to specify reload thinning out Yes No If thinning out Yes is specified reload is executed at the same timing as interrupt output following thinning out If thinning out No is specified reload is executed at the reload timing after write access to the TRnCCR1 register Caution When write access is performed to the TRnOPT1 register the internal thinning out counter is cleared when the register v...

Page 376: ...n triggers peak inter rupts and valley interrupts in each mode Figure 10 35 A D Conversion Trigger Output Controller The above figure shows the A D conversion trigger controller As shown in this figure it is possible to select and perform OR output of compare match interrupts INTTRnCC5 INTTRnCC4 and peak interrupts INTTRnCD valley interrupts INTTRnOD interrupt signals sub counter peak timing and s...

Page 377: ...onversion trigger outputtable upon compare match interrupt INTTRnCC4 during counter down count TRnOPT2 register TRnAT04 1 A D conversion trigger outputtable upon compare match interrupt INTTRnCC5 during counter up count TRnOPT2 register TRnAT05 1 A D conversion trigger outputtable upon compare match interrupt INTTRnCC5 during counter down count The A D conversion start trigger signals selected wit...

Page 378: ... When TRnAT05 to 00 000010 Output INTTRnCD When TRnAT05 to 00 000100 Output INTTRnCC4 during up count When TRnAT05 to 00 001000 Output INTTRnCC4 during down count When TRnAT05 to 00 010000 Output INTTRnCC5 during up count When TRnAT05 to 00 100000 Output INTTRnCC5 during down count When TRnAT05 to 00 000011 Setting at which A D conversion start trigger is output for both peaks and valleys When TRn...

Page 379: ...t 2 Cautions related to A D conversion triggers In the PWM mode and PWM mode with dead time no valley interrupt INTTRnOD is output Only peak interrupts INTTRnCD are valid Counter INTTRnCD INTTRnOD When TRnAT05 00 000011 Both INTTRnCD and INTTRnOD are selected but peak not output due to interrupt thinning out specification TRnADTRG0 Counter INTTRnCD INTTRnOD When TRnAT05 00 000101 INTTRnCD is thinn...

Page 380: ...ing bits TRnTBA2 to TRnTBA0 of the TRnIOC4 register The possibility of normal phase inverted phase simultaneous active error detection in each mode is indicated below Remark Error detection possible Error detection not possible Figure 10 37 Error Interrupt INTTRnER and Error Signal TRnER Output Controller Output of the error signal TRnER due to normal phase inverted phase simultaneous active error...

Page 381: ...are set so that pins TORn3 and TORn4 simultaneously output H Figure 10 38 Error Interrupt and Error Signal Output Controller in PWM mode If the output active level is switched by manipulating TRnIOC0 register bits TRnOL1 and TRnOL2 the following results TORn1 TORn2 TORn3 TORn4 TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR0 INTTRnER TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR2 TRnCCR3 TRnCCR1 TRnCCR4 TRnCCR1 T...

Page 382: ...TRnER is output when the TRnCCR0 and TRnCCR1 registers are set so that pins TORn1 and TORn2 simultaneously output H Similarly an error interrupt INTTRnER is output when the TRnCCR3 and TRnCCR4 registers are set so that pins TORn3 and TORn4 simultaneously output H Figure 10 39 Error Interrupt and Error Signal Output Controller in triangular wave PWM mode TORn1 TORn2 TORn3 TORn4 INTTRnER TRnCCR2 TRn...

Page 383: ...error occurs this is likely due to an internal circuit fault Figure 10 40 Error Interrupt and Error Signal Output Controller in High Accuracy T PWM Mode PWM Mode with Dead Time TORn1 TORn2 INTTRnER TRnTBF L Counter A glitch may occur during normal phase inverted phase switching The detection flag TRnTBF is not set TORn1 TORn2 INTTRnER TRnTBF L Counter A glitch may occur during normal phase inverte...

Page 384: ...values transferred to the TRnCCR1 to TRnCCR5 buffer registers and compare match interrupts INTTRnCC1 to INTTRnCCR5 are output The TRnCCR0 to TRnCCR5 registers can be rewritten using the anytime write method regardless of the value of bit TRnCE Pins TORn0 to TORn7 are toggle output controlled when bits TRnOE0 to TRnOE7 are set to 1 Figure 10 41 Basic Operation Flow in Interval Timer Mode Note In th...

Page 385: ...upts Register Rewrite Method Rewrite during Operation Function TRnCCR0 Reload Possible Compare value TRnCCR1 to TRnCCR3 Reload Possible Compare value TRnCCR4 TRnCCR5 Reload Possible Compare value Pin Function TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORnm Toggle output upon TRnCCRm register compare match m 0 to 5 TORn6 TORn7 Interrupt Function INTTRnCCm TRnCCRm register compare match m 0 to 5 INT...

Page 386: ...TORn1 are not output TRnOE0 1 0 TRnOL0 0 TRnOL1 1 Remarks 1 D1 D2 Setting values of TRnCCR0 register 0000H to FFFFH D3 Setting values of TRnCCR1 register 0000H to FFFFH 2 Interval time Dm 1 count clock cycle 3 m 1 to 3 n 0 1 Counter D1 D 2 INTTRnCC0 D1 D2 D1 FFFFH TRnCCR1 D3 D3 D3 INTTRnCC1 TRnCCR0 D3 TRnCE A Interval time D1 1 count clock A A B TORn0 TORn1 Low High A Interval time D2 1 count cloc...

Page 387: ...ORn1 output performed TRnOE0 1 1 TRnOL0 0 TRnOL1 1 Remarks 1 D1 Setting value of TRnCCR0 register 0000H to FFFFH D2 Setting value of TRnCCR1 register 0000H to FFFFH 2 Interval time Dm 1 count clock cycle 3 TORn0 TORn1 toggle time Dm 1 count clock cycle 4 m 1 2 n 0 1 Counter D1 INTTRnCC0 D1 D2 FFFFH TRnCCR1 INTTRnCC1 TRnCCR0 D2 TRnCE D1 D2 D1 D2 Interval time Interval time Interval time TORn0 TORn1...

Page 388: ...nOE1 to TRnOE7 are set to 1 When a compare register TRnCCR0 to TRnCCR5 is not used it is recommended to set it contents to FFFFH External event count operation flow 1 TRnCTL1 register bits TRnMD3 to TRnMD0 0001B mode setting Edge detection set with TRnIOC2 register bits TRnEES1 and TRnEES0 TRnEES1 TRnEES0 setting other than 00B 2 TRnCTL0 register bit TRnCE 1 count enable 3 TEVTRn pin input edge de...

Page 389: ...rite during Operation Function TRnCCR0 Anytime rewrite Possible Compare value TRnCCR1 to TRnCCR3 Anytime rewrite Possible Compare value TRnCCR4 TRnCCR5 Anytime rewrite Possible Compare value Pin Function TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORnm Toggle output upon TRnCCRm register compare match m 0 to 5 TORn6 TORn7 Interrupt Function INTTRnCCm TRnCCRm register compare match m 0 to 5 INTTRnOV...

Page 390: ...and TORn1 are not output The signal input from TEVTRn and internally synchronized is counted as the count clock TRnOE0 1 0 TRnOL0 0 TRnOL1 1 Remarks 1 D1 D2 Setting values of TRnCCR0 register 0000H to FFFFH D3 Setting value of TRnCCR1 register 0000H to FFFFH 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter D1 D 2 INTTRnCC0 D1 D2 D1 FFFFH TRnCCR1 D3 D3 D3 INTTRnCC1 TRnCCR0 D3 TRnCE TORn0 TORn1 L...

Page 391: ...CCR0 and TRnCCR1 register values are not rewritten TORn0 and TORn1 are output TRnOE0 1 1 TRnOL0 0 TRnOL1 1 Remarks 1 D1 Setting value of TRnCCR0 register 0000H to FFFFH D2 Setting value of TRnCCR1 register 0000H to FFFFH 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter D1 INTTRnCC0 D1 D2 FFFFH TRnCCR1 INTTRnCC1 TRnCCR0 D2 TRnCE D1 D2 D1 D2 TORn0 TORn1 TEVTRn ...

Page 392: ...c When D1 D2 TRnCCR0 and TRnCCR1 register values are not rewritten TORn0 and TORn1 are output TRnOE0 1 1 TRnOL0 0 TRnOL1 1 Remarks 1 D1 Setting value of TRnCCR0 register 0000H D2 Setting value of TRnCCR1 register 0000H 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter 0000H INTTRnCC0 FFFFH TRnCCR1 INTTRnCC1 TRnCCR0 0000H TRnCE TORn0 TORn1 0000H ...

Page 393: ...4 d When D1 D2 TRnCCR0 TRnCCR1 register values are not rewritten TORn0 and TORn1 are output TRnOE0 1 1 TRnOL0 0 TRnOL1 1 Remarks 1 D1 Setting value of TRnCCR0 register 0001H D2 Setting value of TRnCCR1 register 0000H 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter INTTRnCC0 FFFFH TRnCCR1 INTTRnCC1 TRnCCR0 TRnCE TORn0 TORn1 0001H 0001H 0000H ...

Page 394: ...n be rewritten during count operation Compare register reload is performed at the timing when the counter value and the TR1CCR0 register match However when write access to the TR1CCR1 register is performed the next reload timing becomes valid so that even if wishing to rewrite only the value of the TR1CCR0 register write the same value to the TR1CCR1 register In this case reload is not performed e...

Page 395: ... Cycle TR1CCR1 to TR1CCR3 Reload Possible Duty TR1CCR4 TR1CCR5 Reload Possible Duty Pin Function TIR1m m 0 to 3 TTRGR1 Counter clear start through external trigger input TEVTR1 Timer count through external event count input Pin Function TOR10 Toggle output upon TR1CCR0 register compare match or external trigger input TOR1m External trigger pulse waveform output m 1 to 5 TOR16 TOR17 Interrupt Funct...

Page 396: ...al trigger TTRGR1 pin input Counter starts counting Counter clear start Initial settings Timer operation enable TR1CE 1 Transfer of valu es of TR1CCR0 to TR1CCR5 to buffers TR1CCR0 to TR1CCR5 Match between counter and TR1CCR0 counter clear start External trigger TTRGR1 pin input Clock selection TR1CTL1 TR1EEE 0 TR1CTL0 TR1CKS2 to TR1CKS0 External trigger pulse output mode setting TR1CTL1 TR1MD3 to...

Page 397: ...gister 0000H to FFFFH D11 D12 Setting values of TR1CCR1 register 0000H to FFFFH 2 TOR11 PWM duty setting value of TR1CCR1 register count clock cycle TOR11 PWM cycle setting value of TR1CCR0 register 1 count clock cycle 3 Pin TOR10 is toggled when the counter is cleared immediately following count start Counter TR1CCR1 FFFFH TR1CCR0 buffer buffer TR1CCR0 TR1CE External trigger TTRGR1 pin D01 D02 D0...

Page 398: ...pt INTTRnCC0 is output and upon a match between the counter and TRnCCR1 to TRnCCR5 buffer registers compare match interrupts INTTRnCC1 to INTTRnCCR5 are output The TRnCCR0 and TRnCCR1 registers can be rewritten using the anytime write method regardless of the value of bit TRnCE Even a trigger is input during the counter operation it is ignored Be sure to input the second trigger when the counter i...

Page 399: ...cle TRnCCR1 to TRnCCR3 Anytime rewrite Possible Output delay value TRnCCR4 TRnCCR5 Anytime rewrite Possible Output delay value Pin Function TIR1m m 0 to 3 TTRGR1 Counter start through external trigger input TEVTR1 Pin Function TORn0 Active at count start inactive upon TRnCCR0 register match TORnm Active upon TRnCCRm register match inactive upon TRnCCR0 register match m 1 to 5 TORn6 TORn7 Interrupt...

Page 400: ...n enable TRnCE 1 Transfer of values of TRnCCR0 to TRnCCR5 to buffers TRnCCR0 to TRnCCR5 Initial settings Clock selection TRnCTL1 TRnEEE 0 TRnCTL0 TRnCKS2 to TRnCKS0 One shot pulse mode setting TRnCTL1 TRnMD2 to TRnMD0 011 Compare register setting TRnCCR0 to TRnCCR5 Trigger wait status counter in standby at FFFFH Trigger wait status counter in standby at 0000H Match between counter and buffers TRnC...

Page 401: ...ng value of TRnCCR0 register 0000H to FFFFH D1 Setting value of TRnCCR1 register 0000H to FFFFH 2 TORn1 output delay setting value of TRnCCR1 register count clock cycle TORn1 output pulse width setting value of TRnCCR0 register 1 setting value of TRnCCR1 register count clock cycle 3 n 0 1 0000H Counter INTTRnCC0 FFFFH TRnCCR1 INTTRnCC1 TRnCCR0 TRnCE External trigger TTRGR1 pin Note2 TORn1 TRnEST D...

Page 402: ...buffer register During count operation a compare match interrupt INTTRnCC0 is output upon a match between the counter and TRnCCR0 register and compare match interrupts INTTRnCC1 to INTTRnCC5 are output upon a match between the counter and TRnCCR1 to TRnCCR5 registers The TRnCCR0 to TRnCCR5 registers can be rewritten during count operation Compare register reload occurs upon a match between the cou...

Page 403: ... TRnCCR0 Reload Possible Cycle TRnCCR1 to TRnCCR3 Reload Possible Duty TRnCCR4 TRnCCR5 Reload Possible Duty Pin Function TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORn0 Toggle output upon TRnCCR0 register compare match TORnm PWM output upon TRnCCRm register compare match m 1 to 5 TORn6 TORn7 Pulse output through A D conversion trigger Interrupt Function INTTRnCCm TRnCCRm register compare match INT...

Page 404: ...ence Timer operation enable Transfer of value of TRnCCRm to TRnCCRm buffer TORn1 to TORn5 output low level upon a match between counter and TRnCCR1 to TRnCCR5 bffers Upon a match between counter and TRnCCR0 buffer counter clear start and TORn1 to TORn5 output high level INTTRnCC1 to INTTRnCC5 occurrence Initial settings Clock selection TRnCTL0 TRnCKS2 to TRnCKS0 PWM mode setting TRnCTL1 TRnMD3 to ...

Page 405: ...ORn1 to TORn5 output low level Timer operation enable TRnCE 1 Transfer of value of TRnCCRm to TRnCCRm buffer Upon a match between counter and TRnCCR1 to TRnCCR5 TORn1 to TORn5 output low level TRnCCR0 rewrite TRnCCR1 rewrite Upon a match between counter and TRnCCR0 counter clear start and TORn1 to TORn5 output high level 1 INTTRnCC1 to INTTRnCC5 occurrence INTTRnCC0 occurrence INTTRnCC1 to INTTRnC...

Page 406: ...1 D12 D13 Setting values of TRnCCR1 register 0000H to FFFFH 2 TORn1 PWM duty setting value of TRnCCR1 register count clock cycle TORn1 PWM cycle setting value of TRnCCR0 register 1 count clock cycle TORn0 is toggled immediately following counter start and at setting value of TRnCCR0 register 1 count clock cycle 3 n 0 1 Counter FFFFH TRnCCR1 TRnCCR0 TRnCE TORn1 TRnCCR0 buffer TRnCCR1 buffer D00 D00...

Page 407: ...0 buffer register was not performed Held until the next reload timing Remarks 1 D00 D01 D02 D03 Setting values of TRnCCR0 register 0000H to FFFFH D10 D11 D12 D13 Setting values of TRnCCR1 register 0000H to FFFFH 2 The TORn0 and TORn1 pins become high level at timer count start 3 n 0 1 Counter FFFFH TRnCCR1 TRnCCR0 TRnCE TORn1 TRnCCR0 buffer TRnCCR1 buffer D00 0000H D10 D11 D12 D12 D10 D11 D12 0000...

Page 408: ...etween TRnCCR0 buffer and counter TIRn0 edge detection settings TRnIS1 TRnIS0 TRnCCS1 0 TRnCCS0 0 TRnCCS1 0 TRnCCS0 0 TRnCCS1 1 TRnCCS0 1 TRnCCS1 1 TRnCCS0 1 Timer operation enable TRnCE 1 Transfer of values of TRnCCR0 and TRnCCR1 to TRnCCR0 and TRnCCR1 buffers Timer operation enable TRnCE 1 Transfer of value of TRnCCR1 to TRnCCR1 buffer Counter overflow Timer operation enable TRnCE 1 Transfer of ...

Page 409: ...gister Rewrite Method Rewrite during Operation Function TRnCCR0 Anytime rewriteNote 1 PossibleNote 1 Capture or compare value TRnCCR1 to TRnCCR3 Anytime rewriteNote 1 PossibleNote 1 Capture or compare value TRnCCR4 TRnCCR5 Anytime rewrite Possible Compare value Pin Function TIR1m Input capture trigger transfer counter value to TR1CCRm register m 0 to 3 Note 2 TTRGR1 TEVTR1 Pin Function TORnm Toggl...

Page 410: ...ed in the free running mode until TRnCE 0 is set Moreover during count operation a compare match interrupt INTTRnCC0 is output upon a match between the counter and TRnCCR0 buffer register and a compare match interrupt INTTRnCC1 is output upon a match between the counter and TRnCCR1 buffer register The TRnCCR0 and TRnCCR1 registers can be rewritten using the anytime write method regardless of the v...

Page 411: ...0000H to FFFFH D10 D11 Setting values of TRnCCR1 register 0000H to FFFFH 2 TORn0 toggle width setting value of TRnCCR0 register 1 count clock cycle 3 TORn1 toggle width setting value of TRnCCR1 register 1 count clock cycle 4 Pins TORn0 and TORn1 become high level at count start 5 n 0 1 0000H Counter FFFFH TRnCCR1 TRnCCR0 TRnCE INTTRnCC1 D00 D00 D01 D11 D11 D10 D00 D01 D11 D10 INTTRnCC0 D00 D01 D10...

Page 412: ...e trigger interval is such that it includes two overflow occurrences 2 or more free running cycles Cautions 1 In free running mode the external event clock input TEVTR1 is prohibited TR1CTL1 TR1EEE 0 2 When an internal count clock fXX 16 TRnCTL0 TRnCKS2 0 is selected in free running mode the TRnCCR0 and TRnCCR1 registers are used as capture regis ters the a value of FFFFH will be captured if a val...

Page 413: ...ree running mode the external event clock input TEVTR1 is prohibited TR1CTL1 TR1EEE 0 2 When an internal count clock fXX 16 TRnCTL0 TRnCKS2 0 is selected in free running mode and TRnCCR0 register is used as capture register the a value of FFFFH will be captured if a valid signal edge is input before the first count up Figure 10 53 Basic Operation Timing in Free Running Mode Compare Capture Functio...

Page 414: ...6 Overflow flag When in the free running mode the counter overflows from FFFFH to 0000H the overflow flag TRnOVF is set to 1 and an overflow interrupt INTTRnOV is output The overflow flag is cleared through 0 write from the CPU The overflow flag is not cleared by just being read ...

Page 415: ...ge detection pulse width measurement can be similarly performed by using the TR1CCR1 to TR1CCR3 registers Figure 10 54 Basic Operation Timing in Pulse Width Measurement Mode TR1OE0 1 0 TR1OL0 1 0 Remarks 1 D00 D01 D02 D03 Values captured to TR1CCR0 register 0000H to FFFFH 2 TIR10 Setting to rising edge falling edge both edges detection TRnIOC1 register bits TR1IS1 TR1IS0 1B Cautions 1 In the pulse...

Page 416: ...upts Register Rewrite Method Rewrite during Operation Function TR1CCR0 Capture value TR1CCR1 to TR1CCR3 Capture value TR1CCR4 TR1CCR5 Pin Function TIR1m Input capture trigger transfer counter value to TR1CCRm register m 0 to 3 TTRGR1 TEVTR1 Pin Function TOR10 to TOR15 TOR16 TOR17 Interrupt Function INTTR1CCm TIR1m capture m 0 to 3 INTTR1CC4 INTTR1CC5 INTTR1OV Overflow INTTR1ER ...

Page 417: ...unter and TRnCCR1 to TRnCCR5 registers a compare match interrupt INTTRnCC1 is output Moreover upon counter underflow an overflow interrupt INTTRnOV is output The TRnCCR0 to TRnCCR5 registers can be rewritten during count operation Compare register reload occurs upon a match between the counter value and the TRnCCR0 buffer register However since the next reload timing becomes valid when the TRnCCR1...

Page 418: ...eload Possible 1 2 of cycle TRnCCR1 to TRnCCR3 Reload Possible 1 2 of duty TRnCCR4 TRnCCR5 Reload Possible 1 2 of duty Pin Function TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORn0 Inactive during counter up count active during down count TORnm PWM output upon TRnCCRm register compare match m 0 to 5 TORn6 TORn7 Pulse output through A D conversion trigger Interrupt Function INTTRnCCm TRnCCRm registe...

Page 419: ...580EE3V1UD00 Figure 10 55 Basic Operation Timing in Triangular Wave PWM Mode When TORn0 TORn1 are output TRnOE0 1 1 TRnOL0 1 0 Remark n 0 1 D00 D10 Counter FFFFH INTTRnCC0 TRnCE D00 TRnCCR0 0000H FFFFH TRnCCR1 0000H D10 D10 INTTRnCC1 D00 D10 D00 INTTRnOV TORn0 TORn1 ...

Page 420: ...m value and upon a match with the maximum value indicated by TRnCCR0 TRnDTC1 performing down count The 10 bit counters for dead time generation TRnDTT1 to TRnDTT3 load the setting values of the TRnDTC0 and TRnDTC1 registers upon a match between the counter and the TRnCCR1 to TRnCCR3 registers and perform down count Upon a match between the 16 bit counter and the TRnCCR1 to TRnCCR3 registers INTTRn...

Page 421: ...selectable as A D conversion trigger Pin Function TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORn0 Inactive during counter or sub counter up count active during down count TORn1 PWM output upon TRnCCR1 compare match with dead time TORn2 Inverted output to TORn1 TORn3 PWM output upon TRnCCR2 compare match with dead time TORn4 Inverted output to TORn3 TORn5 PWM output upon TRnCCR3 compare match with ...

Page 422: ...a timer Rn internal circuit fault If the dead time setting is 000H a glitch may occur upon occurrence of an error interrupt INTTRnER at the normal phase and inverted phase switch timing d Rewrite timing for registers with reload function Batch rewrite anytime rewrite can be set for registers with the reload function This setting is performed with TRnOPT0 register bit RnCMS The default is 0 batch r...

Page 423: ... and TRnDTC1 registers The dead time can be obtained with counter operation clock cycle P TRnDTC0 TRnDTC1 The time until TORn2 TORn4 TORn6 pin inactive change TORn1 TORn3 TORn5 pin active change can be set with the TRnDTC0 register The time until TORn1 TORn3 TORn5 pin inactive change TORn2 TORn4 TORn6 pin active change can be set with the TRnDTC1 register i Carrier wave cycle For the carrier wave ...

Page 424: ... FFFEH the value of TRnDTC0 register is loaded to the sub counter immediately after TRnCE 1 is set Then until a match with 0000H the sub counter counts down in 2 steps and the counter value is loaded to the sub counter at the counter s up count down count switch timing The TRnDTC0 register goes on counting up and upon a match with the TRnCCR0 register starts counting down in 2 steps At the same ti...

Page 425: ...cy T PWM Mode Remarks 1 TRnCCR0 0010H TRnDTC0 0002H TRnDTC1 0004H 2 TD0 Time depends on dead time setting of TRnDTC0 register TD1 Time depends on dead time setting of TRnDTC1 register TS1 Time is determined through sub counter compare when sub counter value counter value 3 n 0 1 TRnCCR0 TORn1 TORn2 Counter FFFE 00020004 0008 000A 000C 000A 00080006000400020004 0006 FFFE 00000002000400060008 000E 0...

Page 426: ...04H 2 TD0 Time depends on dead time setting of TRnDTC0 register TD1 Time depends on dead time setting of TRnDTC1 register TS0 Time is determined through sub counter compare when sub counter value counter value TS1 Time is determined through sub counter compare when sub counter value counter value 3 n 0 1 TRnCCR0 TORn1 TORn2 000400060008 000A 000C 000A 000800060004000200040006 00000002000400060008 ...

Page 427: ...xample When Performing Additional Pulse Control Remarks 1 TRnCCR0 12 TRnDTC0 0 TRnDTC1 0 2 n 0 1 The locations where additional pulse control is performed are when an odd value has been set to the TRnCCR1 register In the above figure the arrows and numbers indicate the duty width of the TORn1 pin output within 1 cycle As can be seen in the above figure when additional pulse control is performed th...

Page 428: ...ve figure the arrows and numbers indicate the duty width of the TORn1 pin output within 1 cycle When additional pulse control is not performed the output width of pin TORn1 can be controlled in 2 count clock steps from 12 clocks to 0 clocks In this case the duty change amount is larger compared to when additional pulse control is performed TRnCCR1 0 TRnCCR1 2 TRnCCR1 4 TRnCCR1 6 TRnCCR1 8 TRnCCR1 ...

Page 429: ...er setting is changed like this a match between the 16 bit counter and TRnCCR1 register does not occur thereafter Therefore the TORn1 pin output level is forcibly changed to inactive level at the following 16 bit sub counter trough timing Output will be switched at 16 bit sub counter peak trough timing after that Figure 10 63 Timings of Timer Output in High accuracy T PWM mode 1 3 a Output When TR...

Page 430: ...TC1 TRnCCRm TRnCCR0 TRnDTC0 TRnDTC1 to TRnCCRm TRnDTC0 TRnDTC1 Figure 10 63c shows the output waveform when rewriting the TRnCCR1 register from x TRnDTC0 TRnDTC1 x TRnCCR0 TRnDTC0 TRnDTC1 to y y TRnDTC0 TRnDTC1 In this case the TORn1 pin output becomes active when the TORn1 pin set condition occurs upon a match between the 16 bit counter or 16 bit sub counter and the TRnCCR1 regis ter immediately ...

Page 431: ...DTC0 TRnDTC1 TRnDTC0 TRnCCR0 In this case the TORn2 pin output becomes inactive high level when the TORn2 pin set condition occurs upon a match between the 16 bit counter or 16 bit sub counter and TRnCCRm register immediately after batch rewrite Figure 10 63 Timings of Timer Output in High accuracy T PWM mode 3 3 d Output When Rewriting from TRnDTC0 TRnDTC1 TRnCCR1 TRnCCR0 TRnDTC0 TRnDTC1 to TRnCC...

Page 432: ...tch interrupt occurs between TRnCCR0 and TRnDTC0 the operation is cleared by special processing Clear RT5 The operation is cleared upon a match between peripheral 16 bit sub counter peak and compare register values in positive phase active level Table 10 2 Negative Phase Operation Condition List Operation Symbol Condition Set SB1 Match between counting down near the 16 bit sub counter peak and com...

Page 433: ...o 0000H 0000H TRnCCR1 to TRnCCR3 TRnDTC0 Figureaa TRnCCR1 to TRnCCR3 0000H TRnDTC0 1 Figureab TRnDTC0 1 TRnCCR1 to TRnCCR3 TRnDTC0 2 Figure 10 64c TRnDTC0 2 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC0 TRnDTC1 Figure 10 64d TRnCCR0 TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 64e TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 Figure 10 64f TRnCCR1 to TRnCCR3 TRnCCR0 Figure 10 64g TRnDTT1 to TRnD...

Page 434: ...ure 10 64c To prevent this phenomenon change 0000H TRnCCR1 to TRnCCR3 TRnDTC0 to TRnDTC0 TRnCCR1 to TRnCCR3 TRnDTC 2 through TRnDTC0 or directly change 0000H TRnCCR1 to TRnCCR3 TRnDTC0 to TRnDTC0 2 TRnCCR1 to TRnCCR3 d TRnCCR1 to TRnCCR3 0000H TRnDTC0 2 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 TRnDTC0 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn5 TORn6 16 bit counter 16 bit sub counter 0000H ST3 ST2 ...

Page 435: ...nCCR1 to TRnCCR3 0000H TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H ST3 SB2 RT2 RT3 TRnCCR0 RB2 RT2 SB2 RB2 SB2 TRnCCR1 to TRnCCR3 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H ST3 SB2 RT3 TRnCCR0 RB1 SB1 RB1 SB1 TRnCCR1 to TRnCCR3 TRnDTT1 to TRnDTT3 TORn1 T...

Page 436: ...H Figure 10 65a 0000H TRnCCR1 to TRnCCR3 TRnDTC0 Figure 10 65b TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC0 1 Figure 10 65c TRnDTC0 1 TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC1 Figure 10 65d TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC0 TRnDTC1 Figure 10 65e TRnCCR0 TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 65f TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 Figure 10 65g TRnDTT1 to TRnDTT3 TORn1...

Page 437: ...RnCCR0 TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 TRnDTC0 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 ST2 TRnCCR0 ST1 RB5 RT1 TRnCCR1 to TRnCCR3 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 ST2 TRnCCR0 ST2 RB2 RT2 TRnCCR1 to TRnCCR3 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 T...

Page 438: ...e No TRnCCR0 TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 Figure 10 66a TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 66b TRnCCR0 TRnDTC1 2 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 66c TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 2 Figure 10 66d TRnDTC0 1 TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC1 Figure 10 66e 0000H TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC1 Figure 10 66f TRnCCR1 to TRnCCR3 0000H Figure 1...

Page 439: ...R0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 b TRnCCR1 to TRnCCR3 TRnCCR0 TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 SB1 RB1 TRnCCR0 SB1 RB1 L TRnCCR1 to TRnCCR3 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 SB1 RB1 TRnCCR0 SB1 RB4 L TRnCCR1 to TRnCCR3 ...

Page 440: ...gure below To prevent this phenomenon change TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 to TRnDTC0 TRnCCR1 to TRnCCR3 TRnDT1 2 through TRnCCR0 TRnDTC1 or directly change TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 to TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 2 d TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 x 2 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit s...

Page 441: ...CCR1 to TRnCCR3 TRnCCR0 TRnCCR1 to TRnCCR3 0000H TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 ST2 RB3 TRnCCR0 RT2 TRnCCR1 to TRnCCR3 RB2 ST2 ST2 RT2 RB2 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB3 ST2 RB3 TRnCCR0 RT1 TRnCCR1 to TRnCCR3 ST1 ST1 RT1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 ...

Page 442: ...3 TRnCCR0 Figure 10 67a TRnCCR0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 Figure 10 67b TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 67c TRnCCR0 TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC1 Figure 10 67d TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC0 TRnDTC1 Figure 10 67e TRnDTC0 1 TRnCCR1 to TRnCCR3 TRnDTC0 TRnDTC1 Figure 10 67f 0000H TRnCCR1 to TRnCCR3 TRnDTC0 1 Figure 10 67g TRnDTT1 to TRnDT...

Page 443: ... 0000H TRnDTC0 TRnDTC1 TRnCCR1 to TRnCCR3 TRnCCR0 TRnDTC0 TRnDTC1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB2 RB1 TRnCCR0 SB1 RT1 TRnCCR1 to TRnCCR3 RB1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H SB2 RB2 TRnCCR0 SB2 RT1 TRnCCR1 to TRnCCR3 RB2 RT1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TOR...

Page 444: ...1 to TRnCCR3 TRnDTC0 TRnDTC1 g TRnCCR1 to TRnCCR3 0000H 0000H TRnCCR1 to TRnCCR3 TRnDTC0 1 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit sub counter 16 bit sub counter 0000H L RB2 TRnCCR0 RT2 TRnCCR1 to TRnCCR3 RB2 RT2 ST2 ST2 TRnDTT1 to TRnDTT3 TORn1 TORn3 TORn5 TORn2 TORn4 TORn6 16 bit counter 16 bit sub counter 0000H L TRnCCR0 RT1 TRnCCR1 to TRnCCR3 RT1 ST1 ST1 ...

Page 445: ...bit counter and two dead time setting registers TRnDTC0 TRnDTC1 The TRnDTC0 register is used to set the dead time from when a negative phase changes to inac tive until a positive phase changes to active The TRnDTC1 register is used to set the dead time from when a positive phase changes to inactive until a negative phase changes to active The output waveform in case of TRnDTC0 x TRnDTC1 y is shown...

Page 446: ...and TRnDTC1 registers 3 Rewriting is prohibited when TRnCMS 1 4 In case of changing TRnCCR0 and TRnCCR1 at a 16 bit counter peak Match interrupts INTTRnCC1 to INTTRnCC5 will not occur immediately after reload execution if the values set in the TRnCCR1 to TRnCCR5 register matches with and TRnCCR0 TRnDTC1 the new maximum value of main counter after updating Figure 10 69 Dead Time Control in High Acc...

Page 447: ...s executed from 0000H because no match occurs In this case the count opera tion continues by loading the TRnDTC0 register setting value However no match with TRnCCR0 TRnDTC1 occurs in the count up operation thus the 16 bit counter overflows In this case the count operation continues by loading the TRnDTC0 register setting value again An overflow interrupt INTTRnOV occurs when the 16 bit counter lo...

Page 448: ...n be used in the high accuracy T PWM mode Error interrupts INTTRnER do not occur in the high accuracy T PWM mode In case of occurrence the internal circuits may be damaged Figure 10 71 Error Interrupt Operation Example 16 bit counter TORn1 TORn2 INTTRnER TRnTBF Damage occurrence in TORn2 control circuit Error interrupt output Positive negative simultaneous active detection flag set 0 write clear ...

Page 449: ...minimum value and when the maximum value cycle indicated by the TRnCCR0 register is matched the counter is cleared 0000H and the counter continues up count operation The 10 bit dead time counters TRnDTT1 to TRnDTT3 reload the setting value of the TRnDTC0 and TRnDTC1 registers upon a match between the counter and the TRnCCR1 to TRnCCR3 registers and perform down count Upon a match between the 16 bi...

Page 450: ...tion TIR1m m 0 to 3 TTRGR1 TEVTR1 Pin Function TORn0 Toggle output upon TRnCCR0 register compare match TORn1 PWM output with dead time upon TRnCCR1 register compare match TORn2 Inverted phase output to TORn1 TORn3 PWM output with dead time upon TRnCCR2 register compare match TORn4 Inverted phase output to TORn3 TORn5 PWM output with dead time upon TRnCCR3 register compare match TORn6 Inverted phas...

Page 451: ...RnCCR3 registers PWM is output with 100 duty 4 The maximum value of the TRnCCR0 register is FFFFH TRnDTC0 5 Perform setting so as to satisfy condition FFFFH TRnCCR0 TRnDTC0 i j k FFFFH 0H TRnCCR0 TRnCCR1 TRnCCR2 TRnCCR3 TRnDTC0 d0 TRnDTC1 d1 d0 d0 d1 d0 d0 d1 d0 d0 d1 d1 i j m d1 TRnDTT1 TRnDTT2 TRnDTT3 TORn1 TORn2 TORn3 TORn4 TORn5 TORn6 Counter m for cycle setting i U phase duty j V phase duty k...

Page 452: ...dicates an internal circuit fault d Interrupt and thinning out function settings A peak interrupt INTTRnCD occurs upon a match between the TRnCCR0 register and the counter bit TRnIOE control is invalid To output a peak interrupt set TRnICE 1 Use of the thinning out function for peak interrupts is done with the TRnID4 to TRnID0 registers e Reload thinning out function setting To set the reload timi...

Page 453: ...e setting range of the TRnCCR1 to TRnCCR3 registers is 0000H TRnCCRm TRnCCR0 TRnDTC0 The TRnCCR0 and TRnDTC0 registers must be set so as to satisfy TRnCCR0 TRnDTC0 FFFFH Remark n 0 1 m 1 to 3 4 Operation in PWM mode with dead time The figure shows the timing chart when TRnCCR0 0007H TRnDTC0 0002H TRnDTC1 0002H and the TRnCCR0 register is set to 0000H to 0007H one part When the compare value of the...

Page 454: ...re provided The TRnDTC0 register is used to set the dead time from when the inverted phase becomes inactive to when the normal phase becomes active and the TRnDTC1 register is used to set the dead time from when the normal phase becomes inactive to when the inverted phase becomes active The following figure shows an output example when TRnDTC0 x TRnDTC1 y TRnCCR0 TORn1 TORn2 FFFF 00000001000200030...

Page 455: ...er 10 16 bit Inverter Timer Counter R User s Manual U16580EE3V1UD00 Figure 10 75 Output Waveform Example in PWM Mode with Dead Time TRnDTT1 2 3 TRnDTC0 x TRnDTC1 y TORn1 3 5 TORn2 4 6 x y x y x y TRnCCR0 Counter ...

Page 456: ...TRnER is output as long as no hardware fault occurs except when TRnDTC0 TRnDTC1 0000H is set Also when TRnDTC0 TRnDTC1 000H is set glitches may occur upon error interrupt INTTRnER output In this case the occurrence of glitches during error interrupt INTTRnER output can be prevented by setting bit TRnEOC to 0 Figure 10 76 Error Interrupt INTTRnER in PWM Mode with Dead Time TORn1 TORn2 INTTRnER TRnT...

Page 457: ...it accuracy PWM output function Free running function Pulse width measurement function 2 phase encoder function Triangular wave PWM output function Offset trigger generation function 11 2 Function Outline Capture trigger input signal 2 Encoder input signal 2 Encoder clear signal 1 External trigger input signal 1 External event input 1 Readable counter 1 Count write buffer 1 Capture compare reload ...

Page 458: ...gister TTnCNT TMTn counter write buffer register TTnTCW TTnCCR0 buffer register TTnCCR1 buffer register Timer input pins 7 TITn0 TITn1 TEVTTn TTRGTn TENCTn0 TENCTn1 TECRTn Note Timer output pins 2 TOTn0 TOTn1 Note Timer input signals Timer output signals TTnEQC0 TTnEQC1 Control registers TMTn control registers 0 1 TTnCTL0 to TTnCTL2 TMTn I O control registers 0 to 2 TTnIOC0 to TTnIOC3 TMTn option ...

Page 459: ...ter 0 TT0CCR0 R W 0000H FFFFF69CH TMT0 capture compare register 1 TT0CCR1 R W 0000H FFFFF69EH TMT0 counter read buffer register TT0CNT R 0000HNote FFFFF990H TMT0 counter write buffer register TT0TCW R W 0000H FFFFF6A0H TMT1 control register 0 TT1CTL0 R W 00H FFFFF6A1H TMT1 control register 1 TT1CTL1 R W 00H FFFFF6A2H TMT1 control register 2 TT1CTL2 R W 00H FFFFF6A3H TMT1 I O control register 0 TT1...

Page 460: ... 32 φ 64 Counter Control COUNT UP DOWN TTnCCR1 buffer TO Control TTnCCR1 TTnEQC1 INTTTnCC1 TTnEQC0 INTTTnCC0 TOTn0 INTTTnOV TTRGTn TEVTTn TITn1 TITn0 TTnCCR1 TTnCCR0 Edge detector LOAD TTnCCR0 buffer LOAD TOTn1 TTnCCR0 Clear Clear Encoder clock generator TENCTn0 TENCTn1 TECRTn LOAD TTnTCW INTTTnEC LOAD φ 256 φ 1024 φ 2 TTnCNT Counter Internal bus Internal bus ...

Page 461: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTnCCR0 Table 11 3 Capture Compare Functions in Each Mode Operation Mode Capture Compare Setting of TTnCCR0 Register Rewriting Method during Compare Counter Clear Function Interval mode Compare only Anytime write Compare match External event count mode Compare only Anytime write Compare match External trigger pulse output mode Compare only Batch write Reload Co...

Page 462: ...e TTnCR0 register upon TITn0 pin input edge detection The function to clear counters following capture differs according to the operation mode Refer to Table 11 3 Capture Compare Functions in Each Mode 2 TMTn capture compare register 1 TTnCCR1 The TTnCCR1 register is a 16 bit register that functions both as a capture register and a compare register This register can be read and written in 16 bit u...

Page 463: ... detection is saved to the TTnCCR1 register The function to clear the counter following capture also differs according to the mode Refer to Table 11 4 Capture Compare Functions in Each Mode Table 11 4 Capture Compare Functions in Each Mode Operation Mode Capture Compare Setting of TTnCCR1 Register Rewriting Method during Compare Counter Clear Function Interval mode Compare only Anytime write Exter...

Page 464: ... Register TTnTCW 4 TMTn counter read buffer register TTnCNT The TTnCNT register is a read buffer register that can read the counter value This register can be read in 16 bit units only Reset input clears this register to 0000H Remark When in the encoder compare mode encoder capture mode the value of the TTnCE bit is changed from 1 to 0 the value that can be read by the TTnCNT register differs acco...

Page 465: ...hen bit TTnCE is set to 0 the internal operation clock of TMTn stops fixed to low level and TMTn is reset asynchronously When bit TTnCE is set to 1 the internal operation of TMTn is enabled from when bit TTnCE was set to 1 and count up is performed The time until count up is as listed in Table TMTn Count Clock and Time Until Count Up Remarks 1 In the encoder compare mode encoder capture mode the f...

Page 466: ...0 Internal Count Clock Selection 0 0 0 fXX 2 0 0 1 fXX 4 0 1 0 fXX 8 0 1 1 fXX 16 1 0 0 fXX 32 1 0 1 fXX 64 1 1 0 fXX 256 1 1 1 fXX 1024 Table 11 5 TMTn Count Clock and Count Delay Count Clocks TTnCKS2 TTnCKS1 TTnCKS0 Count Delay Minimum Maximum fXX 2 0 0 0 3 base clocks 4 base clocks fXX 4 0 0 1 fXX 8 0 1 0 fXX 16 0 1 1 4 base clocks 5 base clocks 1 count clock fXX 32 1 0 0 fXX 64 1 0 1 fXX 256 1...

Page 467: ...writing was mistakenly performed set TTnCE 0 and then set the bit again Remark n 0 1 After reset 00H R W Address TR0CTL1 FFFFF691H TR1CTL1 FFFFF6A1H 7 6 5 4 3 2 1 0 TTnCTL1 0 TTnEST TTnEEE 0 TTnMD3 TTnMD2 TTnMD1 TTnMD0 n 0 1 TTnEST Software Trigger Control 0 No operation 1 Enable software trigger control In one shot pulse mode One shot pulse software trigger Can be made to function as a software t...

Page 468: ...is performed when TTnCE 1 If rewriting was mistakenly performed set TTnCE 0 Remark n 0 1 TTnMD3 TTnMD2 TTnMD1 TTnMD0 Timer Mode 0 0 0 0 Interval mode 0 0 0 1 External event count mode 0 0 1 0 External trigger pulse output mode 0 0 1 1 One shot pulse mode 0 1 0 0 PWM mode 0 1 0 1 Free running mode 0 1 1 0 Pulse width measurement mode 0 1 1 1 Triangular wave PWM mode 1 0 0 0 Encoder compare mode 1 1...

Page 469: ...the counter to be reset to FFFFH the capture registers TTnCCR0 TTnCCR1 to be reset to 0000H and the encoder dedicated flags TTnEOF TTnEUF TTnESF to be reset to 0 When TTnECC 0 the value of the TTnTCW register is loaded to the counter when TTnCE is set from 0 to 1 When TTnECC 1 setting TTnCE 0 causes the values of the counter capture registers TTnCCR0 TTnCCR1 and encoder dedicated flags TTnEOF TTnE...

Page 470: ...ode TTnUDS1 TTnUDS0 Encoder Operation Mode 0 0 Upon detection of the valid edge of the A phase of encoder input TENCTn0 pin the following count operation is performed in the B phase of encoder input When high count down When low count up 0 1 Count up upon detection of valid edge of A phase of encoder input TENCTn0 pin Count down upon detection of valid edge of B phase of encoder input TENCTn1 pin ...

Page 471: ...the TTnIOC0 register can be performed using the same value Figure 11 9 TMTn I O Control Register 0 TTnIOC0 Remark n 0 1 m 0 1 After reset 00H R W Address TR0IOC0 FFFFF693H TR1IOC0 FFFFF6A3H 7 6 5 4 3 2 1 0 TTnIOC0 0 0 0 0 TTnOL1 TTnOE1 TTnOL0 TTnOE0 n 0 1 TTnOLm Timer Output Level Setting TOTnm pin 0 Normal output Low level when output is inactive 1 Inverted output High level when output is inacti...

Page 472: ...TnIS1 TTnIS0 n 0 1 TTnIS3 TTnIS2 Capture Input TITn1 Valid Edge Setting 0 0 No edge detection capture operation invalid 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection Capture operation is performed and capture interrupt INTTTnCC1 is output upon edge detection Remark The setting of bits TTnIS3 and TTnIS2 are valid in the free running mode and pulse w...

Page 473: ...2 FFFFF695H TT1IOC2 FFFFF6A5H 7 6 5 4 3 2 1 0 TTnIOC2 0 0 0 0 TTnEES1 TTnEES0 TTnETS1 TTnETS0 n 0 1 TT1EES1 TT1EES0 External Event Counter Input TEVTTn Valid Edge Setting 0 0 No edge detection capture operation invalid 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both rising and falling edge detection Remark The settings of bits TTnEES1 and TTnEES0 are valid in the external event count...

Page 474: ...level When TTnSCE 1 the counter is cleared to 0000H if all the conditions set with bits TTnZCL TTnBCL and TTnACL are matched When TTnSCE 1 the settings of bits TTnECS1 and TTnECS0 are invalid so no encoder clear interrupt INTTTnEC is output When TTnSCE 0 the settings of bits TTnZCL TTnBCL and TTnACL are invalid The settings of bits TTnECS1 and TTnECS0 become valid and the encoder clear interrupt I...

Page 475: ...pt INTTTnEC is output upon detection of the valid edge set with bits TTnECS1 TTnECS0 Caution When TTnSCE 1 the encoder clear interrupt INTTTnEC is not output Remark Bits TTnECS1 and TTnECS0 are valid in the encoder compare mode and when TTnSCE 0 TTnEIS1 TTnEIS0 Set the valid edge of the encoder input signal TENCTn1 TENCTn0 pins 0 0 No edge detection 0 1 Rising edge detection 1 0 Falling edge detec...

Page 476: ...capture register Remark The setting of bit TTnCCS0 is valid in the free running mode only TTnOVF Flag that indicates TMTn overflow 0 No overflow occurrence after timer restart or flag reset 1 Overflow occurrence In the free running mode pulse width measurement mode and offset trigger generation mode if the counter value is counted up from FFFFH overflow occurs the TTnOVF flag is set 1 and the coun...

Page 477: ...nOPT1 0 0 0 0 0 TTnEUF TTnEOF TTnESF n 0 1 TTnEUF Indication of Encoder Underflow 0 No underflow indicated 1 Indicates counter underflow in the encoder compare mode If the counter value is counted down from 0000H underflow occurs the OVF flag is set to 1 and the counter is set to FFFFH When the TTnEUF flag is set to 1 an overflow interrupt INTTTnOV occurs at the same time The TTnEUF flag is cleare...

Page 478: ... instruction When TTnCE 0 is set while TTnECC 0 Cautions 1 The TTnEOF flag is not cleared even if it is read 2 The TTnEOF flag can be read and written but even if 1 is written to the TTnEOF flag from the CPU this is invalid Remark When bit TTnECC of the TTnCTL2 register is 1 the flag status is held even if the value of bit TTnCE is changed from 1 to 0 TTnESF Indication of Encoder Count Direction 0...

Page 479: ...ODE and offset trigger generation using the reload method In all other modes the read contents are 0 Figure 11 15 TMTn Option Register 2 TTnOPT2 Remark n 0 1 After reset 00H R W Address TT0OPT2 FFFFF699H TT1OPT2 FFFFF6A9H 7 6 5 4 3 2 1 0 TTnOPT2 0 0 0 0 0 0 0 TTnRSF n 0 1 TTnRSF Reload Status Flag 0 No reload request or reload completed 1 Reload request was output It indicates that the data to be ...

Page 480: ...TTnCE changes from 0 to 1 b Triangular wave PWM MODE The counter starts counting from initial value FFFFH It counts up FFFFH 0000H 0001H 0002H 0003H Following count up operation the counter counts down upon a match with the TTnCCR0 register c Modes other than the above The counter starts counting from initial value FFFFH It counts up FFFFH 0000H 0001H 0002H 0003H 2 Counter clear operation There ar...

Page 481: ...TnCE 1 is set next 4 Counter read operation during counter operation In TMT the counter value can be read during count operation using the TTnCNT register Remark n 0 1 Table 11 6 Counter Clear Operation Operation Mode Clear Cause TTnCCR0 TTnCCR1 Other Interval mode Compare match External event count mode Compare match External trigger pulse output mode Compare match External trigger TTRGTn pin One...

Page 482: ...ement mode and offset trigger generation mode capture operation is performed for counter value FFFFH and the counter is cleared to 0000H 6 Underflow operation Counter underflow occurs in the triangular wave PWM Mode and encoder compare mode Underflow occurs when the counter value changes from 0000H to FFFFH When underflow occurs in the triangular wave PWM mode an overflow interrupt INTTTnOV occurs...

Page 483: ...n the write value is immediately transferred to the TTnCCR0 buffer register and TTnCCR1 buffer register and is used as the value to be compared with the counter Figure 11 16 Basic Operation Flow for Anytime Rewrite Remarks 1 The interval mode is used as an example 2 n 0 1 START Initial settings INTTTnCC0 occurrence TTnCCR1 rewrite Transfer to buffer TTnCCR1 TTnCCR0 rewrite Transfer to buffer TTnCC...

Page 484: ...Remarks 1 D01 D02 Setting values of TTnCCR0 register 0000H to FFFFH D11 D12 Setting values of TTnCCR1 register 0000H to FFFFH 2 The interval mode is used as an example 3 n 0 1 Counter TTnCCR0 TTnCCR0 buffer TTnCCR1 TTnCCR1 buffer D01 D01 D02 D11 D11 D12 D12 INTTTnCC0 INTTTnCC1 D01 0000H D11 D12 D02 TTnCE D01 D02 0000H D11 D12 ...

Page 485: ...ing to the TTnCCR1 register the value becomes valid at the next reload timing Therefore even if wishing to rewrite only the value of the TTnCCR0 rewrite the same value to the TTnCCR1 register to make the next reload valid Figure 11 18 Basic Operation Flow for Reload Batch Rewrite Caution Rewrite to the TTnCCR1 register includes enabling reload Therefore rewrite the TTnCCR1 register after rewriting...

Page 486: ...erval mode Compare only Anytime write type External event count mode External trigger pulse output mode Compare only Reload type One shot pulse mode Compare only Anytime write type PWM mode Compare only Reload type Free running mode Capture compare selectable When compare is selected anytime write type Pulse width measurement mode Capture only Triangular wave PWM mode Compare only Reload type Enco...

Page 487: ... transferred to the TTnCCR1 buffer register and a compare match interrupt INTTTnCC1 is output The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method regardless of the value of bit TTnCE Pins TOTn0 and TOTn1 are toggle output controlled when bits TTnOE0 and TTnOE1 are set to 1 Figure 11 20 Basic Operation Flow in Interval Timer Mode Note In the case of a match between the...

Page 488: ...OTn1 are not output TTnOE0 1 0 TTnOL0 0 TTnOL1 1 Remarks 1 D1 D2 Setting values of TTnCCR0 register 0000H to FFFFH D3 Setting values of TTnCCR1 register 0000H to FFFFH 2 Interval time Dm 1 count clock cycle 3 m 1 to 3 n 0 1 Counter D1 D 2 INTTTnCC0 D1 D2 D1 FFFFH TTnCCR1 D3 D3 D3 INTTTnCC1 TTnCCR0 D3 TTnCE A Interval time D1 1 count clock A A B TOTn0 TOTn1 Low High A Interval time D2 1 count clock...

Page 489: ...n1 output performed TTnOE0 1 1 TTnOL0 0 TTnOL1 1 Remarks 1 D1 Setting value of TTnCCR0 register 0000H to FFFFH D2 Setting value of TTnCCR1 register 0000H to FFFFH 2 Interval time Dm 1 count clock cycle 3 TOTn0 TOTn1 toggle time Dm 1 count clock cycle 4 m 1 2 n 0 1 Counter D1 INTTTnCC0 D1 D2 FFFFH TTnCCR1 INTTTnCC1 TTnCCR0 D2 TTnCE D1 D2 D1 D2 Interval time Interval time Interval time TOTn0 TOTn1 ...

Page 490: ... only one compare register channel it is recommended to set the TTnCCR1 register to FFFFH External event count operation flow 1 TTnCTL1 register bits TTnMD3 to TTnMD0 0001B mode setting Edge detection set with TTnIOC2 register bits TTnEES1 and TTnEES0 TTnEES1 TTnEES0 setting other than 01B 2 TTnCTL0 register bit TTnCE 1 count enable 3 TEVTTn pin input edge detection count up start Cautions 1 In ex...

Page 491: ...Tn0 and TOTn1 are not output The signal input from TEVTTn and internally synchronized is counted as the count clock TTnOE1 0 TTnOL0 0 TTnOL1 1 Remarks 1 D1 D2 Setting values of TTnCCR0 register 0000H to FFFFH D3 Setting value of TTnCCR1 register 0000H to FFFFH 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter D1 D 2 INTTTnCC0 D1 D2 D1 FFFFH TTnCCR1 D3 D3 D3 INTTTnCC1 TTnCCR0 D3 TTnCE TOTn1 High ...

Page 492: ...CR0 and TTnCCR1 register values are not rewritten TOTn0 and TOTn1 are output TTnOE1 1 TTnOL0 0 TTnOL1 1 Remarks 1 D1 Setting value of TTnCCR0 register 0000H to FFFFH D2 Setting value of TTnCCR1 register 0000H to FFFFH 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter D1 INTTTnCC0 D1 D2 FFFFH TTnCCR1 INTTTnCC1 TTnCCR0 D2 TTnCE D1 D2 D1 D2 TO Tn1 TEVTTn ...

Page 493: ... When D1 D2 TTnCCR0 and TTnCCR1 register values are not rewritten TOTn0 and TOTn1 are output TTnOE1 1 TTnOL0 0 TTnOL1 1 Remarks 1 D1 Setting value of TTnCCR0 register 0000H D2 Setting value of TTnCCR1 register 0000H 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter 0000H INTTTnCC0 FFFFH TTnCCR1 INTTTnCC1 TTnCCR0 0000H TTnCE TO Tn1 0000H ...

Page 494: ...4 4 d When D1 D2 TTnCCR0 TTnCCR1 register values are not rewritten TOTn0 and TOTn1 are output TTnOE1 1 TTnOL0 0 TTnOL1 1 Remarks 1 D1 Setting value of TTnCCR0 register 0001H D2 Setting value of TTnCCR1 register 0000H 2 Number of event counts Dm 1 m 1 2 3 n 0 1 Counter INTTTnCC0 FFFFH TTnCCR1 INTTTnCC1 TTnCCR0 TTnCE TO Tn1 0001H 0001H 0000H ...

Page 495: ... reload is performed at the timing when the counter value and the TTnCCR0 register match However when write access to the TTnCCR1 register is performed the next reload timing becomes valid so that even if wishing to rewrite only the value of the TTnCCR0 register write the same value to the TTnCCR1 register In this case reload is not performed even if only the TTnCCR0 register is rewritten If durin...

Page 496: ...rnal trigger TTRGTn pin input Counter starts counting ITTTnCC0 occurrence Counter clear start Initial settings Timer operation enable TTnCE 1 Transfer of values of TTnCCR0 and TTnCCR1 to buffers TTnCCR0 and TTnCCR1 Match between counter and TTnCCR0 counter clear start External trigger TTRGTn pin input Clock selection TTnCTL1 TTnEEE 0 TTnCTL0 TTnCKS2 to TTnCKS0 External trigger pulse output mode se...

Page 497: ... 0000H to FFFFH D11 D12 Setting values of TTnCCR1 register 0000H to FFFFH 2 TOTn1 PWM duty setting value of TTnCCR1 register count clock cycle TOTn1 PWM cycle setting value of TTnCCR0 register 1 count clock cycle 3 Pin TOTn0 is toggled when the counter is cleared immediately following count start 4 n 0 1 Counter TTnCCR1 FFFFH TTnCCR0 buffer TTnCCR1 buffer TTnCCR0 TTnCE External trigger TTRGTn pin ...

Page 498: ...een the counter and TTnCCR1 buffer register a compare match interrupt INTTTnCC1 is output The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method regardless of the value of bit TTnCE Even if a trigger is input during the counter operation it is ignored Be sure to input the second trigger when the counter is stopped at 0000H In the one shot pulse mode registers TTnCCR0 and...

Page 499: ...r operation enable TTnCE 1 Transfer of values of TTnCCR0 and TTnCCR1 to buffers TTnCCR0 and TTnCCR1 Initial settings Clock selection TTnCTL1 TTnEEE 0 TTnCTL0 TTnCKS2 to TTnCKS0 One shot pulse mode setting TTnCTL1 TTnMD2 to TTnMD0 011 Compare register setting TTnCCR0 TTnCCR1 Trigger wait status counter in standby at FFFFH Trigger wait status counter in standby at 0000H External trigger TTRGTn pin i...

Page 500: ...egister 0000H to FFFFH D1 Setting value of TTnCCR1 register 0000H to FFFFH 2 TOTn1 output delay setting value of TTnCCR1 register count clock cycle TOTn1 output pulse width setting value of TTnCCR0 register 1 setting value of TTnCCR1 register count clock cycle 3 n 0 1 0000H Counter INTTTnCC0 FFFFH TTnCCR1 INTTTnCC1 TTnCCR0 TTnCE External trigger TTRGTn pin TOTn1 TTnEST D0 D0 D0 D1 D1 D1 D0 D1 Note...

Page 501: ...re register reload occurs upon a match between the counter value and the TTnCCR0 buffer register However since the next reload timing becomes valid when the TTnCCR1 register is written to write the same value to the TTnCCR1 register even when wishing to rewrite only the value of the TTnCCR0 register Reloading is not performed if only the TTnCCR0 register is rewritten In the PWM mode the TTnCCR0 an...

Page 502: ...er and TTnCCR1 buffer TOTn1 outputs low level Timer operation enable TTnCE 1 Transfer of value of TTnCCRm to TTnCCRm buffer Upon a match between counter and TTnCCR1 TOTn1 outputs low level TTnCCR0 rewrite TTnCCR1 rewrite Upon a match between counter and TTnCCR0 counter clear start and TOTn1 outputs high level 1 INTTTnCC1 occurrence INTTTnCC0 occurrence INTTTnCC1 occurrence Initial settings Clock s...

Page 503: ...D12 D13 Setting values of TTnCCR1 register 0000H to FFFFH 2 TOTn1 PWM duty setting value of TTnCCR1 register count clock cycle TOTn1 PWM cycle setting value of TTnCCR0 register 1 count clock cycle 3 TOTn0 is toggled immediately following counter start and at setting value of TTnCCR0 register 1 count clock cycle 4 n 0 1 Counter FFFFH TTnCCR1 TTnCCR0 TTnCE TOTn1 TTnCCR0 buffer TTnCCR1 buffer D00 D00...

Page 504: ...0 buffer register was not performed Held until the next reload timing Remarks 1 D00 D01 D02 D03 Setting values of TTnCCR0 register 0000H to FFFFH D10 D11 D12 D13 Setting values of TTnCCR1 register 0000H to FFFFH 2 The TOTn0 and TOTn1 pins become high level at timer count start 3 n 0 1 Counter FFFFH TTnCCR1 TTnCCR0 TTnCE TOTn1 TTnCCR0 buffer TTnCCR1 buffer D00 0000H D10 D11 D12 D12 D10 D11 D12 0000...

Page 505: ...CS0 0 TTnCCS1 1 TTnCCS0 1 TTnCCS1 1 TTnCCS0 1 Timer operation enable TTnCE 1 Transfer of values of TTnCCR0 and TTnCCR1 to TTnCCR0 and TTnCCR1 buffers Timer operation enable TTnCE 1 Transfer of value of TTnCCR1 to TTnCCR1 buffer Counter overflow Timer operation enable TTnCE 1 Transfer of value of TTnCCR0 to TTnCCR0 buffer Match between TTnCCR1 buffer and counter TITn0 edge detection capture of coun...

Page 506: ...d in the free running mode until TTnCE 0 is set Moreover during count operation a compare match interrupt INTTTnCC0 is output upon a match between the counter and TTnCCR0 buffer register and a compare match interrupt INTTTnCC1 is output upon a match between the counter and TTnCCR1 buffer register The TTnCCR0 and TTnCCR1 registers can be rewritten using the anytime write method regardless of the va...

Page 507: ...000H to FFFFH D10 D11 Setting values of TTnCCR1 register 0000H to FFFFH 2 TOTn0 toggle width setting value of TTnCCR0 register 1 count clock cycle 3 TOTn1 toggle width setting value of TTnCCR1 register 1 count clock cycle 4 Pins TOTn0 and TOTn1 become high level at count start 5 n 0 1 0000H Counter FFFFH TTnCCR1 TTnCCR0 TTnCE INTTTnCC1 D00 D00 D01 D11 D11 D10 D00 D01 D11 D10 INTTTnCC0 D00 D01 D10 ...

Page 508: ...rigger inter val is such that it includes two overflow occurrences 2 or more free running cycles Cautions 1 In free running mode the external event clock input TEVTTn is prohibited TTnCTL1 TTnEEE 0 2 When an internal count clock fXX 16 TTnCTL0 TTnCKS2 0 is selected in free running mode the TTnCCR0 and TTnCCR1 registers are used as capture regis ters the a value of FFFFH will be captured if a valid...

Page 509: ...e running mode the external event clock input TEVTTn is prohibited TTnCTL1 TTnEEE 0 2 When an internal count clock fXX 16 TTnCTL0 TTnCKS2 0 is selected in free running mode and TTnCCR0 register is used as capture register the a value of FFFFH will be captured if a valid signal edge is input before the first count up Figure 11 32 Basic Operation Timing in Free Running Mode Compare Capture Function ...

Page 510: ...Overflow flag When in the free running mode the counter overflows from FFFFH to 0000H the overflow flag TTnOVF is set to 1 and an overflow interrupt INTTTnOV is output The overflow flag is cleared through 0 write from the CPU The overflow flag is not cleared by just being read ...

Page 511: ...ment can be similarly performed by using the TTnCCR1 register Cautions 1 In the pulse width measurement mode the external event clock input TEVTTn is prohibited TTnCTL1 TTnEEE 0 2 When an internal count clock fXX 16 TTnCTL0 TTnCKS2 0 is selected in pulse width measurement mode and a valid signal edge is input before the first count up the a value of FFFFH will be captured in the corresponding TTnC...

Page 512: ...are match interrupt INTTTnCC1 is output Moreover upon counter underflow an overflow interrupt INTTTnOV is output The TTnCCR0 and TTnCCR1 registers can be rewritten during count operation Compare register reload occurs upon a match between the counter value and the TTnCCR0 buffer register However since the next reload timing becomes valid when the TTnCCR1 register is written to write the same value...

Page 513: ...EE3V1UD00 Figure 11 34 Basic Operation Timing in Triangular Wave PWM Mode a When TOTn0 TOTn1 are output TTnOE0 1 1 TTnOL0 1 0 Remark n 0 1 D00 D10 Counter FFFFH INTTTnCC0 TTnCE D00 TTnCCR0 0000H FFFFH TTnCCR1 0000H D10 D10 INTTTnCC1 D00 D10 D00 INTTTnOV TOTn0 TOTn1 ...

Page 514: ...output upon a match between the counter and TTnCCR0 register A compare match interrupt INTTTnCC1 is output upon a match between the counter and TTnCCR1 register 3 Counter clear operation Clearing of the counter to 0000H is performed under the following conditions Mode TTnCCR0 register TTnCCR1 register Encoder compare mode Compare only Compare only Clear Condition Method whereby counter is cleared ...

Page 515: ...the setting value of the TTnCCR0 register upon occurrence of counter underflow Bit TTnLDE is valid only when the TTnECm bit setting is 00B 01B in a mode where the TTnCCR0 or TTnCCR1 register is used as a compare only register In the case of all other settings bit TTnLDE is invalid even if manipulated As an example of the use of the encoder count function counter operation becomes possible between ...

Page 516: ...nt mode 1 Operation example TTnIOC3 TTnEIS3 to 2 TENCTn1 pin input Edge detection specification invalid TTnIOC3 TTnEIS1 to 0 10B TENCTn0 pin input Rising edge detection Figure 11 35 Encoder Count Function Up Down Count Selection Specification Timings 1 6 a Timing 1 Remarks 1 Counting is performed when the edges of the TENCTn0 TENCTn1 pin inputs overlap 2 n 0 1 A Phase Pin TENCTn0 B Phase Pin TENCT...

Page 517: ...t Selection Specification Timings 2 6 b Timing 2 Remarks 1 The count value is held when the edges of the TENCTn0 TENCTn1 pin inputs overlap 2 n 0 1 A Phase Pin TENCTn0 B Phase Pin TENCTn1 Count Low level Rising edge Down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge Low level Up Falling edge Both edges Rising edge High level Falling edge Both edges Simultaneous...

Page 518: ... 3 6 c Timing 3 Remark n 0 1 A Phase Pin TENCTn0 B Phase Pin TENCTn1 Count Low level Falling edge Hold Rising edge Low level Down High level Rising edge Hold Falling edge High level Rising edge High level High level Falling edge Falling edge Low level Up Low level Rising edge Hold Rising edge Rising edge Hold Falling edge Rising edge Rising edge Falling edge Down Falling edge Falling edge Up TENCT...

Page 519: ...Function Up Down Count Selection Specification Timings 4 6 d Timing 4 Remark n 0 1 A Phase Pin TENCTn0 B Phase Pin TENCTn1 Count Low level Falling edge Down Rising edge Low level High level Rising edge Falling edge High level Rising edge High level Up High level Falling edge Falling edge Low level Low level Rising edge Simultaneous pin TENCTn0 TENCTn1 inputs Hold TENCTn0 TENCTn1 Counter Up count D...

Page 520: ...Tn0 edge detection specification invalid Figure 11 35 Encoder Count Function Up Down Count Selection Specification Timings 5 6 e Timing 5 Remarks 1 The count value is held when the edges of the TENCTn0 TENCTn1 pin inputs overlap 2 n 0 1 TENCTn0 TENCTn1 Counter Up count Down count 04 03 05 06 07 08 07 06 05 Hold Up count 06 Up count ...

Page 521: ... TTnCCR0 register Operation is performed under the following conditions upon a match between the counter and TTnCCR1 register Caution In encoder compare mode TTnMD3 to TTnMD0 bits 1000B if the compare regis ters TTnCCR0 TTnCCR1 are set to the same value of TTnTCW register when TTnECC bit 0 the timer cannot perform the comparison with the compare registers TTnCCR0 TTnCCR1 and TTnTCW register which ...

Page 522: ...tion When TTnECM0 1 the counter is cleared to 0000H if the next count following a match between the counter and TTnCCR0 register is up count When TTnLDE 1 the setting value of the TTnCCR0 register is loaded to the counter upon underflow Therefore the setting value of the TTnCCR0 register is used as the maximum count value and count operation can be realized within 0000H TTnCCR0 register setting va...

Page 523: ...ugh detection of valid edge of TECRTn pin input TTnSCE 0 When TTnSCE 0 the counter is cleared to 0000H in synchronization with the internal operation clock upon detection of the valid edge set through TECRTn pin input edge detection specification At this time an encoder clear interrupt INTTTnEC is output When TTnSCE 0 the setting of bits TTnZCL TTnBCL and TTnACL are invalid Figure 11 36 Counter Cl...

Page 524: ...TTnECS0 are invalid Operation example When TTnSCE 1 TTnCLA 1 TTnCLB 0 TTnCLZ 1 TTnUDS 11B are set Clear condition level TECRTn pin High level TENCTn1 pin Low level TENCTn0 pin High level Figure 11 36 Counter Clearing to 0000H through Encoder Clear Input pin TECRTn Timings 2 4 b when TECRTn Pin Input Is Delayed from TENCTn1 Pin Input during Up Count Remark n 0 1 TENCTn0 TENCTn1 TECRTn H L 0 m m 1 T...

Page 525: ...Input Occurs Earlier Than TENCTn1 Pin Input During Up Count No miscount occurs due to TECRTn pin input delay because the clear condition is set according to the levels of pins TENCTn0 TENCTn1 and TECRTn and the counter is cleared to 0000H upon clear condition detection Remark n 0 1 TENCTn0 TENCTn1 TECRTn H L 0 m H Signal after edge detection Base clock Counter Count clock TENCTn0 TENCTn1 TECRTn H ...

Page 526: ...NCTn1 Pin Input During Down Count No miscount occurs due to the TECRTn pin input delay during down count similarly to during up count Remark n 0 1 TENCTn0 TENCTn1 TECRTn H L 0 m m 1 H m 1 TTnCCR0 0 TTnCCR1 INTTTnCC1 INTTTnCC0 m TTnCCR0 INTTTnCC0 Signal after edge detection When m 1 set to TTnCCR0 When 0000H set to TTnCCR1 Compare match interrupt not output When m set to TTnCR0 Base clock Counter C...

Page 527: ...etting value of the TTnTCW register Initial value 0000H of TTnTCW register b Count operation when TTnECC 1 is set Since the setting value of the TTnTCW register is not loaded to the counter the count operation is performed from initial value FFFFH As the initial operation it is recommended to set TTnECC 0 and load to the counter the value set to the TTnTCW register then start the count operation R...

Page 528: ... when setting value of bit TTnECC is rewritten 0 1 0 when TTnCE 1 2 When setting value of bit TTnECC is rewritten 1 0 1 while TTnCE 0 The counter is reset when the setting value of bit TTnECC is changed from 1 to 0 while TTnCE 0 Then when TTnECC 1 is set again and the value of bit TTnCE is changed from 0 to 1 counting restarts from the counter s initial value FFFFH without the setting value of the...

Page 529: ... rising edge of TENCTn0 and TENCTn1 pin inputs TTnIOC3 TTnSCE 0 TTnECS1 0 00B Valid edge detection clear no edge specified Since TTnUDS1 0 and TTnEIS1 0 that control the count operation are set to 00B and 01B rising edge detection respectively the counter is operated through detection of the phase of pin TENCTn1 upon detection of the rising edge of TENCTn0 pin input A compare match interrupt INTTT...

Page 530: ...the counter is operated through detection of the phase of pins TENCTn0 and TENCTn1 A compare match interrupt INTTTnCC0 is output upon a match between the counter value and the TTnCCR0 buffer register p A compare match interrupt INTTTnCC1 is output upon a match between the counter value and the TTnCCR1 buffer register q The counter is not cleared upon a match with the TTnCCR0 register or the TTnCCR...

Page 531: ...Valid edge detection clear no edge specified Since TTnUDS1 0 that control the count operation are set to 11B the counter is operated through detection of the phase of pins TENCTn0 and TENCTn1 A compare match interrupt INTTTnCC0 is output upon a match between the counter value and the TTnCCR0 buffer p At this time the counter is cleared to 0000H if the next count operation is up count A compare mat...

Page 532: ...n of TITn0 pin input serves as the reload timing During count operation a capture interrupt INTTTnCC0 is output upon capture to the TTnCCR0 register through TITn0 pin input and a compare match interrupt INTTTnCC1 is output upon a match between the counter and the TTnCCR1 register The TOTn0 pin becomes the level set with bit TTnOL0 If TTnOL0 0 a low level is output a and if TTnOL0 1 a high level is...

Page 533: ...buffer register even if this value is changed Pin TOTn1 is set when the counter is cleared to 0000H upon detection of the valid edge of pin TITn0 and it is reset upon a match between the counter value and the TTnCCR1 register Therefore pin TOTn1 remains high level if the valid edge of the TITn0 pin input is detected before a match with the TTnCCR1 register occurs XXXX i j k i j m n m n TTnCCR0 TTn...

Page 534: ...534 Chapter 11 16 bit Timer Event Counter T User s Manual U16580EE3V1UD00 ...

Page 535: ...ins corresponding to the capture compare register as the capture trigger Base clock fCLK fXX 4 fCLK 16 MHz fXX 64 MHz Count clocks selectable through division by prescaler 2 phase encoder input The 2 phase encoder signal from external is used as the count clock of the timer counter with the external clock input pins TIUD1 TCUD1 The counter mode can be selected from among the four following modes M...

Page 536: ...value b Up down counter mode The timer clear operation can be selected from among the following four conditions Timer clear performed upon occurrence of match with CM100 set value during TMENC10 up count operation and timer clear performed upon occurrence of match with CM101 set value during TMENC10 down count operation Timer clear performed only by external input Timer clear performed upon occurr...

Page 537: ...own below Remark fXX Internal system clock Table 12 1 Timer ENC10 Configuration List Timer Count Clock Register Read Write Generated Interrupt Signal Capture Trigger Timer ENC10 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 TMENC10 Read write INTOVF INTUDF CM100 Read write INTCM10 CM101 Read write INTCM11 CC100 Read write INTCC10 TICC10 CC101 Read write INTCC11 TICC11 ...

Page 538: ...CC11 pin or the interrupt from the TICC10 pin selected by the CSL bit of the CSL1 register Remark fXX Internal system clock 1 2 1 4 1 8 1 16 1 32 1 64 1 128 Edge detector Output control Selector Selector Edge detector Edge detector Edge detector Edge detector CLR1 CLR0 CM11 CM10 TMENC1 TM10 clear controller CC11 CC10 MSEL CMD TM1UBD ENMD ALVT1 RLEN TM1UDF TM1OVF Clear TCLR Internal bus Internal bu...

Page 539: ...ven during a count operation Figure 12 2 Timer ENC10 TMENC10 TMENC10 start and stop is controlled by the TM1CE bit of timer control register 10 TMC10 The TMENC10 operation consists of the following two modes a General purpose timer mode In the general purpose timer mode TMENC10 operates as a 16 bit interval timer free running timer or for PWM output Counting is performed based on the clock selecte...

Page 540: ... Timer ENC10 TMENC10 Clear Conditions Operation Mode TUM10 Register TMC10 Register TMENC10 Clear CMD Bit MSEL Bit ENMD Bit CLR1 Bit CLR0 Bit General purpose timer mode 0 0 0 Clearing not performed 1 Cleared upon match with CM100 set value UDC mode A 1 0 0 0 Cleared only by TCLR1 input 0 1 Cleared upon match with CM1n0 set value during up count operation 1 0 Cleared by TCLR1 input or upon match wit...

Page 541: ...imer mode CMD bit of TUM10 register 0 and UDC mode A MSEL bit of TUM10 register 0 an interrupt signal INTCM10 is always generated upon occurrence of a match In UDC mode B MSEL bit of TUM10 register 1 an interrupt signal INTCM10 is generated only upon occurrence of a match during up count operation This register can be read written in 16 bit units Reset input clears this register to 0000H Caution W...

Page 542: ...imer mode CMD bit of TUM10 register 0 and UDC mode A MSEL bit of TUM10 register 0 an interrupt signal INTCM11 is always generated upon occurrence of a match In UDC mode B MSEL bit of TUMn register 1 an interrupt signal INTCM11 is generated only upon occurrence of a match during down count operation This register can be read written in 16 bit units Reset input clears this register to 0000H Caution ...

Page 543: ...e may differ from the actual value If CC100 must be read twice be sure to read another register between the first and the second read operation Figure 12 5 Capture Compare Register 100 CC100 a When set as a capture register When CC100 is set as a capture register the valid edge of the corresponding external TICC10 signal is detected as the capture trigger TMENC10 latches the count value in synchro...

Page 544: ...e may differ from the actual value If CC101 must be read twice be sure to read another register between the first and the second read operation Figure 12 6 Capture Compare Register 101 CC101 a When set as a capture register When CC101 is set as a capture register the valid edge of the corresponding external TICC11 signal is detected as the capture trigger TMENC10 latches the count value in synchro...

Page 545: ...ose timer mode up count 1 UDC mode up down count TOE Timer Output TO1 Control 0 Timer output disabled 1 Timer output enabled When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE bit At this time timer output consists of the inverted phase level of the level set by the ALVT1 bit ALVT1 Active Level Specification for Timer Output TO1 0 Active level is high level ...

Page 546: ...RLEN Transfer Operation Control in UDC Mode A 0 Transfer operation from CM100 register to TMENC10 disabled 1 Transfer operation from CM100 register to TMENC10 enabled When RLEN 1 the value set to CM100 is transferred to TMENC10 upon occurrence of TMENC10 underflow When the CMD bit of the TUM10 register 0 general purpose timer mode the RLEN bit settings are invalid and a transfer operation is not e...

Page 547: ...ENC10 count value and CM100 set value 1 1 No clearing Clearing by match of the TMENC10 count value and CM100 set value is valid only during TMENC10 up count operation TMENC10 is not cleared during TMENC10 down count operation When the CMD bit of the TUM10 register 0 general purpose timer mode the CLR1 and CLR0 bit settings are invalid When the MSEL bit of the TUM10 register 1 UDC mode B the CLR1 a...

Page 548: ...and shared with the external capture input pin TICC11 Therefore in the UDC mode the external capture function cannot be used 3 The TCLR1 pin is used for the UDC mode and alternately shared with the external capture input pin TICC10 Therefore when the TCLR1 input is used in UDC mode A the external capture function cannot be used Figure 12 9 Capture Compare Control Register 10 CCR10 After reset 00H ...

Page 549: ...een set an illegal interrupt incorrect counting and incorrect clearing may occur depending on the timing of setting the PM10 and PMC10 registers Figure 12 10 Signal Edge Selection Register 10 SESA10 1 2 After reset 00H R W Address FFFFF6BDH 7 6 5 4 3 2 1 0 SESA10 TESUD1 TESUD0 CESUD1 CESUD0 IES111 IES110 IES101 IES100 TIUD TCUD1 TCLR1 TICC11 capture trigger TICC10 capture trigger TESUD1 TESUD0 Val...

Page 550: ... 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges A valid edge on the TICC11 pin triggers the capture register CC101 Simultaneously an interrupt INTCC11 is generated IES101 IES100 Valid Edge Specification of TICC10 Capture Trigger Input Pin 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges A valid edge on the TICC10 pin triggers the c...

Page 551: ...f the TUM10 register 1 UDC mode setting the values of the PRM2 to PRM0 bits to 000B 001B 010B and 011B is prohibited 3 When TMENC10 is in mode 4 specification of the valid edge for the TIUD1 and TCUD1 pins is invalid Figure 12 11 Prescaler Mode Register 10 PRM10 Remark fXX Internal system clock a In general purpose timer mode CMD bit 0 The count clock is fixed to the internal clock The clock rate ...

Page 552: ...ation Mode TMENC10 Operation Mode 1 Down count when TCUD1 high level Up count when TCUD1 low level Mode 2 Up count upon detection of valid edge of TIUD1 input Down count upon detection of valid edge of TCUD1 input Mode 3 Automatic judgment by TCUD1 input level upon detection of valid edge of TIUD1 input Mode 4 Automatic judgment upon detection of both edges of TIUD1 input and both edges of TCUD1 i...

Page 553: ...DF TMENC10 Underflow Flag 0 No TMENC10 count underflow 1 TMENC10 count underflow The TM1UDF bit is cleared 0 upon completion of read access to the STATUS10 register from the CPU TM1OVF TMENC10 Overflow Flag 0 No TMENC10 count overflow 1 TMENC10 count overflow The TM1OVF bit is cleared 0 upon completion of read access to the STATUS10 register from the CPU TM1UBD TMENC10 Up Down Counter Operation St...

Page 554: ... s CMD bit 1 MSEL bit 0 The TMENC10 clear source can be selected as external clear input TCLR1 the internal signal indicating a match between the TMENC10 count value and the CM100 set value during an up count operation or the logical sum OR of the two signals using the CLR1 and CLR0 bits of the TMC10 register TMENC10 can transfer reload the value of CM100 upon occurrence of TMENC10 underflow when ...

Page 555: ...MC register to 1 2 Free running operation TMENC10 performs full count operation from 0000H to FFFFH and after the TM1OVF bit of the STATUS10 register is set 1 TMENC10 is cleared and resumes counting The free running cycle can be calculated by the following formula Free running cycle 65 536 TMENC10 count clock rate Caution The free running operation can be achieved by setting the ENMD bit of the TM...

Page 556: ...ing edge and the falling edge are selected as the capture triggers it is possible to measure the input pulse width from external If a single edge is selected as the capture trigger the input pulse cycle can be measured 5 PWM output operation PWM output operation is performed from the TO1 pin by setting TMENC10 to the general purpose timer mode CMD bit of the TUM10 register 0 The resolution is 16 b...

Page 557: ...next count clock after the match The required PWM output duty is set by using the compare register CM101 Figure 12 14 PWM Signal Output Example When ALVT10 Bit 0 Is Set Cautions 1 Changing the values of the CM100 and CM101 registers is prohibited during TMENC10 operation TM1CE bit of TMC10 register 1 2 Changing the value of the ALVT1 bit of the TUM register is prohibited during TMENC10 operation 3...

Page 558: ...e value of CM100 upon occurrence of TMENC10 underflow when the RLEN bit of the TMC10 register is set 1 UDC mode B TUMn register s CMD bit 1 MSEL bit 1 The status of TMENC10 after match of the TMENC10 count value and CM100 set value is as follows 1 In case of an up count operation TMENC10 is cleared 0000H and the INTCM10 interrupt is generated 2 In case of a down count operation the TMENC10 count v...

Page 559: ... operations are performed based on the level of the TCUD1 pin upon detection of the valid edge of the TIUD1 pin TMENC10 down count operation when TCUD1 pin high level TMENC10 up count operation when TCUD1 pin low level Figure 12 15 Mode 1 When Rising Edge Is Specified as Valid Edge of TIUD1 Pin Figure 12 16 Mode 1 When Rising Edge Is Specified as Valid Edge of TIUD1 Pin In Case of Simultaneous TIU...

Page 560: ...tection of valid edge of TIUD1 pin TMENC10 down count upon detection of valid edge of TCUD1 pin Caution If the count clock is simultaneously input to the TIUD1 pin and the TCUD1 pin count operation is not performed and the immediately preceding value is held Figure 12 17 Mode 2 When Rising Edge Is Specified as Valid Edge of TIUD1 TCUD1 Pins 0006H TIUD1 TCUD1 TMENC1 0007H 0008H Up count Hold value ...

Page 561: ...e TCUD1 pin level sampled at the valid edge timing of the TIUD1 pin is low TMENC10 counts down If the TCUD1 pin level sampled at the valid edge timing of the TIUD1 pin is high TMENC10 counts up Figure 12 18 Mode 3 When Rising Edge Is Specified as Valid Edge of TIUD1 Pin Figure 12 19 Mode 3 When Rising Edge Is Specified as Valid Edge of TIUD1 Pin In Case of Simultaneous TIUD1 TCUD1 Pin Edge Timing ...

Page 562: ... and falling edges of the two signals input to the TIUD1 and TCUD1 pins Therefore TMENC10 counts four times per cycle of an input signal 4 count Figure 12 20 Mode 4 Cautions 1 When mode 4 is specified as the operation mode of TMENC10 the valid edge specifications for pins TIUD1 and TCUD1 are not valid 2 If the TIUD1 pin edge and TCUD1 pin edge are input simultaneously in mode 4 TMENC10 continues t...

Page 563: ... be combined with the transfer operation b Transfer operation The operations at the next count clock after the count value of TMENC10 becomes 0000H during TMENC10 count down operation are as follows In case of down count operation The data held in CM100 is transferred In case of up count operation The TMENC10 count value is incremented 1 Remarks 1 Transfer enable disable can be set with the RLEN b...

Page 564: ...mode a capture interrupt INTCC10 INTCC11 is generated upon detection of the valid edge 4 Operation in UDC mode B a Basic operation The operations at the next count clock after the count value of TMENC10 and the CM100 set value match when TMENC10 is in UDC mode B are as follows In case of up count operation TMENC10 is cleared 0000H and the INTCM10 interrupt is generated In case of down count operat...

Page 565: ...ring up count operation INTCM11 only during down count operation INTCC10Note INTCC11Note is output Note This match interrupt is generated when CC100 and CC101 are set to the compare register mode c Capture function TMENC10 connects two capture compare register CC100 CC101 channels When CC100 and CC101 are set to the capture register mode the value of TMENC10 is captured in synchronization with the...

Page 566: ...M101 Figure 12 23 Clear Operation upon Match with CM100 During TMENC10 Up Count Operation Remark Items between parentheses in the above figure apply to down count operation Figure 12 24 Clear Operation upon Match with CM101 during TMENC10 Down Count Operation Remark Items between parentheses in the above figure apply to up count operation Count clock rising edge set as valid edge CM10 FFFEH Clear ...

Page 567: ...e figure apply to down count operation 12 6 3 Transfer operation The internal operation during TMENC10 transfer operation is as follows Figure 12 26 Internal Operation During Transfer Operation Caution The count operations after the TMENC10 count value becomes 0000H are as follows In case of down count Transfer operation is performed In case of up count Transfer operation is not performed Remark I...

Page 568: ...ration Mode set to General Purpose Timer Mode and Count Clock Set to fXX 8 Remark fCLK Base clock An interrupt signal such as illustrated in Figure 12 27 is output at the next count following match of the TMENC10 count value and the set value of a corresponding compare register 12 6 5 TM1UBD flag bit 0 of STATUS register operation In the UDC mode CMD bit of TUM register 1 the TM1UBD flag changes a...

Page 569: ...n Interrupt request signal INTBRG2 13 2 Configuration The AFO function includes the following hardware Table 13 1 AFO Configuration Figure 13 1 Block Diagram of Auxiliary Frequency Output Function Item Configuration Control registers Prescaler mode registers 2 PRSM2 Prescaler compare registers 2 PRSCM2 AFO INTBRG2 PRSCM2 8 bit Counter Output Control fXX f 2 XX f 4 XX f 8 XX ...

Page 570: ...nits Reset input clears this register to 00H Figure 13 2 Prescaler Mode Register 2 PRSM2 Cautions 1 Do not rewrite the PRSM2 register during operation 2 Set the BGCS21 BGCS20 bits before setting the BGCE2 bit to 1 After reset 00H R W Address FFFFFDE0H 7 6 5 4 3 2 1 0 PRSM2 0 0 BGCE2 0 0 BGCS21 BGCS20 BGCE2 Baud Rate Generator Output Control 0 Disabled 1 Enabled BGCS21 BGCS20 Baud Rate Generator Cl...

Page 571: ...setting the BGCE2 bit of the PRSM2 register to 1 3 Do not set the AFO clock to a higher frequency than 8 MHz Remark fBGCS2 Clock frequency selected by the BGCS21 BGCS20 bits of the PRSM2 register After reset 00H R W Address FFFFFDE1H 7 6 5 4 3 2 1 0 PRSCM2 PRSCM27 PRSCM26 PRSCM25 PRSCM24 PRSCM23 PRSCM22 PRSCM21 PRSCM20 PRSCM 27 PRSCM 26 PRSCM 25 PRSCM 24 PRSCM 23 PRSCM 22 PRSCM 21 PRSCM 20 AFO Clo...

Page 572: ...e baud rate generated from the main clock is obtained by the following equation Remarks 1 fAFO AFO clock 2 fBGCS2 Clock frequency selected by the BGCS21 BGCS20 bits of the PRSM2 register 3 fXX Main clock oscillation frequency 4 k PRSM2 register setting value 2 k 5 5 N PRSCMm register setting value 1 to 255 when PRSCM2 01H to FFH or N 256 when PRSCM2 00H 13 4 3 Interval timer function The AFO funct...

Page 573: ...00 to ANI09 ANI10 to ANI19 10 bit resolution On chip A D conversion result register ADCRn0 to ADCRn9 10 bits 10 A D conversion trigger mode A D trigger mode Timer trigger mode External trigger mode Successive approximation method DMA transfer support of A D conversion result to internal RAM Remark n 0 1 ...

Page 574: ...egister nH ADCRnmH n 0 1 m 0 to 9 ADCRnm is a 10 bit register that holds A D conversion results Each time A D conversion is completed the conversion results are loaded from the successive approximation register SAR RESET input makes this register undefined 6 A D conversion result register for DMA transfer ADDMAn n 0 1 ADDMAn is a 16 bit register that holds the last 10 bit A D conversion result and...

Page 575: ...oftware processing is shown below Take the average result of a number of A D conversions and use that as the A D conversion result Execute a number of A D conversions consecutively and use those results omitting any exceptional results that may have been obtained 2 Do not apply a voltage outside the AVSSn to AVREFn range to the pins that are used as A D converter input pins Successive approximatio...

Page 576: ... without clearing the ADCEn bit the trigger input standby state is set immediately after changing the register 2 Changing the setting of the BSn and MSn bits is prohibited while A D conversion is enabled ADCEn bit 1 3 When data is written to the ADMn0 register during an A D conversion operation the conversion operation is initialized and conversion is executed from the beginning Figure 14 2 A D Co...

Page 577: ...egister during an A D conversion operation the conversion operation is initialized and conversion is executed from the beginning Figure 14 3 A D Converter n Mode Register 1 ADMn1 1 2 Remark n 0 1 After reset 00H R W Address ADM01 FFFFF201H ADM11 FFFFF241H 7 6 5 4 3 2 1 0 ADMn1 EGAn1 EGAn0 TRGn1 TRGn0 FRn3 FRn2 FRn1 FRn0 n 0 1 EGAn1 EGAn0 Valid Edge Specification of External Trigger Input ADTRGn 0 ...

Page 578: ...me FRn3 to FRn0 bits during an A D conversion operation ADCEn bit 1 To change the value clear the ADCEn bit to 0 2 When the trigger mode TRGn1 and TGRn0 bits is changed midway A D conversion can be started immediately without having to secure the A D stabilization time by re setting the ADCE bit to 1 Remarks 1 fXX Main clock 2 n 0 1 FRn3 FRn2 FRn1 FRn0 Number of conversion clocks Conversion Operat...

Page 579: ...data is written to the ADMn2 register during an A D conversion operation the conversion operation is initialized and conversion is executed from the beginning Figure 14 4 A D Converter n Mode Register 2 ADMn2 Remark n 0 1 After reset 00H R W Address ADM01 FFFFF201H ADM11 FFFFF241H 7 6 5 4 3 2 1 0 ADMn2 0 0 0 0 ANISn3 ANISn2 ANISn1 ANIn0 n 0 1 ANISn ANISn ANISn ANISn Specification of Analog Input P...

Page 580: ...etting of the ADTRSELn register is changed while A D conversion is enabled ADCEn bit 1 Figure 14 5 A D Converter n Trigger Source Select Register ADTRSELn Remark n 0 1 After reset 00H R W Address ADTRSEL0 FFFFF270H ADTRSEL1 FFFFF272H 7 6 5 4 3 2 1 0 ADTRSELn 0 0 0 0 TSELn3 TSELn2 TSELn1 TSELn0 n 0 1 TSELn3 TSELn2 TSELn2 TSELn0 Trigger Source Selection in Timer Trigger Mode 0 0 0 0 None All trigger...

Page 581: ...n9H Remark n 0 1 m 0 to 9 After reset Undefined R Address ADCR00 FFFFF210H ADCR10 FFFFF250H ADCR01 FFFFF212H ADCR11 FFFFF252H ADCR02 FFFFF214H ADCR12 FFFFF254H ADCR03 FFFFF216H ADCR13 FFFFF256H ADCR04 FFFFF218H ADCR14 FFFFF258H ADCR05 FFFFF21AH ADCR15 FFFFF25AH ADCR06 FFFFF21CH ADCR16 FFFFF25CH ADCR07 FFFFF21EH ADCR17 FFFFF25EH ADCR08 FFFFF220H ADCR18 FFFFF260H ADCR09 FFFFF222H ADCR19 FFFFF262H 15...

Page 582: ...14 7 shows the relationship between the analog input voltage and the A D conversion results Remark n 0 1 m 0 to 9 Table 14 1 Assignment of A D Conversion Result Registers to Analog Input Pins Analog Input Pin Assignment of A D Conversion Result Registers Select 1 Buffer Mode Scan Mode Select 4 Buffer Mode ANIn0 ADCRn0 ADCRn0H ADCRn0 to ADCRn3 ADCRn0H to ADCRn3H ANIn1 ADCRn1 ADCRn1H ANIn2 ADCRn2 AD...

Page 583: ...re 14 7 Relationship Between Analog Input Voltage and A D Conversion Results Remark n 0 1 m 0 to 9 1023 1022 1021 3 2 1 0 Input voltage AVREF 1 2048 1 1024 3 2048 2 1024 5 2048 2048 2048 2048 3 1024 1024 1024 2043 1022 2045 1023 2047 1 A D conversion results ADCRnm ...

Page 584: ...nsured Figure 14 8 A D Conversion Result Registers n0 to n9 n0H to n9H ADCRn0 to ADCRn9 ADCRn0H to ADCRn9H Remark n 0 1 After reset Undefined R Address ADDMA0 FFFFF224H ADDMA1 FFFFF264H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDMAn ADDMA n9 ADDMA n8 ADDMA n7 ADDMA n6 ADDMA n5 ADDMA n4 ADDMA n3 ADDMA n2 ADDMA n1 ADDMA n0 0 0 0 0 0 ODFn ADDMAn9 to ADDMAn0 A D Conversion Result for DMA Transfer 000H t...

Page 585: ...n of the 10 bits ends the conversion results are stored in the ADCRnm register When A D conversion has been performed the specified number of times the A D conversion end interrupt INTADn is generated n 0 1 m 0 to 9 Notes 1 If the setting of the ADMn0 ADMn1 or ADMn2 registers n 0 1 is changed during A D conversion the operation immediately before is stopped and the result of the conversion is not ...

Page 586: ...ecuted from the beginning again b Timer trigger mode This mode specifies the conversion timing of the analog input set for the ANIn0 to ANIn9 pins using signals from the inverter timer R TMR0 TMR1 The ADTRSELn register specifies the analog input conversion timing by selecting either one of the A D converter trigger signals TR0ADTRG0 TR0ADTRG1 TR1ADTRG0 TR1ADTRG1 or one of the top and bottom revers...

Page 587: ...rom the beginning again 2 Operation mode There are two operation modes that set the ANIn0 to ANIn9 pins select mode and scan mode The select mode has sub modes that consist of 1 buffer mode and 4 buffer mode These modes are set by the BSn and MSn bits of the ADMn0 register a Select mode In this mode one analog input specified by the ADMn2 register is A D converted The conversion results are stored...

Page 588: ...ta 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANIn1 Data 2 ANIn1 Data 3 ANIn1 Data 4 ANIn1 Data 5 ANIn1 ADCRn1 register INTADn interrupt Conversion start ADMn0 register setting ADCEn bit set ADCEn bit set ADCEn bit set ADCEn bit set Conversion start ADMn0 register setting ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn8 ANIn9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn7 ADCRn8 ADC...

Page 589: ... next conversion operation is repeated unless the ADCEn bit of the ADM0 register is cleared to 0 Figure 14 10 Select Mode Operation Timing 4 Buffer Mode ANIn2 Remark n 0 1 m 0 to 9 ANIn2 input A D conversion Data 1 ANIn2 Data 2 ANIn2 Data 3 ANIn2 Data 4 ANIn2 Data 5 ANIn2 Data 6 ANIn2 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANIn2 ADCRn0 Data 2 ANIn2 ADCRn1 Data 3 ANIn2 ADCRn2 Data 4 ANIn2...

Page 590: ...ADCEn bit of the ADMn0 register is cleared to 0 Figure 14 11 Scan Mode Operation Timing 4 Channel Scan ANI0 to ANI3 Remark n 0 1 m 0 to 9 ANIn3 input ANIn0 input ANIn1 input ANIn2 input A D conversion Data 1 ANIn0 Data 2 ANIn1 Data 3 ANIn2 Data 4 ANIn3 Data 5 ANIn0 Data 6 ANIn1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANIn0 ADCR0 Data 2 ANIn1 ADCR1 Data 3 ANIn2 ADCR2 Data 4 ANIn3 ADCR3 Dat...

Page 591: ...nd one to one Each time an A D conversion is executed an A D conversion end interrupt INTAD is generated and A D conversion ends The next conversion operation is repeated unless the ADCE bit of the ADM0 register is cleared to 0 Table 14 3 Correspondence Between Analog Input Pins and ADCRnm Register A D Trigger Select 1 Buffer This mode is most appropriate for applications in which the results of e...

Page 592: ...n is stopped The next conversion operation is repeated unless the ADCEn bit of the ADMn0 register is cleared to 0 Table 14 4 Correspondence Between Analog Input Pins and ADCRnm Register A D Trigger Select 4 Buffers This mode is suitable for applications in which the average of the A D conversion results is calcu lated Analog Input A D Conversion Result Register ANI0 to ANI3 ADCRn0 1st time ADCRn1 ...

Page 593: ... register 4 ANIn3 is A D converted 5 The conversion result is stored in ADCRn1 register 6 ANIn3 is A D converted 7 The conversion result is stored in ADCRn2 register 8 ANIn3 is A D converted 9 The conversion result is stored in ADCRn3 register 10 The INTAD interrupt is generated Remark n 0 1 m 0 to 9 ADCRn8 ADCRn9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn7 ANIn0 ANIn1 ANIn2 ANIn3 ANIn...

Page 594: ...f all the specified analog input ends the A D conversion end interrupt INTADn is generated and A D conversion is stopped The next conversion operation is repeated unless the ADCEn bit of the ADMn0 register is cleared to 0 Table 14 5 Correspondence Between Analog Input Pins and ADCRnm Register A D Trigger Scan Note Set by the ANISn3 to ANISn0 bits of the ADMn2 register This mode is most appropriate...

Page 595: ...in ADCRn1 6 ANIn2 is A D converted 7 The conversion result is stored in ADCRn2 8 ANIn3 is A D converted 9 The conversion result is stored in ADCRn3 10 ANIn4 is A D converted 11 The conversion result is stored in ADCRn4 12 ANIn5 is A D converted 13 The conversion result is stored in ADCRn5 14 The INTAD interrupt is generated Remark n 0 1 m 0 to 9 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn...

Page 596: ...event signal occurs during conversion the conversion operation is executed from the beginning again If data is written to the ADMn0 to ADMn2 registers during conversion the conversion operation is stopped and executed from the beginning again 14 6 1 Select mode operation In this mode an analog input ANIn0 to ANIn9 specified by the ADMn2 register is A D converted The conversion results are stored i...

Page 597: ...generated 3 ANIn1 is A D converted 4 The conversion result is stored in ADCRn1 5 The INTADn interrupt is generated Remark n 0 1 Trigger Analog Input A D Conversion Result Register Timer event signal TR0ADTRG0 TR0ADTRG1 TR1ADTRG0 TR1ADTRG1 INTTR0CD INTR0OD INTTR1CD INTTR1OD ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ANIn7 ADCRn7 ANIn8 ADCRn8 ANIn9 ADC...

Page 598: ...er conversion has finished the next conversion is repeated when a timer event signal is generated unless the ADCEn bit of the ADMn0 register is cleared to 0 This mode is suitable for applications in which the average of the A D conversion results is calculated Table 14 7 Correspondence Between Analog Input Pins and ADCRnm Register 4 Buffer Mode Timer Trigger Select 4 Buffers Remark n 0 1 m 0 to 9 ...

Page 599: ...d 4 The conversion result is stored in ADCR0 5 ANIn3 is A D converted 6 The conversion result is stored in ADCR1 7 ANIn3 is A D converted 8 The conversion result is stored in ADCR2 9 ANIn3 is A D converted 10 The conversion result is stored in ADCR3 11 The INTADn interrupt is generated Remark n 0 1 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn8 ANIn9 TR0ADTRG0 ADCRn0 ADCRn1 ADCRn2 ADCRn3 AD...

Page 600: ...finished the A D converter waits for a trigger unless the ADCEn bit of the ADMn0 register is cleared to 0 When a timer event occurs again the converter starts A D conversion again starting from the ANIn0 input This mode is most appropriate for applications in which multiple analog inputs are constantly monitored Table 14 8 Correspondence Between Analog Input Pins and ADCRnm Register Scan Mode Time...

Page 601: ...CRn0 5 ANIn1 is A D converted 6 The conversion result is stored in ADCRn1 7 ANIn2 is A D converted 8 The conversion result is stored in ADCRn2 9 ANIn3 is A D converted 10 The conversion result is stored in ADCRn3 11 ANIn4 is A D converted 12 The conversion result is stored in ADCRn4 13 The INTADn interrupt is generated Remark n 0 1 A D converter ADCn ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7...

Page 602: ...ns In this mode one analog input ANIn0 to ANIn9 specified by the ADMn2 register is A D converted The conversion results are stored in the ADCRnm register corresponding to the analog input In the select mode there are two select modes 1 buffer mode and 4 buffer mode according to the storing method of the conversion results 1 1 buffer mode external trigger select 1 buffer In this mode one analog inp...

Page 603: ...DCEn bit of ADMn0 is set to 1 enable 2 The external trigger is generated 3 ANIn1 is A D converted 4 The conversion result is stored in ADCRn1 5 The INTADn interrupt is generated Remark n 0 1 m 0 to 9 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn8 ANIn9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn8 ADCRn9 ADCRn7 A D converter ADCn ADTRGn ...

Page 604: ...Correspondence Between Analog Input Pins and ADCRnm Register External Trigger Select 4 Buffers While the ADCEn bit of the ADMn0 register is 1 A D conversion is started when a trigger is input from the ADTRGn pin This mode is suitable for applications in which the average of the A D conversion results is calcu lated Trigger Analog Input A D Conversion Result Register ADTRGn signal ANI0 to ANI3 ADCR...

Page 605: ...The conversion result is stored in ADCR0 5 ANIn3 is A D converted 6 The conversion result is stored in ADCR1 7 ANIn3 is A D converted 8 The conversion result is stored in ADCR2 9 ANIn3 is A D converted 10 The conversion result is stored in ADCR3 11 The INTADn interrupt is generated Remark n 0 1 m 0 to 9 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn8 ANIn9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ...

Page 606: ...ster is cleared to 0 after end of conversion the A D converter waits for a trigger The converter starts A D conversion from the ANIn0 input when a trigger is input to the ADTRGn pin again Table 14 11 Correspondence Between Analog Input Pins and ADCRnm Register External Trigger Scan When a trigger is input to the ADTRGn pin while the ADCEn bit of the ADMn0 register is 1 A D conversion is started ag...

Page 607: ... The conversion result is stored in ADCRn0 5 ANIn1 is A D converted 6 The conversion result is stored in ADCRn1 7 ANIn2 is A D converted 8 The conversion result is stored in ADCRn2 9 ANIn3 is A D converted 10 The conversion result is stored in ADCRn3 11 The INTADn interrupt is generated Remark n 0 1 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 ANIn8 ANIn9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCR...

Page 608: ... 2 Releasing HALT mode on page 258 the ADMn0 ADMn1 and ADMn2 registers as well as the ADCRnm register hold the value n 0 1 m 0 to 9 4 Input range of ANIn0 to ANIn9 Use the input voltage at ANIn0 to ANIn9 within the specified range If a voltage outside the range of AVREF is input to any of these pins even within the absolute maximum rating range the converted value of the channel is undefined In ad...

Page 609: ...errupt INTUCnRE Reception complete interrupt INTUCnR Transmission enable interrupt INTUCnT Character length 7 8 bits Parity function Odd even 0 none Transmission stop bit 1 2 bits On chip dedicated baud rate generator MSB LSB first transfer selectable Transmit receive data level inversion possible 13 to 20 bits selectable for the SBF Sync Break Field in the LIN Local Interconnect Network communica...

Page 610: ... reset to 0 by reading the UCnSTR register 7 UARTCn status register 1 UCnSTR1 The UCnSTR1 register indicates the operating status during a reception 8 UARTCn receive shift register This is a shift register used to convert the serial data input to the RXDCn pin into parallel data Upon reception of 1 byte of data and detection of the stop bit the receive data is transferred to the UCnRX register Thi...

Page 611: ...the transmission enable interrupt INUCnT is generated Figure 15 1 Block Diagram of Asynchronous Serial Interface n Remarks 1 n 0 1 2 fXX Internal system clock Internal bus Internal bus UCnOTP0 UCnOTP1 UCnCTL0 UCnSTR UCnSTR1 UCnCTL1 UCnCTL2 Receive shift register UCnRX Filter Selector UCnTX Transmit shift register Transmission controller Reception controller Selector Baud rate generator Baud rate g...

Page 612: ...ntrol and UARTCn asynchronous reset are performed with the UCnPWR bit The TXDCn pin output is fixed to high level by setting the UCnPWR bit to 0 UCnTXE Transmission Operation Enable 0 Stops transmission operation 1 Enables transmission operation The TXDCn pin output is fixed to high level by setting the UCnPWR bit to 0 Since the UCnTXE bit is initialized by the operating clock to initialize the tr...

Page 613: ... 0 parity 1 0 Odd parity output Odd parity check 1 1 Even parity output Even parity check These bits can be rewritten only when UCnPWR bit 0 or UCnTXE bit UCnRXE bit 0 If Reception with 0 parity is selected during reception a parity check is not performed Therefore since the UCnPE bit of the UCnSTA0 register is not set no error interrupt is output When transmission and reception are performed in t...

Page 614: ...s this register to 00H Figure 15 3 UARTCn Control Register 1 UCnCTL1 Remark fXX Internal system clock After reset 00H R W Address UC0CTL1 FFFFFA01H UC1CTL1 FFFFFA21H 7 6 5 4 3 2 1 0 UCnCTL1 0 0 0 0 UCnCKS3 UCnCKS2 UCnCKS1 UCnCKS0 n 0 1 UCnCKS3 UCnCKS2 UCnCKS1 UCnCKS0 Base clock fXCLK selection 0 0 0 0 fXX 2 0 0 0 1 fXX 4 0 0 1 0 fXX 8 0 0 1 1 fXX 16 0 1 0 0 fXX 32 0 1 0 1 fXX 64 0 1 1 0 fXX 128 0 ...

Page 615: ...CnCTL2 Remark fXCLK Clock frequency selected by the UCnCKS3 to UCnCKS0 bits of the UCnCTL1 register After reset FFH R W Address UC0CTL2 FFFFFA02H UC1CTL2 FFFFFA22H 7 6 5 4 3 2 1 0 UCnCTL2 UCnBRS7 UCnBRS6 UCnBRS5 UCnBRS4 UCnBRS3 UCnBRS2 UCnBRS1 UCnBRS0 n 0 1 UCn BRS7 UCn BRS6 UCn BRS5 UCn BRS4 UCn BRS3 UCn BRS2 UCn BRS1 UCn BRS0 Default k Serial clock 0 0 0 0 0 0 Setting prohibited 0 0 0 0 0 1 0 0 ...

Page 616: ... Also upon normal end of SBF reception 1 During SBF reception SBF Sync Brake Field reception is judged during LIN communication The UCnSRF bit is held high when a SBF reception error occurs and then SBF reception is started again UCnSRT SBF Reception Trigger 0 1 SBF reception trigger This is the SBF reception trigger bit during LIN communication and when read 0 is always read For SBF reception set...

Page 617: ... register is 0 or when the UCnRXE bit of the UCnCTL0 register is 0 UCnTDL Transmit Data Level 0 Normal output of transfer data 1 Inverted output of transfer data The value of the TXDCn pin can be inverted using the UCnTDL bit This bit can be set when the UCnPWR bit of the UCnCTL0 register is 0 or when the UCnTXE bit of the UCnCTL0 register is 0 UCnRDL Receive Data Level 0 Normal input of transfer ...

Page 618: ...et 00H R W Address UC0OPT1 FFFFFA0AH UC1OPT1 FFFFFA2AH 7 6 5 4 3 2 1 0 UCnOPT1 0 0 0 0 0 0 0 UCnEBE n 0 1 UCnEBE Extension Bit Operation Enable 0 Extension bit operation disabled Transfer data length set by UCnCL bit of the UCnCTL0 register 1 Extension bit operation enabled During extension bit operation a 9 th data bit is sent or received instead of the parity bit Extension bit operation is only ...

Page 619: ... UCnSL D0 D6 D7 D8 D9 D10 0 0 0 0 0 Data Stop 0 1 Data Stop Stop 1 0 Data Data Stop 1 1 Data Data Stop Stop other than 00B 0 0 Data Parity Stop 0 1 Data Parity Stop Stop 1 0 Data Data Parity Stop 1 1 Data Data Parity Stop Stop 1 0 0 0 0 Data Stop 0 1 Data Stop Stop 1 0 Data Data DataNote Stop 1 1 Data Data DataNote Stop Stop other than 00B 0 0 Data Parity Stop 0 1 Data Parity Stop Stop 1 0 Data Da...

Page 620: ...TR FFFFFA04H UC1STR FFFFFA24H 7 6 5 4 3 2 1 0 UCnSTR UCnTSF 0 0 0 0 UCnPE UCnFE UCnOVE n 0 1 UCnTSF Transfer Status Flag 0 When UCnPWR bit of UCnCTL0 register 0 or UCnTXE bit of UCnCTL0 register 0 has been set When following transfer completion there was no next data transfer from UCnTX 1 Write to UCnTXB bit The UCnTSF bit is always 1 when performing continuous transmission When initializing the t...

Page 621: ...but it can only be cleared by writing 0 to it and it cannot be set by writing 1 to it When 1 is written to this bit the hold status is entered UCnOVE Overrun Error Flag 0 When UCnPWR bit of UCnCTL0 register 0 or UCnRXE bit of UCnCTL0 register 0 has been set When 0 has been written 1 When receive data has been set to the UCnRXB register and the next receive operation is completed before that receiv...

Page 622: ...0BH UC1STR1 FFFFFA2BH 7 6 5 4 3 2 1 0 UCnSTR1 0 0 0 0 0 0 0 UCnRSF n 0 1 UCnRSF Receive Status Flag 0 When UCnPWR bit of UCnCTL0 register 0 or UCnRXE bit of UCnCTL0 register 0 has been set When the stop bit has been detected 1 During reception when the start bit has been detected The UCnRSF flag is set 1 by the start bit detection and it is cleared 0 by detection of the first stop bit condition In...

Page 623: ...SB first reception when the data length has been specified as 7 bits and th extension bit operation is disabled the receive data is transferred to bits 6 to 0 of the UXnRXL register and the MSB always becomes 0 During MSB first reception the receive data is transferred to bits 7 to 1 of the UCnRXL register and the LSB always becomes 0 When an overrun error UCnOVE bit 1 occurs the receive data at t...

Page 624: ... bit or 8 bit data character length is specified UCnEBE bit 0 The UCnTX register can be read or written in 16 bit units The UCnTXL register can be read or written in 8 bit units Reset input sets the UCnTX register to 1FFH and the UCnTXL register to FFH Figure 15 10 UARTCn Transmit Data Register UCnTX UCnTXL After reset 1FFH R W Address UC0TX FFFFFA08H UC1TX FFFFFA28H 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 625: ...or overrun error occur refer to 15 3 6 UARTCn status register UCnSTR 2 Reception complete interrupt INTUCnR A reception complete interrupt is output when data is shifted into the UARTCn receive shift register and transferred to the UCnRX register in the reception enabled status A reception complete interrupt will not be generated when a reception error has occurred No reception complete interrupt ...

Page 626: ...ied in the UCnOPT1 register Moreover control of UART output inverted output for the TXDCn bit is performed using the UCnTDL bit of the UCnOPT0 register Start bit 1 bit Character bits 7 bits 8 bits 9 bits Parity bit Even parity odd parity 0 parity no parityNote Stop bit 1 bit 2 bits Note Extension bit operation presumes no parity setting Figure 15 11 UARTC Transmit Receive Data Format 1 2 a 8 bit d...

Page 627: ...odd parity 2 stop bits transfer data 36H e 8 bit data length LSB first no parity 1 stop bit transfer data 87H f 9 bit data length LSB first no parity 1 stop bit transfer data 155H 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity bit Stop bit Stop bit 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop bit ...

Page 628: ... the UCnOPT0 register If even finer output width adjustments are required such adjustments can be performed using bits UCnBRS7 to UCnBRS0 of the UCnCTLn register 3 80H transfer in the 8 bit mode is substituted for the wake up signal frame 4 A transmission enable interrupt INTUCnT is output at the start of each transmission The INTUCnT signal is also output at the start of each SBF transmission Sle...

Page 629: ...unication error detection processing and UARTCn receive shift register and data transfer of the UCnRX register are not performed The UARTCn receive shift register holds the initial value FFH 4 The RXDCn pin is connected to TI capture input of the timer the transfer rate is calculated and the baud rate error is calculated The value of the UCnCTL2 register obtained by compensating the baud rate erro...

Page 630: ... 13 to 20 specified by the UCnSLS2 to UCnSLS0 bits of the UCnOPT0 register is output A transmission enable interrupt INTUCnT is generated upon SBF transmission start Following the end of SBF transmission the UCnSTT bit is automatically cleared Thereafter the UART transmission mode is restored Transmission is suspended until the data to be transmitted next is written to the UCnTX register or until ...

Page 631: ...if the SBF width is 11 or more bits normal processing is judged and a reception complete interrupt INTUCnR is output Error detection for the UCnOVE UCnPE and UCnFE bits of the UCnSTR register is suppressed and UART communication error detection processing is not performed Moreover UARTCn reception shift register and data transfer of the UCnRX register are not performed and FFH the initial value is...

Page 632: ...nerated upon completion of transmission of the data of the UCnTX register to the UARTCn transmit shift register and thereafter the contents of the UARTCn transmit shift register are output to the TXDCn pin LSB first Write of the next transmit data to the UCnTX register is enabled by generating the INTUCnT signal Continuous transmission is enabled by writing the data to be transmitted next to the U...

Page 633: ...tion rate can thus be achieved During continuous transmission overrun the completion of the next transmission before the first transmission completion processing has been executed may occur An overrun can be detected by incorporating a program that can count the number of transmit data and by referencing transfer status flag UCnTSF bit of UCnSTR register Caution During continuous transmission exec...

Page 634: ...ion start b Transmission end Start Data 1 Data 1 TXDCn UCnTX Transmission shift register INTUCnT UCnTSF Data 2 Data 2 Data 1 Data 3 Parity Stop Start Data 2 Parity Stop Start Start Data n 1 Data n 1 Data n 1 Data n FF Data n TXDCn UCnTX Transmission shift register INTUCnT UCnTSF UCnPWR or UCnTXE Parity Stop Stop Start Data n Parity Parity Stop ...

Page 635: ...CnSTR1 register is set 1 to indicate the receive operation status When the reception complete interrupt INTUCnR is output upon reception of the stop bit the data of the UARTCn receive shift register is written to the UCnRX register and the UCnRSF flag is cleared 0 simultaneously However if an overrun error occurs UCnOVE bit 1 the receive data at this time is not written to the UCnRX register and a...

Page 636: ...error flag is cleared by writing 0 to it Table 15 3 Reception Error Causes Cautions 1 In case of a reception error the reception complete interrupt INTUCnR is not generated Instead of this a reception error interrupt INTUCnRE can be received 2 Be sure to read the UCnRX register even when a reception error occurs If the UCnRX register is not read an overrun error occurs during reception of the next...

Page 637: ... The number of bits whose value is 1 among the reception data including the parity bit is counted and if it is an odd number a parity error is output 2 Odd parity a During transmission Opposite to even parity the number of bits whose value is 1 among the transmit data including the parity bit is controlled so that it is an odd number The parity bit values are as follows Odd number of bits whose va...

Page 638: ...2 When the same sampling value is read twice the match detector output changes and sampling as the input data is performed Moreover since the circuit is as shown in Figure 15 20 the processing that goes on within the receive operation is delayed by 2 clocks in relation to the external signal status Figure 15 20 Noise Filter Circuit Match detector In f 2 XX RXDCn Q I n LD_EN Q Receive data signal ...

Page 639: ...nPWR bit of the UCnCTL0 register is 1 the clock selected by bits UCnCKS3 to UCnCKS0 of the UCnCTL1 register is supplied to the 8 bit counter This clock is called the base clock Clock and its frequency is called fXCLK When the UCnPWR bit 0 the clock is fixed to the low level 2 Serial clock generation A serial clock can be generated by setting the UCnCTL1 register and the UCnCTL2 register n 0 1 The ...

Page 640: ...tion Cautions 1 The baud rate error during transmission must be within the error tolerance on the receiving side 2 The baud rate error during reception must satisfy the range indicated in section 15 6 5 Allowable baud rate range during reception on page 642 Example Base clock fXCLK frequency 16 MHz 16 000 000 Hz Setting value of bits UCnBRS7 to UCnBRS0 of UCnCTL2 register 00110100B k 52 Target bau...

Page 641: ... Data Baud Rate bps fXX 64 MHz UCnCTL1 UCnCTL2 Error 50 0BH 4EH 0 16 300 09H 68H 0 16 600 08H 68H 0 16 1200 07H 68H 0 16 2400 06H 68H 0 16 4800 05H 68H 0 16 9600 04H 68H 0 16 10400 04H 60H 0 16 19200 03H 68H 0 16 31250 02H 80H 0 00 38400 02H 68H 0 16 56000 01H 8FH 0 10 76800 01H 68H 0 16 125000 01H 40H 0 00 153600 01H 34H 0 16 250000 01H 20H 0 00 312500 00H 33H 0 39 1000000 00H 10H 0 00 2000000 00...

Page 642: ...ng the UCnCTL2 register following start bit detection The transmit data can be normally received if up to the last data stop bit can be received in time for this latch timing When this is applied to 11 bit reception the following results in terms of logic FL BR 1 BR UARTCn baud rate n 0 1 k UCnCTL2 setting value n 0 1 FL 1 bit data length Latch timing margin 2 clocks Minimum allowable transfer rat...

Page 643: ...r obtaining the minimum and maximum baud rate values yields the following Remarks 1 The reception accuracy depends on the bit count in 1 frame the input clock frequency and the division ratio k The higher the input clock frequency and the larger the division ratio k the higher the accuracy is 2 k UCnCTL2 setting value n 0 1 Table 15 5 Maximum Minimum Allowable Baud Rate Error Divide Ratio k Maximu...

Page 644: ...art bit detection by the receiving side so this has no influence on the transfer result Figure 15 23 Transfer Rate During Continuous Transfer Assuming 1 bit data length FL stop bit length FLstp and base clock frequency fXCLK we obtain the following equation Therefore the transfer rate during continuous transmission is as follows Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL...

Page 645: ...utput SIBn Serial data input SCKBn Serial clock output Slave select function supported SSBn Serial slave select input Interrupt request signals 3 Reception error interrupt INTCBnRE Reception complete interrupt INTCBnR Transmission enable interrupt INTCBnT Remark μPD70F3187 n 0 1 μPD70F3447 n 0 16 2 Configuration CSIB includes the following hardware Table 16 1 CSIBn Configuration Item Configuration...

Page 646: ...70F3187 n 0 1 μPD70F3447 n 0 2 fXX Internal system clock fBRG0 Clock from BRG0 fBRG1 Clock from BRG1 Internal bus CBnCTL2 CBnCTL0 CBnSTR Controller INTCBnRE INTCBnR SOBn INTCBnT CBnTX SO latch Phase control Shift register CBnRX CBnCTL1 Phase control SIBn fBRG1 fBRG0 f 8 XX f 128 XX f 16 XX f 32 XX f 64 XX SCKBn SSBn Selector ...

Page 647: ...gister is read only in 16 bit units The CBnRXL register is read only in 8 bit units Reset input clears the CBnRX register to 0000H and the CBnRXL register to 00H accordingly In addition to reset input the CBnRX or CBnRXL registers can be initialized by clearing 0 the CBnPWR bit of the CBnCTL0 register Figure 16 2 CSIBn Receive Data Register CBnRX CBnRXL Note Not available on μPD70F3447 Remark μPD7...

Page 648: ... can be read or written in 16 bit units The CBnTXL register can be read or written in 8 bit units Reset input clears the CBnTX register to 0000H and the CBnRXL register to 00H accordingly In addition to reset input the CBnTX and CBnTXL registers can be initialized by clearing to 0 the CBnPWR bit of the CBnCTL0 register Figure 16 3 CSIBn Transmit Data Register CBnTX CBnTXL Note Not available on μPD...

Page 649: ... μPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 01H R W Address CB0CTL0 FFFFFD00H CB1CTL0 FFFFFD20HNote 2 7 6 5 4 3 2 1 0 CBnCTL0 CBnPWR CBnTXENote 1 CBnRXENote 1 CBnDIRNote 1 0 CBnSSENote 1 CBnTMSNote 1 CBnSCE CBnPWR CSIBn Operation Control 0 Stops clock operation and reset the internal circuit 1 Enables operating clock operation The CBnPWR bit controls the CSIB operating clock and...

Page 650: ...low level is input to the SSBn pin CBnTMSNote Transfer Mode Selection 0 Single transfer mode 1 Continuous transfer mode When the CBnTMS bit 0 the single transfer mode is entered so continuous transmission continuous reception are not supported Even in the case of transmission only an interrupt is output upon completion of reception transfer CBnSCE Serial Clock Enable 0 Clock output stopped 1 Clock...

Page 651: ...e on μPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 00H R W Address CB0CTL1 FFFFFD01H CB1CTL1 FFFFFD21HNote 2 7 6 5 4 3 2 1 0 CBnCTL1 0 0 0 CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0 CBnCKP CBnDAP Specification of Data Transmission Reception Timing in Relation to Clock Phase 0 0 0 1 1 0 1 1 CBnCKS2 CBnCKS1 CBnCKS0 Base Clock fXCCLK Mode 0 0 0 fBRG0 Note 1 Master mode 0 0 1 fBRG1 Note 1 M...

Page 652: ...CB0TXE and CB0RXE bits are 0 Figure 16 6 CSIBn Control Register 2 CBnCTL2 Note Not available on μPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 00H R W Address CB0CTL2 FFFFFD02H CB1CTL2 FFFFFD22HNote 7 6 5 4 3 2 1 0 CBnCTL2 0 0 0 0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 CBnCL3 CBnCL2 CBnCL1 CBnCL0 Serial Register Bit Length 0 0 0 0 8 bits 0 0 0 1 9 bits 0 0 1 0 10 bits 0 0 1 1 11 bits 0 1 0 0 1...

Page 653: ...an 16 bits set the data to the CBnTX or CBnRX register starting from the LSB regardless of whether the transfer start bit is the MSB or LSB Any data can be set for the higher bits that are not used but the receive data becomes 0 following serial transfer Figure 16 7 Effect of Transfer Data Length Setting a Transfer bit length 10 bits MSB first b Transfer bit length 12 bits LSB first Remark μPD70F3...

Page 654: ...D03H CB1CTL0 FFFFFD23HNote 7 6 5 4 3 2 1 0 CBnSTR CBnTSF 0 0 0 0 0 0 CBnOVE CBnTSF CSIBn Operation Control 0 Idle status 1 Operating status During transmission this register is set 1 when data is prepared in the CBnTX register and during reception it is set 1 when a dummy read of the CBnRX register is performed The clear timing is after the edge of the last clock CBnOVE Overrun Error Flag 0 No ove...

Page 655: ...status 3 Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply 4 Write transfer data to the CBnTX register transmission start 5 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX CBnRXL register is possible 6 Read the CBnRX register before clearing the CBnPWR bit to 0 7 Check that the CBnTSF bit of the CBnSTR register is 0 an...

Page 656: ...set the transmission reception enable status 3 Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply 4 Write transfer data to the CBnTX register transmission start 5 The reception complete interrupt INTCBnR is output notifying the CPU that writing the CBnTX CBnTXL register is possible 6 Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBnPWR bit t...

Page 657: ...my read of the CBnRX register reception start trigger 5 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX CBnRXL register is possible 6 Clear the CBnSCE bit of the CBnCTL0 register to 0 to set the reception end data status 7 Read the CBnRX register before clearing the CBnPWR bit to 0 8 Check that the CBnTSF bit of the CBnSTR register is 0 and clear the CBn...

Page 658: ...the CBnCTL0 register is 1 to enable CSIB operating clock supply 4 Write transfer data to the CBnTX register transmission start 5 The transmission enable interrupt INTCBnT is received and transfer data is written to the CBnTX register 6 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX CBnRXL register is possible Read the CBnRX register before the next rece...

Page 659: ...e using the CBnDIR bit of the CBnCTL0 register to set the transmission reception enabled status 3 Set the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply 4 Write transfer data to the CBnTX register transmission start 5 The transmission enable interrupt INTCBnT is received and transfer data is written to the CBnTX register 6 Check that the CBnTSF bit of the CBnSTR regi...

Page 660: ...the CBnPWR bit of the CBnCTL0 register is 1 to enable CSIB operating clock supply 4 Perform a dummy read of the CBnRX register reception start trigger 5 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX CBnRXL register is possible Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0 6 Clear the CBnSCE bit of...

Page 661: ... 3 Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply 4 Perform a dummy read of the CBnRX register reception start trigger 5 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX CBnRXL register is possible 6 If the data could not be read before the end of the next transfer a receive error interrupt INTCBnRE is output and the...

Page 662: ...the CBnCTL0 register to 1 to enable CSIB operating clock supply 4 Write the transfer data to the CBnTX register 5 The transmission enable interrupt INTCBnT is received and the transfer data is written to the CBnTX register 6 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX register is possible Read the CBnRX register before the next receive data arrives o...

Page 663: ...0 register to set the reception enabled status 3 Set the CBnPWR bit of the CBnCTL0 register to 1 to enable CSIB operating clock supply 4 Perform a dummy read of the CBnRX register reception start trigger 5 The reception complete interrupt INTCBnR is output notifying the CPU that reading the CBnRX register is possible Read the CBnRX register before the next receive data arrives or before the CBnPWR...

Page 664: ... Clock Timing 1 2 a CBnCKP 0 CBnDAP 0 b CBnCKP 1 CBnDAP 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 D6 D5 D4 D3 D2 D1 D0 D7 SIBn capture Reg R W SOBn pin INTCBnT interrupt INTCBnR interrupt CBnTSF bit SCKBn pin D6 D5 D4 D3 D2 D1 D0 D7 SIBn capture Reg R W SOBn pin INTCBnT interrupt INTCBnR interrupt CBnTSF bit SCKBn pin ...

Page 665: ...ng 2 2 c CBnCKP 0 CBnDAP 1 d CBnCKP 1 CBnDAP 1 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 D6 D5 D4 D3 D2 D1 D0 D7 SIBn capture Reg R W SOBn pin INTCBnT interrupt INTCBnR interrupt CBnTSF bit SCKBn pin D6 D5 D4 D3 D2 D1 D0 D7 SIBn capture Reg R W SOBn pin INTCBnT interrupt INTCBnR interrupt CBnTSF bit SCKBn pin ...

Page 666: ...itten 2 μPD70F3187 n 0 1 μPD70F3447 n 0 2 SOBn pin When CSIBn operation is disabled CBnPWR bit 0 the SOBn pin output status is as follows Remarks 1 The SOBn pin output changes when any one of the CBnTXE CBnDAP and CBnDIR bits of the CBnCTL1 register is rewritten 2 μPD70F3187 n 0 1 μPD70F3447 n 0 3 don t care CBnCKP SCKBn Pin Output 0 Fixed to high level 1 Fixed to low level CBnTXE CBnDAP CBnDIR SO...

Page 667: ...ion Figure 16 19 Operation Flow of Single Transmission Note Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings Remark μPD70F3187 n 0 1 μPD70F3447 n 0 START No Yes INTCBnR 1 Transfer data exists END Yes No Initial settings CBnCTL0 CBnCTL1 registers etc Note CBnTX register write Transfer start ...

Page 668: ...Reception Master Note Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings Remark μPD70F3187 n 0 1 μPD70F3447 n 0 START No No INTCBnR 1 Last data END Yes Yes Dummy read of CBnRX register CBnCTL0 CBnSCE bit 0 CBnCTL0 CBnSCE bit 1 CBnRX register read CBnRX register read Initial settings CBnCTL0 CBnCTL1 registers etc Note ...

Page 669: ...16 21 Operation Flow of Single Reception Slave Note Set the CBnSCE bit of CBnCTL0 register to 1 as part of the initial settings Remark μPD70F3187 n 0 1 μPD70F3447 n 0 START No No INTCBnR 1 Last data END Yes Yes CBnRX register read Initial settings CBnCTL0 CBnCTL1 registers etc Note Dummy read of CBnRX register ...

Page 670: ...er to 1 as part of the initial settings Remarks 1 The steps below the broken line constitute the transmission flow Execute only steps below the broken line when starting the second and subsequent transmissions 2 μPD70F3187 n 0 1 μPD70F3447 n 0 START No Yes INTCBnT 1 Data to be transferred next exists END Yes No CBnTX register write transfer start Initial settings CBnCTL0 CBnCTL1 registers etc Note...

Page 671: ...he steps below the broken line constitute the transmission flow Execute only steps below the broken line when starting the second and subsequent transmissions 2 μPD70F3187 n 0 1 μPD70F3447 n 0 No No INTCBnR 1 Data currently received last data Yes Yes CBnCTL0 CBnSCE bit 0 CBnRX register read No INTCBnR 1 END Yes CBnCTL0 CBnSCE bit 1 CBnRX register read CBnRX register read START Initial settings CBn...

Page 672: ...L0 register to 1 as part of the initial settings Remarks 1 The steps below the broken line constitute the transmission flow Execute only steps below the broken line when starting the second and subsequent transmissions 2 μPD70F3187 n 0 1 μPD70F3447 n 0 START No No INTCBnR 1 Last data END Yes Yes CBnRX register read Initial settings CBnCTL0 CBnCTL1 registers etc Note Dummy read of CBnRX register ...

Page 673: ... and CSIB1 are connected as shown in the following block diagram Figure 16 26 Block Diagram of CSIBn Baud Rate Generators Note Not available on μPD70F3447 Remarks 1 An unused baud rate generator BRGm can be employed as interval timer generating a dedicated interrupt request INTBRGm 2 m 0 1 BRGOUTm INTBRGm PRSCMm 8 bit Counter Output Control f 8 XX f 16 XX f 32 XX f 64 XX CSIB0 CSIB1 INTBRG0 BRGOUT...

Page 674: ...register to 00H Figure 16 27 Prescaler Mode Registers 0 and 1 PRSM0 PRSM1 Cautions 1 Do not rewrite the PRSMm register during operation 2 Set the BGCSm1 BGCSm0 bits before setting the BGCEm bit to 1 Remark m 0 1 After reset 00H R W Address PRSM0 FFFFFDC0H PRSM1 FFFFFDD0H 7 6 5 4 3 2 1 0 PRSMm 0 0 BGCEm 0 0 BGCSm1 BGCSm0 m 0 1 BGCEm Baud Rate Generator Output Control 0 Disabled 1 Enabled BGCSm1 BGC...

Page 675: ...SCMm register before setting the BGCEm bit of the PRSMm register to 1 Remarks 1 fBGCSm Clock frequency selected by the BGCSm1 BGCSm0 bits of the PRSMm register 2 m 0 1 After reset 00H R W Address PRSM0 FFFFFDC1H PRSM1 FFFFFDD1H 7 6 5 4 3 2 1 0 PRSCMm PRSCMm7 PRSCMm6 PRSCMm5 PRSCMm4 PRSCMm3 PRSCMm2 PRSCMm1 PRSCMm0 m 0 1 PRSCM m7 PRSCM m6 PRSCM m5 PRSCM m4 PRSCM m3 PRSCM m2 PRSCM m1 PRSCM m0 Serial ...

Page 676: ...n completion interrupt INTCBnR In the single transfer mode writing the next transmit data is ignored during communication CBnTSF bit 1 and the next transfer is not started Also if reception only communication CBnCTL0 CBnTXE bit 0 CBnCTL0 CBnRXE bit 1 is set the next transfer is not started even if the receive data is read during communication CBnTSF bit 1 Therefore when using the single transfer m...

Page 677: ...rst switchable Transmission mode reception mode and transmission reception mode selectable 3 wire serial interface SO3n Serial data output SI3n Serial data input SCK3n Serial clock I O Four external chips select signal outputs SCS3n0 to SCS3n3 Interrupt request signals 2 Transmission reception completion interrupt INTC3n CSIBUFn overflow interrupt INTC3nOVF Sixteen on chip 20 bit transmit receive ...

Page 678: ...t CSI buffer register 3n SFCS3n The SFCS3n register is a 16 bit buffer register that stores chip select data The lower 8 bits can also be accessed by an 8 bit buffer register SFCS3nL 6 Transmit data CSI buffer register 3n SFDB3n The SFDB3n register is a 16 bit buffer register that stores transmit data This register is also divided into two registers the higher 8 bits SFDB3nH and lower 8 bits SFDB3...

Page 679: ...n INTC3n SI3n SCS3n3 SCS3n2 SCS3n1 SCS3n0 SCK3n Transfer control CSI data buffer register n CSIBUFn BRG3n Prescaler output fXX Receive data buffer register 3n SIRB3n Shift register n SIO3n 0 19 15 16 INTC3nOVF Transfer data control CSIBUF status register 3n SFA3n Transmit data CSI buffer register 3n SFDB3n Chip Select CSI buffer register 3n SFCS3n Selector Chip Select Control fXCLK Clocked serial ...

Page 680: ...eset 00H R W Address CSIM30 FFFFFD40H CSIM31 FFFFFD60HNote 7 6 5 4 3 2 1 0 CSIM3n CSICAEn CTXEn CRXEn TRMDn DIRn CSITn CSWEn CSMDn CSICAEn CSI3n Operation Clock Control 0 Stops clock supply to CSI3n 1 Supplies clock to CSI3n Cautions 1 The CSI3n unit is reset when the CSICAEn bit 0 and CSI3n is stopped To operate CSI3n first set the CSICAEn bit to 1 2 When rewriting the CSICAEn bit from 0 to 1 or ...

Page 681: ... the INTC3n interrupt is not output except when the last data set by the SFNn3 to SFNn0 bits of the SFN3n register is transferred but a delay of half a clock can be inserted between each data transferred CSWEn Transfer Wait Control 0 Disables transfer wait 1 Enables transfer wait 1 wait cycle inserted on starting transfer Caution Inserting a transfer wait cycle CSWEn bit 1 is valid only in the mas...

Page 682: ... CSIM3n register Figure 17 3 Clocked Serial Interface Clock Select Register 3n CSIC3n 1 3 Note Not available on µPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 07H R W Address CSIC30 FFFFFD41H CSIC31 FFFFFD61HNote 7 6 5 4 3 2 1 0 CSIC3n MDLn2 MDLn1 MDLn0 CKPn DAPn CKS3n2 CKS3n1 CKS3n0 MDLn2 MDLn1 MDLn0 Set Value N Transfer Clock BRG3n Output Signal 0 0 0 BRG3n stop mode power save 0 ...

Page 683: ...e port mode control register PMC82 of the PMC8 register for CSI30 or PMC92 of the PMC9 register for CSI31 to 0 The pin is set into port mode fixed to low level output 4 Clear the CTXEn and CRXEn bits of the CSIM3n register to 0 Transmission and reception are disabled 5 Set the CTXEn or CRXEn bit of the CSIM3n register to 1 Transmission or reception is enabled both transmission and reception can al...

Page 684: ...C3n 3 3 Remarks 1 fXX Main clock 2 μPD70F3187 n 0 1 μPD70F3447 n 0 CKS3n2 CKS3n1 CKS3n0 Set Value k Basic Clock fXCLK Mode 0 0 0 0 fXX Master mode 0 0 1 1 fXX 2 Master mode 0 1 0 2 fXX 4 Master mode 0 1 1 3 fXX 8 Master mode 1 0 0 4 fXX 16 Master mode 1 0 1 5 fXX 32 Master mode 1 1 0 6 fXX 64 Master mode 1 1 1 External clock SCK3n Slave mode ...

Page 685: ... input clears the SIRB3n register to 0000H and the SIRB3nL and SIRB3nH registers to 00H accordingly In addition to reset input the SIRB3n as well as the SIRB3nL and SIRB3nH registers are initialized by clearing to 0 the CSICAEn bit of the CSIM3n register Figure 17 4 Receive Data Buffer Register 3n SIRB3n SIRB3nL SIRB3nH Notes 1 In consecutive mode TRMDn bit of the CSIM3n register 1 Undefined 2 Not...

Page 686: ...ransmit data written last is read The SFCS3n register can be read or written in 16 bit units The SFCS3nL register can be read or written in 8 bit or 1 bit units Reset input clears the SFCS3n register to FFFFH and the SFCS3nL register to FFH accordingly Figure 17 5 Chip Select CSI Buffer Register 3n SFCS3n SFCS3nL Note Not available on µPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset F...

Page 687: ...DB3nH registers can be read or written in 8 bit or 1 bit units Reset input clears the SFDB3n register to 0000H and the SFDB3nL and SFDB3nH registers to 00H accordingly Figure 17 6 Transmit Data CSI Buffer Register 3n SFDB3n SFDB3nL SFDB3nH Note Not available on µPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 0000H R W Address SFDB30 FFFFFD46H SFDB31 FFFFFD66HNote 15 14 13 12 11 10 9 ...

Page 688: ...ter is read immediately after data has been written to the SFDB3n and SFDB3nL registers the values of the SFFULn SFEMPn and SFPn3 to SFPn0 bits do not change in time 4 If the SFA3n register is read before the SFFULn bit is set to 1 and the 17th data is written the CSIBUFn overflow interrupt INTC3nOVF is generated Figure 17 7 CSIBUF Status Register 3n SFA3n 1 3 Note Not available on µPD70F3447 Rema...

Page 689: ...us Flag 0 Data is in CSIBUFn register 1 CSIBUFn is empty Cautions 1 This flag is cleared to 0 when the CSICAEn bit of the CSIM3n register is cleared to 0 and the FPCLR bit is set to 1 2 If the data written to the CSIBUFn register has been transferred in the consecutive mode TRMDn bit of the CSIM3n register 1 the SFEMP bit is set to 1 in the same way as in the single mode TRMDn bit of the CSIM3n re...

Page 690: ...bit of the CSIM3n register 1 the number of data completely transferred value of CSIBUFn pointer for SIO3n loading storing can be read If the SFPn3 to SFPn0 bits are 0H however the number of transferred data is as follows depending on the setting of the SFEMPn bit When SFEMPn bit 0 Number of transferred data 0 When SFEMPn bit 1 Number of transferred data 16 or status before starting transfer before...

Page 691: ...1 μPD70F3187 n 0 1 μPD70F3447 n 0 2 m 0 to 3 After reset 00H R W Address CSIL30 FFFFFD49H CSIL31 FFFFFD69HNote 7 6 5 4 3 2 1 0 CSIL3n CSLVn3 CSLVn2 CSLVn1 CSLVn0 CCLn3 CCLn2 CCLn1 CCLn0 CSLVnm Chip Select Output SCS3nm Level Setting n 0 1 m 0 to 3 0 Active level of SCSnm output is low level 1 Active level of SCSnm output is high level CCLn3 CCLn2 CCLn1 CCLn0 Transfer Data Length 0 0 0 0 16 bits 1 ...

Page 692: ... SFN3n Note Not available on µPD70F3447 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 After reset 00H R W Address SFN30 FFFFFD49H SFN31 FFFFFD69HNote 7 6 5 4 3 2 1 0 SFN3n 0 0 0 0 SFNn3 SFNn2 SFNn1 SFNn0 SFNn3 SFNn2 SFNn1 SFNn0 Number of Transfer Data 0 0 0 0 16 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14...

Page 693: ...register In the master mode CKS3n2 to CKS3n0 bits of the CSIC3n register other than 111B BRG3n is selected as the clock source 1 Transfer clock Figure 17 10 Transfer Clock of CSI3n Remarks 1 μPD70F3187 n 0 1 μPD70F3447 n 0 2 fXX Main clock fXCLK Basic clock selected by CSIC3n register Prescaler 1 1 1 2 1 4 1 8 1 16 1 32 1 64 Clocked serial interface clock select register 3n CSIC3n Selector BRG3n 1...

Page 694: ...IC3n register 1 N 7 Cautions 1 If the CKS3n2 to CKS3n0 bits of the CSIC3n register are cleared to 000B setting the MDLn2 to MDLn0 bits of the CSIC3n register to 001B is prohibited 2 Because the maximum transfer rate in the master mode CKS3n2 to CKS3n0 bits other than 111B is 8 Mbps do not exceed this value Example When the main clock fXX is 64 MHz the maximum transfer rate is set when the CKS3n2 t...

Page 695: ... Table 17 1 Operation Modes TRMDn Bit CKS3n2 to CKS3n0 Bits CTXEn and CRXEn Bits DIRn Bit CSITn Bit CSWEn Bit CSMDn Bit Single mode Master mode Transmission reception transmission and reception MSB LSB first INTC3n delay mode enabled disabled Transfer wait disabled Intermediate inactive level of chip select outputs disabled Transfer wait enabled Intermediate inactive level of chip select outputs e...

Page 696: ... in 8 bit units or to the SFDB3n register in 16 bit units If data is written to the SFDB3nL register in 16 bit units however the higher 8 bits of the data of the SFDB3nH register are ignored and not transferred The SFFULn bit of the SFA3n register is set to 1 when 16 data exist in the CSIBUFn register and outputs a CSIBUFn overflow interrupt INTC3nOVF when the SFFULn bit 1 and when the 17th transf...

Page 697: ...ransfer Direction Specification MSB first a Transfer direction MSB first Transfer data length 8 Bits b Writing from SFDB3n register to CSIBUFn register c Reading from CSIBUFn register or SFDB3n register Remark μPD70F3187 n 0 1 μPD70F3447 n 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK3n I O SI3n input SO3n output SFDB3n CSIBUFn Data 00H SIO3n 15 8 7 0 SO3n SI3n SFDB3n read ...

Page 698: ...irst Transfer data length 8 Bits b Writing from SFDB3n register to CSIBUFn register c Reading from CSIBUFn register or SFDB3n register Remark μPD70F3187 n 0 1 μPD70F3447 n 0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SCK3n I O SI3n input SO3n output SFDB3n CSIBUFn Data 00H SIO3n 15 8 7 0 SO3n SI3n SFDB3n read value CSIBUFn or SIRB3n 00H Data SIO3n 15 8 7 0 SO3n SI3n ...

Page 699: ...units by using the CCLn3 to CCLn0 bits of the CSIL3n register n 1 0 Figure 17 14 Transfer Data Length Changing Function Transfer Data Length 16 Bits CCLn3 to CCLn0 Bits of CSIL3n Register 0000B Transfer Direction MSB First DIRn Bit of CSIM3n Register 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 DI15 DI14 DI13 DI12 DI2 DI1 DI0 DO15 DO14 DO13 DO12 DO2 DO1 DO0 SCK3n I O SI3n input SO3n output ...

Page 700: ...Figure 17 15 Clock Timing a When CKPn bit 0 DAPn bit 0 b When CKPn bit 0 DAPn bit 1 c When CKPn bit 1 DAPn bit 0 d When CKPn bit 1 DAPn bit 1 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 INTC3n interrupt SI3n capture SCK3n SO3n D7 D6 D5 D4 D3 D2 D1 D0 INTC3n interrupt SI3n capture SCK3n SO3n D7 D6 D5 D4 D3 D2 D1 D0 INTC3n interrupt SI3n capture SCK3n SO3n D7 D6 D5 D4 D3 D2 D1 D0 INTC3n interrupt SI3n ca...

Page 701: ...pin is high when the CKPn bit of the CSIC3n register is 0 and low when the CKPn bit is 1 In master mode the chip select outputs SCS3n0 to SCS3n3 are effective Figure 17 16 Master Mode CKPn and DAPn Bits of CSIC3n Register 00B Active Level of CS Outputs Low Level CSLVn3 to CSLVn0 Bits of CSIL3n Register 0000B Transfer Data Length 8 Bits CCLn3 to CCLn0 Bits of CSIL3n Register 1000B Remark μPD70F3187...

Page 702: ...er which data can be transferred in the slave mode are listed in the table below Remarks 1 CTXEn bit Bit 6 of CSIM3n register CRXEn bit Bit 5 of CSIM3n register SFEMPn bit Bit 5 of SFA3n register 2 μPD70F3187 n 0 1 μPD70F3447 n 0 Table 17 2 Conditions Under Which Data Can Be Transferred in Slave Mode Transfer Mode CTXEn Bit CRXEn Bit CSIBUFn Register SIRB3n Register and SIO3n Register Single mode ...

Page 703: ...d If the SIRB3n register is empty when one data has been transferred in the reception mode or transmission reception mode the received data is stored from the SIO3n register to the SIRB3n register the transmission reception completion interrupt INTC3n is output and the SIO3n load CSIBUFn pointer is incremented If the SIRB3n register is not empty the next transfer processing is started However stor...

Page 704: ... 0 0 Transfer data 0 CS data 0 CS data 1 CS data 2 CS data 3 CS data 4 Note Transfer data 1 Transfer data 2 Transfer data 3 Transfer data 4 SFPn3 to SFPn0 7 0 3 4 3 4 CSIBUF status register 3n SFA3n Incremented SIO3n load CSIBUFn pointer Incremented Write CSIBUFn pointer Transmit data CSI buffer register 3n SFDB3n SFDB3nH SFDB3nL 15 8 7 0 Chip select CSI buffer register 3n SFCS3n 15 8 7 0 Differen...

Page 705: ...store CSIBUFn pointer is loaded from the CSIBUFn register to SIO3n register Then transfer processing is started When transfer processing of one data is completed in the reception mode or transmission reception mode the received data is overwritten from the SIO3n register to the transfer data in the CSIBUFn register indicated by the SIO3n load store CSIBUFn pointer and then the pointer is increment...

Page 706: ...5 0 0 Transfer data 0 CS data 0 CS data 1 CS data 2 CS data 3 Note Transfer data 1 Transfer data 2 Transfer data 3 SFPn3 to SFPn0 7 0 3 4 3 4 CSIBUF status register 3n SFA3n Transmit data CSI buffer register 3n SFDB3n SFDB3nH SFDB3nL 15 8 7 0 Chip select CSI buffer register 3n SFCS3n 15 8 7 0 SFCS3n3 to SFCS3n0 SCS3n0 SCS3n1 SCS3n2 SCS3n3 Chip select output buffer Incremented Read CSIBUFn pointer ...

Page 707: ... bit of the CSIM3n register 0 however the condition of starting reception includes that the SIRB3n or SIO3n register is empty If reception to the SIO3n register is completed when the previously received data is held in the SIRB3n register without being read the previously received data is read from the SIRB3n register and the wait status continues until the SIRB3n register becomes empty The SO3n p...

Page 708: ...upt is not affected Caution If the CSITn bit of the CSIM3n register is set to 1 in the consecutive mode TRMDn bit of the CSIM3n register 1 the INTC3n interrupt is not output at the end of data other than the last data set by the SFNn3 to SFNn0 bits of the SFN3n register but a delay of half a clock can be inserted between each data transfer Figure 17 20 Delay Control of Transmission Reception Compl...

Page 709: ...wait function is enabled CSWEn bit 1 the chip select outputs can be During transfer wait CSWE bit 1 the chip select outputs SCS3n0 to SCS3n3 can be configured for an intermediate inactive level output of half a clock period by setting the CSMDn bit of the CSIM3n register to 1 Figure 17 21 Transfer Wait Function 1 3 a Transfer Wait Enabled CSWEn Bit 1 INTC3n Delay Disabled CSITn Bit 0 CKPn and DAPn...

Page 710: ...el and maintain it When the CSIBUFn register is not empty at the time of 1 the chip select pins output an inactive level up to the time of 2 and output subsequently the succeeding chip select data Moreover in single mode TRMDn bit of the CSIM3n register 0 the chip select pins output an inactive level from the time 1 and held it pending until the previously receive data is read from the SIRB3n regi...

Page 711: ...n Delay Enabled CSITn Bit 1 CKPn and DAPn Bits 00B Transfer Data Length 8 Bits CCLn3 to CCLn0 bits 1000B Intermediate Inactive Chip Select Level Disabled CSMDn 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 DI7 DI6 DI5 DO7 DO6 DO5 SCK3n output SI3n input SO3n output INTC3n interrupt DI7 DI1 DI0 Wait Delay DO1 DO0 DO7 Delay CS data CS data SCS3n0 to SCS3n3 outputs ...

Page 712: ...the SCK3n pin changes if the CKPn bit is rewritten in the master mode 2 μPD70F3187 n 0 1 μPD70F3447 n 0 2 SO3n pin The SO3n pin outputs a low level when both the CTXEn and CRXEn bits of the CSIM3n register are 0 n 0 1 This pin outputs a low level when the FPCLRn bit of the SFA3n register is set to 1 the previous value is retained only in the slave mode CKS3n2 to CKS3n0 bits of the CSIC3n register ...

Page 713: ...F3447 n 0 17 5 17 CSIBUFn overflow interrupt signal INTC3nOVF The INTC3nOVF interrupt is output when 16 data exist in the CSIBUFn register and when the 17th data is written to the SFDB3n or SFDB3nL register The 17th data is not written but ignored In the single mode TRMDn bit of the CSIM3n register 0 16 data exist in the CSIBUFn register when write CSIBUFn pointer value SIO3n load CSIBUFn pointer ...

Page 714: ...el L Level CSLVn3 to CSLVn0 bits 0000B Note During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit SFEMPn flag SFDB3n register write CSIBUF3n 0 55H AAH CCH CS0 1 2 3 4 CS1 CS2 CS...

Page 715: ... and at the same time enable transmission by setting the CTXEn bit to 1 6 Confirm that the SFFULn bit of the SFA3n register is 0 and then write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n it is not always nece...

Page 716: ...e slave is put on hold until the SIRB3n register is read 2 During this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CRXEn bit SFDB3n register write CSIBUF3n 0 dummy 55H CS0 CS1 CS2 AAH...

Page 717: ...register is 0 and then write first CS data to the SFCS3n register and subsequently write dummy transfer data to the SFDB3n register reception start trigger If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTC3n it is not always necessary to confirm that the SFFULn bit is 0 7 Confirm that the INTC3n interrupt h...

Page 718: ...on hold until the SIRB3n register is read 2 During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit CRXEn bit SFDB3n register write CSIBUF3n 0 55H AAH 33H CCH CS0 CS1 CS2 96H CSIB...

Page 719: ...etting the CTXEn and CRXEn bits to 1 6 Confirm that the SFFULn bit of the SFA3n register is 0 and then write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n it is not always necessary to confirm that the SFFULn bi...

Page 720: ... Level L Level CSLVn3 to CSLVn0 bits 0000B Note During this period a transmission to the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit SFDB3n register write CSIBUF3n 0 55H AAH 1 2 3 4 CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO3n pin CSOTn flag INTC3n s...

Page 721: ...tting the CTXEn bit to 1 6 Confirm that the SFFULn bit of the SFA3n register is 0 and then write transfer data to the SFDB3n register Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary If it is clearly known that the SFFULn bit is 0 because transfer data is written to that ...

Page 722: ...r will be ignored until at least one dummy transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 2 While the SIRB3n register is full a new reception from the master will be ignored until the SIRB3n register is read Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CRXEn bit SFDB3n register write CSIBUF3n 0 dummy 55H AAH CSIBUF3n 1 CSIBUF3n 2 SCK3n pin ...

Page 723: ...B3n register reception start trigger Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary If it is clearly known that the SFFULn bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of INTC3n it is not always necessary to confirm that...

Page 724: ...il at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 2 While the SIRB3n register is full a new transmission reception from the master will be ignored until the SIRB3n register is read Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit CRXEn bit SFDB3n register write CSIBUF3n 0 55H AAH CCH 96H CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO...

Page 725: ... bit of the SFA3n register is 0 and then write transfer data to the SFDB3n register Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary If it is clearly known that the SFFULn bit is 0 because transfer data is written to that bit by the interrupt servicing routine of INTC3n i...

Page 726: ...vel L Level CSLVn3 to CSLVn0 bits 0000B Note During this period a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer CTXEn bit SFDB3n register write CSIBUF3n 0 55H AAH CCH CS0 CS1 CS2 CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO3n pin CSOTn flag INTC3n s...

Page 727: ...CTXEn bit to 1 6 Set the number of data to be transmitted by using the SFNn3 to SFNn0 bits of the SFN3n register 7 Write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register Writing data exceeding the set value of the SFN3n register is prohibited 8 Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1 Then write 1 to the FPCLRn bit of th...

Page 728: ...ng this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CRXEn bit SFEMPn flag SFDB3n register write CSIBUF3n 0 dummy 55H dummy CS0 1H CS1 CS2 CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SI3n pin CSOT...

Page 729: ...ata to the SFCS3n register and subsequently write dummy transfer data to the SFDB3n register reception start trigger Writing dummy data exceeding the set value of the SFN3n register is prohibited 8 Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1 Then read the SIRB3n register sequentially read the receive data stored in the CSIBUFn register 9 Write 1 to the FPCLRn bit of the ...

Page 730: ... a reception from the slave is put on hold until at least one transmit data has been loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 in order to start the transfer Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit CRXEn bit SFEMPn flag SFDB3n register write CSIBUF3n 0 55H CCH 96H 33H CS0 1H CS1 CS2 CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO3n pin SI3n pin CSOTn...

Page 731: ...ed received by using the SFNn3 to SFNn0 bits of the SFN3n register 7 Write first CS data to the SFCS3n register and subsequently write transfer data to the SFDB3n register Writing data exceeding the set value of the SFN3n register is prohibited 8 Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1 Then read the SIRB3n register sequentially read the receive data stored in the CSI...

Page 732: ...el L Level CSLVn3 to CSLVn0 bits 0000B Note During this period a reception request from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit SFDB3n register write CSIBUF3n 0 55H AAH CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO3n pin CSOTn flag INTC3n signal...

Page 733: ...y using the SFNn3 to SFNn0 bits of the SFN3n register 7 Write transfer data to the SFDB3n register Writing data exceeding the set value of the SFN3n register is prohibited Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary 8 Confirm that the INTC3n interrupt has occurred an...

Page 734: ...LVn0 bits 0000B Note During this period a transmission from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CRXEn bit SFEMPn flag SFDB3n register write CSIBUF3n 0 dummy 55H dummy 1H CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SI3n pin CSOTn flag INTC3n signal SIRB...

Page 735: ...iting dummy data exceeding the set value of the SFN3n register is prohibited Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary 8 Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1 Then read the SIRB3n register sequentially read the receive data stored i...

Page 736: ...e During this period a transmission reception from the master will be ignored until at least one transmit data is loaded to the CSIBUFn register by writing the SFDB3n register SFEMPn flag of SFA3n register 0 Remark μPD70F3187 n 0 1 μPD70F3447 n 0 CTXEn bit CRXEn bit SFEMPn flag SFDB3n register write CSIBUF3n 0 55H CCH 96H 1H CSIBUF3n 1 CSIBUF3n 2 SCK3n pin SO3n pin SI3n pin CSOTn flag INTC3n signa...

Page 737: ...register 7 Write transfer data to the SFDB3n register Writing data exceeding the set value of the SFN3n register is prohibited Since the chip select outputs SCS3n0 to SCS3n3 are ineffective in the slave mode and always output the inactive level writing of CS data to the SFCS3n register is not necessary 8 Confirm that the INTC3n interrupt has occurred and the SFEMPn bit is 1 Then read the SIRB3n re...

Page 738: ...clearing the pointers and if the previously transferred data remains in the CSIBUFn register transferring that data is immediately started If transfer data is set to the CSIBUFn register before transfer is enabled transfer is started as soon as the CTXEn or CRXEn bit is set to 1 3 If the SFA3n register is read immediately after data has been written to the SFDB3n and SFDB3nL registers the SFFULn S...

Page 739: ...r the CAN message buffer registers are identified by m m 0 to 31 for example C0MDATA4m for CAN0 message data byte 4 of message buffer register m 18 1 Features Compliant with ISO 11898 and tested according to ISO DIS 16845 CAN conformance test Standard frame and extended frame transmission reception enabled Transfer rate 1 Mbps max if CAN clock input 8 MHz for 32 channels 32 message buffers per cha...

Page 740: ...o each message buffer Transmit completion interrupt for each message buffer Message buffer number 0 to 7 specified as the transmit message buffer can be set for automatic block transfer Message transmission interval is programmable automatic block transmission function hereafter referred to as ABT Transmission history list function Remote frame processing Remote frame processing by transmit messag...

Page 741: ... the CAN RAM within the CAN module CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings CAN RAM This is the CAN memory functional block which is used to store message IDs message data etc Figure 18 1 Block Diagram of CAN Module CANTXn CANRXn CPU CAN module CAN RAM NPB NEC Peripheral I O Bus MCM Message Control Module NPB interface Inter...

Page 742: ... 1 Frame format 1 Standard format frame The standard format frame uses 11 bit identifiers which means that it can handle up to 2 048 messages 2 Extended format frame The extended format frame uses 29 bit 11 bits 18 bits identifiers which increases the number of messages that can be handled to 2 048 218 messages An extended format frame is set when recessive level CMOS level of 1 is set for both th...

Page 743: ...bus value becomes dominant level 18 2 3 Data frame and remote frame 1 Data frame A data frame is composed of seven fields Figure 18 3 Data Frame Note D Dominant 0 R Recessive 1 Table 18 2 Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the ne...

Page 744: ...sive 1 If dominant level is detected in the bus idle state a hard synchronization is performed the current TQ is assigned to be the SYNC segment If dominant level is sampled at the sample point following such a hard synchronization the bit is assigned to be a SOF If recessive level is detected the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbanc...

Page 745: ...irst Note D Dominant 0 R Recessive 1 Figure 18 7 Arbitration field in extended format mode Cautions 1 ID28 to ID18 are identifiers 2 An identifier is transmitted MSB first Note D Dominant 0 R Recessive 1 Table 18 3 RTR frame settings Frame Type RTR Bit Data frame 0 D Remote frame 1 R R D IDE r1 r0 RTR Identifier Arbitration field Control field 11 bits 1 bit 1 bit ID28 ID18 R D r1 r0 RTR IDE SRR Id...

Page 746: ...de is not 0000B Table 18 4 Frame format setting IDE bit and number of identifier ID bits Frame Format SRR Bit IDE Bit Number of Bits Standard format mode None 0 D 11 bits Extended format mode 1 R 1 R 29 bits Table 18 5 Data length setting Data Length Code Data Byte Count DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 byt...

Page 747: ...5 bit CRC sequence is expressed as follows P X X15 X14 X10 X8 X7 X4 X3 1 Transmitting node Transmits the CRC sequence calculated from the data before bit stuffing in the start of frame arbitration field control field and data field Receiving node Compares the CRC sequence calculated using data bits that exclude the stuffing bits in the receive data with the CRC sequence in the CRC field If the two...

Page 748: ...cted the receiving node sets the ACK slot to the dominant level The transmitting node outputs two recessive level bits g End of frame EOF The end of frame field indicates the end of data frame remote frame Figure 18 12 End of frame EOF Note D Dominant 0 R Recessive 1 R D ACK slot 1 bit ACK delimiter 1 bit ACK field End of frame CRC field R D End of frame 7 bits Interframe space or overload frame A...

Page 749: ...r passive node The interframe space consists of an intermission field a suspend transmission field and a bus idle field Figure 18 14 Interframe space error passive node Notes 1 Bus idle State in which the bus is not used by any node Suspend transmission Sequence of 8 recessive level bits transmitted from the node in the error passive status 2 D Dominant 0 R Recessive 1 Usually the intermission fie...

Page 750: ...tively If another node outputs a dominant level while one node is outputting a passive error flag the passive error flag is not cleared until the same level is detected 6 bits in a row 2 Error flag 2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag 3 Error delimiter 8 Outputs 8 recessive level bits consecutively If a dominant level is detected at the 8th bit a...

Page 751: ...D Dominant 0 R Recessive 1 Table 18 8 Definition of overload frame fields No Name Bit count Definition 1 Overload flag 6 Outputs 6 dominant level bits consecutively 2 Overload flag from other node 0 to 6 The node that received an overload flag in the interframe space outputs an overload flag 3 Overload delimiter 8 Outputs 8 recessive level bits consecutively If a dominant level is detected at the ...

Page 752: ...e extended format data frame and the standard format remote frame conflict on the bus if ID28 to ID18 of both of them are the same the standard format remote frame takes pri ority 18 3 2 Bit stuffing Bit stuffing is used to establish synchronization by appending 1 bit of inverted level data if the same level continues for 5 bits in order to prevent a burst error Table 18 9 Determining bus priority...

Page 753: ... types Table 18 11 Error types Type Description of error Detection state Detection method Detection condition Transmis sion Reception Field Frame Bit error Comparison of the output level and level on the bus except stuff bit Mismatch of levels Transmitting receiving node Bit that is outputting data on the bus at the start of frame to end of frame error frame and overload frame Stuff error Check of...

Page 754: ...te must be tested because it is considered that the bus has a serious fault An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit of the CnINFO register is set to 1 If the value of the transmission error counter is greater than or equal to 256 actually the transmission error counter does not indicate a value greater than or equal to 256 the bus off state...

Page 755: ... to 127 TECS1 TECS0 01 Reception 96 to 127 RECS1 RECS0 01 Error passive Transmission 128 to 255 TECS1 TECS0 11 Outputs a passive error flag 6 consecutive recessive level bits on detection of the error Transmits 8 recessive level bits in between transmissions following an intermission suspend transmission Reception 128 or more RECS1 RECS0 11 Bus off Transmission 256 or more not indicated Note BOFF ...

Page 756: ...the error counter does not change in the following cases 1 ACK error is detected in error passive state and dominant level is not detected while the passive error flag is being output 2 A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit but a dominant level is detected 8 No change Bit error detection while active error flag or overload flag is being...

Page 757: ...nsecutive recessive level bits 128 times At this time the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied When the recovery conditions are satisfied refer to timing 3 in Figure 18 17 the CAN module can enter the operation mode it has requested Until the CAN module enters this operation mode it stays in the initialization mode Completion t...

Page 758: ...function is not defined by the CAN protocol ISO 11898 When using this func tion thoroughly evaluate its effect on the network system 6 Initializing CAN module error counter register CnERC in initialization mode If it is necessary to initialize the CAN module error counter register CnERC and CAN module information register CnINFO for debugging or evaluating a program they can be initialized to the ...

Page 759: ...AN protocol specifica tion Time segment 2 is equivalent to phase segment 2 Figure 18 18 Segment setting Notes 1 IPT Information Processing Time 2 TQ Time Quanta Reference The CAN protocol specification defines the segments constituting the data bit time as shown in Figure18 19 Table 18 15 Segment setting Segment name Settable range Notes on setting to conform to CAN specification Time segment 1 TS...

Page 760: ... delay of the output buffer CAN bus and input buffer The length of this segment is set so that ACK is returned before the start of phase segment 1 Time of prop segment Delay of output buffer 2 Delay of CAN bus Delay of input buffer This segment compensates for an error of data bit time The longer this segment the wider the permissible range but the slower the communication speed Phase segment 1 Pr...

Page 761: ...nsmitting node a Hardware synchronization This synchronization is established when the receiving node detects the start of frame in the inter frame space When a falling edge is detected on the bus that TQ means the sync segment and the next segment is the prop segment In this case synchronization is established regardless of SJW Figure 18 20 Adjusting synchronization of data bit Start of frame Int...

Page 762: ...hase error Negative If the edge is after the sample point phase error If phase error is positive Phase segment 1 is lengthened by specified SJW If phase error is negative Phase segment 2 is shortened by specified SJW The sample point of the data of the receiving node moves relatively due to the discrepancy in the baud rate between the transmitting node and receiving node Figure 18 21 Re synchroniz...

Page 763: ...ller User s Manual U16580EE3V1UD00 18 4 Connection with Target System The CAN module has to be connected to the CAN bus using an external transceiver Figure 18 22 Connection to CAN bus CAN module Transceiver CTxDn CRxDn CANL CANH ...

Page 764: ...ddresses given in the following tables are offsets to the programmable peripheral area base address PBA The setting of BPC is fixed to 8FFBH This setting defines the programmable peripheral area base address PBA 03FE C000H Table 18 17 lists all base addresses used throughout this chapter In the following CnRBaseAddr respectively CnMBaseAddr are used for the base address names for CAN channel n Tab...

Page 765: ...CANn module bit rate prescaler register CnBRP CANn module bit rate register CnBTR CANn module last in pointer register CnLIPT CANn module receive history list register CnRGPT CANn module last out pointer register CnLOPT CANn module transmit history list register CnTGPT CANn module time stamp register CnTS Message buffer registers CANn message data byte 01 register m CnMDATA01m CANn message data by...

Page 766: ...bal automatic block transmission delay register CnGMABTD 00H 040H CAN n module mask 1 register CnMASK1L Undefined 042H CnMASK1H Undefined 044H CAN n module mask 2 register CnMASK2L Undefined 046H CnMASK2H Undefined 048H CAN n module mask 3 register CnMASK3L Undefined 04AH CnMASK3H Undefined 04CH CAN n module mask 4 register CnMASK4L Undefined 04EH CnMASK4H Undefined 050H CAN n module control regis...

Page 767: ...x20H 6H CAN n message data byte 67 register m CnMDATA67m Undefined mx20H 6H CAN n message data byte 6 register m CnMDATA6m Undefined mx20H 7H CAN n message data byte 7 register m CnMDATA7m Undefined mx20H 8H CAN n message data length register m CnMDLCm 0000 xxxxB mx20H 9H CAN n message configuration register m CnMCONFm Undefined mx20H AH CAN n message identifier register m CnMIDLm Undefined mx20H ...

Page 768: ...ar OPMODE2 Clear OPMODE1 Clear OPMODE0 51H Set CCERC Set AL 0 Set PSMODE1 Set PSMODE0 Set OPMODE2 Set OPMODE1 Set OPMODE0 50H CnCTRL R CCERC AL VALID PS MODE1 PS MODE0 OP MODE2 OP MODE1 OP MODE0 51H 0 0 0 0 0 0 RSTAT TSTAT 52H CnLEC W 0 0 0 0 0 0 0 0 52H CnLEC R 0 0 0 0 0 LEC2 LEC1 LEC0 53H CnINFO 0 0 0 BOFF TECS1 TECS0 RECS1 RECS0 54H CnERC TEC7 to TEC0 55H REC7 to REC0 56H CnIE W 0 0 Clear CIE5 ...

Page 769: ... 0 0 0 64H CnTGPT R 0 0 0 0 0 0 THPM TOVF 65H TGPT7 to TGPT0 66H CnTS W 0 0 0 0 0 Clear TSLOCK Clear TSSEL Clear TSEN 67H 0 0 0 0 0 Set TSLOCK Set TSSEL Set TSEN 66H CnTS R 0 0 0 0 0 TSLOCK TSSEL TSEN 67H 0 0 0 0 0 0 0 0 68H to FFH Access prohibited reserved for future use Note Base address CnRBaseAddr Table 18 22 CAN module register bit configuration 2 2 Address offsetNote Symbol Bit 7 15 Bit 6 1...

Page 770: ...data byte 2 3H CnMDATA3m Message data byte 3 4H CnMDATA45m Message data byte 4 5H Message data byte 5 4H CnMDATA4m Message data byte 4 5H CnMDATA5m Message data byte 5 6H CnMDATA67m Message data byte 6 7H Message data byte 7 6H CnMDATA6m Message data byte 6 7H CnMDATA7m Message data byte 7 8H CnMDLCm 0 MDLC3 MDLC2 MDLC1 MDLC0 9H CnMCONFm OWS RTR MT2 MT1 MT0 0 0 MA0 AH CnMIDLm ID7 ID6 ID5 ID4 ID3 I...

Page 771: ...ANn module time stamp register CnTS CANn message control register CnMCTRLm All the 16 bits in the above registers can be read via the usual method Use the procedure described in Figure 18 23 below to set or clear the lower 8 bits in these registers Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits refer to the bit status after set clear o...

Page 772: ...it Setting Clearing Operations 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Clear 7 Clear 6 Clear 5 Clear 4 Clear 3 Clear 2 Clear 1 Clear 0 Set 0 7 Clear 0 7 Status of bit n after bit set clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change ...

Page 773: ...hen the GOM bit is set to 1 Caution To request forced shut down the GOM bit must be cleared to 0 in a subsequent immediately following access after the EFSD bit has been set to 1 If access to another register including reading the CnGMCTRL register is executed without clearing the GOM bit immediately after the EFSD bit has been set to 1 the EFSD bit is forcibly cleared to 0 and the forced shut dow...

Page 774: ...t always separately 15 14 13 12 11 10 9 8 CnGMCTRL 0 0 0 0 0 0 Set EFSD Set GOM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear GOM Set EFSD EFSD bit setting 0 No change in EFSD bit 1 EFSD bit set to 1 Set GOM Clear GOM GOM bit setting 0 1 GOM bit cleared to 0 1 0 GOM bit set to 1 Other than above No change in GOM bit ...

Page 775: ... After reset 0FH R W Address CnRBaseAddr 002H 7 6 5 4 3 2 1 0 CnGMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0 CCP3 CCP2 CCP1 CCP1 CAN module system clock fCANMOD 0 0 0 0 fCAN 1 0 0 0 1 fCAN 2 0 0 1 0 fCAN 3 0 0 1 1 fCAN 4 0 1 0 0 fCAN 5 0 1 0 1 fCAN 6 0 1 1 0 fCAN 7 0 1 1 1 fCAN 8 1 0 0 0 fCAN 9 1 0 0 1 fCAN 10 1 0 1 0 fCAN 11 1 0 1 1 fCAN 12 1 1 0 0 fCAN 13 1 1 0 1 fCAN 14 1 1 1 0 fCAN 15 1 1 1 1 fCAN 16 Defa...

Page 776: ...n Do not set the ABTTRG bit ABTTRG 1 in the initialization mode If the ABTTRG bit is set in the initialization mode the operation is not guaranteed after the CAN module has entered the normal operation mode with ABT Do not set the ABTTRG bit 1 while the CnCTRL TSTAT bit is set 1 Confirm TSTAT 0 directly in advance before setting ABTTRG bit After reset 0000H R W Address CnRBaseAddr 006H 15 14 13 12...

Page 777: ... 0 0 0 0 0 Clear ABTTRG Set ABTCLR Automatic block transmission engine clear request bit 0 The automatic block transmission engine is in idle status or under operation 1 Request to clear the automatic block transmission engine After the automatic block transmission engine has been cleared automatic block transmission is started from message buffer 0 by setting the ABTTRG bit to 1 Set ABTTRG Clear ...

Page 778: ...he ABT message is actually transmitted onto the CAN bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an ABT message message buffers 8 to 31 is made After reset 00H R W Address CnRBaseAddr 008H 7 6 5 4 3 2 1 0 CnGMABTD 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0 ABTD3 ABTD2 ABTD1 ABTD0 Data frame interval during automatic block transmi...

Page 779: ...2 CMID1 CMID0 15 14 13 12 11 10 9 8 CnMASK1H 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 After reset Undefined R W Address CnMASK2L CnRBaseAddr 044H CnMASK2H CnRBaseAddr 046H 15 14 13 12 11 10 9 8 CnMASK2L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 1...

Page 780: ...dr 04CH CnMASK4H CnRBaseAddr 04EH 15 14 13 12 11 10 9 8 CnMASK4L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 7 6 5 4 3 2 1 0 CMID7 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 15 14 13 12 11 10 9 8 CnMASK4H 0 0 0 CMID28 CMID27 CMID26 CMID25 CMID24 7 6 5 4 3 2 1 0 CMID23 CMID22 CMID21 CMID20 CMID19 CMID18 CMID17 CMID16 CMID28 to CMID0 Mask pattern setting of ID bit 0 The ID bits of the messa...

Page 781: ...space Notes 1 The TSTAT bit is set to 1 under the following conditions timing The SOF bit of a transmit frame is detected 2 The TSTAT bit is cleared to 0 under the following conditions timing During transition to bus off state On occurrence of arbitration loss in transmit frame On detection of recessive level at the second bit of the interframe space On transition to the initialization mode at the...

Page 782: ...state because in receive only mode no acknowledge is generated 4 To clear the VALID bit set the Clear VALID bit to 1 first and confirm that the VALID bit is cleared If it is not cleared perform clearing processing again Cautions 1 Transition to and from the CAN stop mode must be made via CAN sleep mode A request for direct transition to and from the CAN stop mode is ignored 2 The MBON flag of CnGM...

Page 783: ...ve only mode 1 0 0 Single shot mode 1 0 1 Self test mode Other than above Setting prohibited 15 14 13 12 11 10 9 8 CnCTRL Set CCERC Set AL 0 Set PSMODE 1 Set PSMODE 0 Set OPMODE 2 Set OPMODE 1 Set OPMODE 0 7 6 5 4 3 2 1 0 0 Clear AL Clear VALID Clear PSMODE 1 Clear PSMODE 0 Clear OPMODE 2 Clear OPMODE 1 Clear OPMODE 0 Set CCERC Setting of CCERC bit 1 CCERC bit is set to 1 Other than above CCERC bi...

Page 784: ...ODE0 Setting of OPMODE0 bit 0 1 OPMODE0 bit is cleared to 0 1 0 OPMODE0 bit is set to 1 Other than above OPMODE0 bit is not changed Set OPMODE1 Clear OPMODE1 Setting of OPMODE1 bit 0 1 OPMODE1 bit is cleared to 0 1 0 OPMODE1 bit is set to 1 Other than above OPMODE1 bit is not changed Set OPMODE2 Clear OPMODE2 Setting of OPMODE2 bit 0 1 OPMODE2 bit is cleared to 0 1 0 OPMODE2 bit is set to 1 Other ...

Page 785: ...gnored After reset 00H R W Address CnLEC CnRBaseAddr 052H 7 6 5 4 3 2 1 0 CnLEC 0 0 0 0 0 LEC2 LEC1 LEC0 LEC2 LEC1 LEC0 Last CAN protocol error information 0 0 0 No error 0 0 1 Stuff error 0 1 0 Form error 0 1 1 ACK error 1 0 0 Bit error The CAN module tried to transmit a recessive level bit as part of a transmit message except the arbitration field but the value on the CAN bus is a dominant level...

Page 786: ...r more TECS1 TECS0 Transmission error counter status bit 0 0 The value of the transmission error counter is less than that of the warning level 96 0 1 The value of the transmission error counter is in the range of the warning level 96 to 127 1 0 Undefined 1 1 The value of the transmission error counter is in the range of the error passive or bus off status 128 RECS1 RECS0 Reception error counter s...

Page 787: ... 11 10 9 8 CnERC REPS REC6 REC5 REC4 REC3 REC2 REC1 REC0 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REPS Reception error passive status bit 0 The reception error counter is not the error passive range 128 1 The reception error counter is in the error passive range 128 REC6 to REC0 Reception error counter bit 0 to 127 Number of reception errors These bits reflect the status of the rece...

Page 788: ...egister CINTSx is enabled 15 14 13 12 11 10 9 8 CnIE 0 0 Set CIE5 Set CIE4 Set CIE3 Set CIE2 Set CIE1 Set CIE0 7 6 5 4 3 2 1 0 0 0 Clear CIE5 Clear CIE4 Clear CIE3 Clear CIE2 Clear CIE1 Clear CIE0 Set CIE5 Clear CIE5 Setting of CIE5 bit 0 1 CIE5 bit is cleared to 0 1 0 CIE5 bit is set to 1 Other than above CIE5 bit is not changed Set CIE4 Clear CIE4 Setting of CIE4 bit 0 1 CIE4 bit is cleared to 0...

Page 789: ... CIE1 Clear CIE1 Setting of CIE1 bit 0 1 CIE1 bit is cleared to 0 1 0 CIE1 bit is set to 1 Other than above CIE1 bit is not changed Set CIE0 Clear CIE0 Setting of CIE0 bit 0 1 CIE0 bit is cleared to 0 1 0 CIE0 bit is set to 1 Other than above CIE0 bit is not changed ...

Page 790: ...0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 CINTS5 to CINTS0 CAN interrupt status bit 0 No related interrupt source event is pending 1 A related interrupt source event is pending Interrupt status bit Related interrupt source event CINTS5 Wakeup interrupt from CAN sleep modeNote CINTS4 Arbitration loss interrupt CINTS3 CAN protocol error interrupt CINTS2 CAN error status...

Page 791: ...k Caution The CnBRP register can be write accessed only in the initialization mode After reset FFH R W Address CnBRP CnRBaseAddr 05AH 7 6 5 4 3 2 1 0 CnBRP TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 TQPRS7 to TQPRS0 CAN protocol layer base system clock fTQ 0 fCANMOD 1 1 fCANMOD 2 n fCANMOD n 1 255 fCANMOD 256 default value CCP3 CCP2 Prescaler CANn module bit rate prescaler register Cn...

Page 792: ...3 12 11 10 9 8 CnBTR 0 0 SJW1 SJW0 0 TSEG22 TSEG21 TSEG20 7 6 5 4 3 2 1 0 0 0 0 0 TSEG13 TSEG12 TSEG11 TSEG10 SJW1 SJW0 Length of synchronization jump width 0 0 1TQ 0 1 2TQ 1 0 3TQ 1 1 4TQ default value TSEG22 TSEG21 TSEG20 Length of time segment 2 0 0 0 1TQ 0 0 1 2TQ 0 1 0 3TQ 0 1 1 4TQ 1 0 0 5TQ 1 0 1 6TQ 1 1 0 7TQ 1 1 1 8TQ default value Data bit time DBT Time segment 1 TSEG1 Phase segment 2 Ph...

Page 793: ...o an operation mode therefore the read value of the CnLIPT register is undefined TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 0 0 0 0 Setting prohibited 0 0 0 1 2TQNote 0 0 1 0 3TQNote 0 0 1 1 4TQ 0 1 0 0 5TQ 0 1 0 1 6TQ 0 1 1 0 7TQ 0 1 1 1 8TQ 1 0 0 0 9TQ 1 0 0 1 10TQ 1 0 1 0 11TQ 1 0 1 1 12TQ 1 1 0 0 13TQ 1 1 0 1 14TQ 1 1 1 0 15TQ 1 1 1 1 16TQ default value After reset Undefined R Addres...

Page 794: ...d RHPMNote 1 Receive history list pointer match 0 The receive history list has at least one message buffer number that has not been read 1 The receive history list has no message buffer numbers that have not been read ROVFNote 2 Receive history list overflow bit 0 All the message buffer numbers that have not been read are preserved All the numbers of the message buffers in which a new data frame o...

Page 795: ...et to 1 after the CAN module has changed from the initialization mode to an operation mode therefore the read value of the CnLOPT register is undefined After reset Undefined R Address CnLOPT CnRBaseAddr 062H 7 6 5 4 3 2 1 0 CnLOPT LOPT7 LOPT6 LOPT5 LOPT4 LOPT3 LOPT2 LOPT1 LOPT0 LOPT7 to LOPT0 Last out pointer of transmit history list LOPT 0 to 31 When the CnLOPT register is read the contents of th...

Page 796: ...ntents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last THPMNote 1 Transmit history pointer match 0 The transmit history list has at least one message buffer number that has not been read 1 The transmit history list has no message buffer numbers that have not been read TOVFNote 2 Transmit history list overflow bit 0 All the message buffer numbe...

Page 797: ...10 9 8 CnTS 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 TSLOCK TSSEL TSEN TSLOCK Time stamp lock function enable bit 0 Time stamp lock function stopped The TSOUT signal is toggled each time the selected time stamp capture event occurs 1 Time stamp lock function enabled The TSOUT signal is toggled each time the selected time stamp capture event occurs However the TSOUT output signal is locked when a ...

Page 798: ... Set TSEN 7 6 5 4 3 2 1 0 0 0 0 0 0 Clear TSLOCK Clear TSSEL Clear TSEN Set TSLOCK Clear TSLOCK Setting of TSLOCK bit 0 1 TSLOCK bit is cleared to 0 1 0 TSLOCK bit is set to 1 Other than above TSLOCK bit is not changed Set TSSEL Clear TSSEL Setting of TSSEL bit 0 1 TSSEL bit is cleared to 0 1 0 TSSEL bit is set to 1 Other than above TSSEL bit is not changed Set TSEN Clear TSEN Setting of TSEN bit ...

Page 799: ...ATA0 3 MDATA0 2 MDATA0 1 MDATA0 0 7 6 5 4 3 2 1 0 CnMDATA1m MDATA1 7 MDATA1 6 MDATA1 5 MDATA1 4 MDATA1 3 MDATA1 2 MDATA1 1 MDATA1 0 15 14 13 12 11 10 9 8 CnMDATA23m MDATA23 15 MDATA23 14 MDATA23 13 MDATA23 12 MDATA23 11 MDATA23 10 MDATA23 9 MDATA23 8 7 6 5 4 3 2 1 0 MDATA23 7 MDATA23 6 MDATA23 5 MDATA23 4 MDATA23 3 MDATA23 2 MDATA23 1 MDATA23 0 7 6 5 4 3 2 1 0 CnMDATA2m MDATA2 7 MDATA2 6 MDATA2 5 ...

Page 800: ...ATA4 3 MDATA4 2 MDATA4 1 MDATA4 0 7 6 5 4 3 2 1 0 CnMDATA5m MDATA5 7 MDATA5 6 MDATA5 5 MDATA5 4 MDATA5 3 MDATA5 2 MDATA5 1 MDATA5 0 15 14 13 12 11 10 9 8 CnMDATA67m MDATA67 15 MDATA67 14 MDATA67 13 MDATA67 12 MDATA67 11 MDATA67 10 MDATA67 9 MDATA67 8 7 6 5 4 3 2 1 0 MDATA67 7 MDATA67 6 MDATA67 5 MDATA67 4 MDATA67 3 MDATA67 2 MDATA67 1 MDATA67 0 7 6 5 4 3 2 1 0 CnMDATA6m MDATA6 7 MDATA6 6 MDATA6 5 ...

Page 801: ... to CAN registers overview on page 766 7 6 5 4 3 2 1 0 CnMDLCm 0 0 0 0 MDLC3 MDLC2 MDLC1 MDLC0 MDLC3 MDLC2 MDLC1 MDLC0 Data length of transmit receive message 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 Setting prohibited If these bits are set during transmission 8 byte data is transmitted re...

Page 802: ...ven if a remote frame whose ID matches has been received from the CAN bus with the RTR bit of the transmit message buffer set to 1 to transmit a remote frame that remote frame is not received or stored interrupt generated DN flag set the MDLC0 to MDLC3 bits updated and recorded to the receive history list After reset Undefined R W Address refer to CAN registers overview on page 766 7 6 5 4 3 2 1 0...

Page 803: ...into ID28 to ID11 bit positions MA0 Message buffer assignment bit 0 Message buffer not used 1 Message buffer used After reset Undefined R W Address refer to CAN registers overview on page 766 15 14 13 12 11 10 9 8 CnMIDLm ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 15 14 13 12 11 10 9 8 CnMIDHm IDE 0 0 ID28 ID27 ID26 ID25 ID24 7 6 5 4 3 2 1 0 ID23 ID22 ID2...

Page 804: ...CAN module is not updating the message buffer reception and storage 1 The CAN module is updating the message buffer reception and storage MOWNote Message buffer overwrite status bit 0 The message buffer is not overwritten by a newly received data frame 1 The message buffer is overwritten by a newly received data frame IE Message buffer interrupt request enable bit 0 Receive message buffer Valid me...

Page 805: ...N module cannot write to the message buffer 1 Writing the message buffer by software is ignored except a write access to the RDY TRQ DN and MOW bits The CAN module can write to the message buffer 15 14 13 12 11 10 9 8 CnMCTRLm 0 0 0 0 Set IE 0 Set TRQ Set RDY 7 6 5 4 3 2 1 0 0 0 0 Clear MOW Clear IE Clear DN Clear TRQ Clear RDY Clear MOW Setting of MOW bit 0 MOW bit is not changed 1 MOW bit is cle...

Page 806: ...ow the transmis sion abort process about clearing the RDY bit 0 for redefinition of the message buffer 5 Clear again when RDY bit is not cleared even if this bit is cleared 6 Be sure that RDY is cleared before writing to the other message buffer registers by checking the status of the RDY bit Set TRQ Clear TRQ Setting of TRQ bit 0 1 TRQ bit is cleared to 0 1 0 TRQ bit is set to 1 Other than above ...

Page 807: ...uffer while a message is being received or transmitted without affecting other transmission reception opera tions 1 To redefine message buffer in initialization mode Place the CAN module in the initialization mode once and then change the ID and control informa tion of the message buffer in the initialization mode After changing the ID and control information set the CAN module to an operation mod...

Page 808: ...ed If no ID and IDE are stored after redefinition redefine the message buffer again 2 When a message is transmitted the transmission priority is checked in accor dance with the ID IDE and RTR bits set to each transmit message buffer to which a transmission request was set The transmit message buffer having the highest priority is selected for transmission If the procedure in Reference Figure 18 26...

Page 809: ...tion mode see Reference Figure 18 36 on page 841 18 8 5 Resetting error counter CnERC of CAN module If it is necessary to reset the CAN module error counter CnERC and CAN module information register CnINFO when re initialization or forced recovery from the bus off status is made set the CCERC bit of the CnCTRL register to 1 in the initialization mode When this bit is set to 1 the CnERC and CnINFO ...

Page 810: ...is not stored in mes sage buffers with a lower priority This also applies when the message buffer with the highest priority is unable to store a message i e when DN 1 indicating that a message has already been received but rewriting is disabled because OWS 0 In this case the message is not actually stored in the candi date message buffer with the highest priority but neither is it stored in a mess...

Page 811: ...message buffer number is recorded to the RHL element indicated by the LIPT pointer Each time recording to the RHL has been completed the LIPT pointer is automatically incremented In this way the number of the message buffer that has received and stored a frame will be recorded chronologically The RGPT pointer is utilized as a read pointer that reads a recorded message buffer number from the RHL Th...

Page 812: ... entries the sequence of occurrence is maintained If more receptions occur without reading the RHL by the host processor complete sequence of receptions can not be recovered Figure 18 29 Receive history list 23 1 2 3 4 5 6 7 Receive history list RHL 23 1 2 3 4 5 6 7 Receive history list RHL Last in message pointer LIPT 23 0 1 2 3 4 5 6 7 23 1 2 3 4 5 6 7 0 22 0 0 22 22 22 Message buffer 7 Message ...

Page 813: ...all messages that have a standard format ID in which bits ID27 to ID25 are 0 and bits ID24 and ID22 are 1 are to be stored in message buffer 14 The procedure for this example is shown below 1 Identifier to be stored in message buffer Note x don t care 2 Identifier to be configured in message buffer 14 example Using CnMIDL14 and CnMIDH14 registers Notes 1 ID with the ID27 to ID25 bits cleared to 0 ...

Page 814: ...xample if a data block consists of k messages k message buffers are initialized for reception of the data block The IE bit in message buffers 0 to k 2 is cleared to 0 interrupts disabled and the IE bit in message buffer k 1 is set to 1 interrupts enabled In this case a reception completion interrupt occurs when a message has been received and stored in mes sage buffer k 1 indicating that MBRB has ...

Page 815: ... matches the ID of a message buffer that satisfies the above conditions The DLC 3 0 bit string in the CnMDLCm register store the received DLC value The CnMDATA0m to CnMDATA7m registers in the data area are not updated data before reception is saved The DN bit of the CnMCTRLm register is set to 1 The CINTS1 bit of the CnINTS register is set to 1 if the IE bit in the CnMCTRLm register of the mes sag...

Page 816: ...ission priority is controlled by the identifier ID Figure 18 30 Message processing example After the transmit message search the transmit message with the highest priority of the transmit mes sage buffers that have a pending transmission request message buffers with the TRQ bit set to 1 in advance is transmitted If a new transmission request is set the transmit message buffer with the new transmis...

Page 817: ...The transmit history list THL function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent The THL consists of storage elements equivalent to up to seven messages the last out message pointer LOPT with the corre sponding CnLOPT register and the transmit history list get pointer TGPT with the corresponding CnT GPT regis...

Page 818: ...es the value of the TGPT pointer the THPM bit is cleared In other words the numbers of the unread message buffers exist in the THL If the LOPT pointer is incremented and matches the value of the TGPT pointer minus 1 the TOVF bit transmit history list overflow of the CnTGPT register is set to 1 This indicates that the THL is full of message buffer numbers that have not been read If a new message is...

Page 819: ... request TRQ is auto matically set while successive transmission is being executed The delay time to be inserted is defined by the CnGMABTD register The unit of the delay time is DBT data bit time DBT depends on the set ting of the CnBRP and CnBTR registers Among transmit objects within the ABT area the priority of the transmission ID is not evaluated The data of message buffers 0 to 7 are sequent...

Page 820: ...he mode is changed from the initialization mode to the ABT mode 4 Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode with ABT Otherwise the operation is not guaranteed 5 The CnGMABTD register is used to set the delay time that is inserted in the period from completion of the preceding ABT message to setting of the TRQ bit for the next ABT message when t...

Page 821: ...ansmitted message buffer for details refer to the process in Reference Figure 18 47 on page 852 If the TRQ bit is cleared to 0 when clearing the ABTTRG bit is requested the internal ABT pointer is incre mented 1 and points to the next message buffer in the ABT area for details refer to the proc ess in Reference Figure 18 48 on page 853 Caution Be sure to abort ABT by clearing ABTTRG bit to 0 The o...

Page 822: ...and at the same time a message is received in a mes sage box the sleep mode request is not cancelled but is executed right after message stor age has been finished This may result in AFCAN being in sleep mode while the CPU would execute the RX interrupt routine Therefore the interrupt routine must check the access to the message buffers as well as reception history list registers by using the MBON...

Page 823: ... submitted 2 Status in CAN sleep mode The CAN module is in the following state after it enters the CAN sleep mode The internal operating clock is stopped and the power consumption is minimized The function to detect the falling edge of the CAN reception pin CRXDn remains in effect to wake up the CAN module from the CAN bus To wake up the CAN module from the CPU data can be written to the PSMODE 1 ...

Page 824: ...ed the CAN module has to be released from sleep mode by software first before entering the initialization mode Caution 1 Be aware that the release of CAN sleep mode by CAN bus event and thus the wake up interrupt may happen at any time even right after requesting sleep mode if a CAN bus event occurs 2 Always reset the PSMODE 1 0 bits to 00B when waking up from CAN sleep mode before accessing any o...

Page 825: ...CPU in a power saving mode to reduce the power consumption By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination the CPU can be woken up from the power saving sta tus by the CAN bus Here is an example for using the power saving modes First put the CAN module in the CAN sleep mode PSMODE 1 0 01B Next put the CPU in the power saving mo...

Page 826: ...es supply of the internal clocks including the clock to the CAN module after the oscillation stabilization time has elapsed and starts instruction execution The CAN module is immediately released from the CAN sleep mode when clock supply is resumed and returns to the normal operation mode PSMODE 00B ...

Page 827: ...is interrupt is generated when the transmission reception error counter is at the warning level or in the error passive or bus off state 2 This interrupt is generated when a stuff error form error ACK error bit error or CRC error occurs 3 This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a falling edge is detected at the CAN reception pin CAN bus transitio...

Page 828: ...reception is indicated by setting the VALID bit of the CnCTRL register 1 Figure 18 32 CAN module terminal connection in receive only mode In the receive only mode no message frames can be transmitted from the CAN module to the CAN bus Transmit requests issued for message buffers defined as transmit message buffers are held pend ing In the receive only mode the CAN transmission pin CTXDn in the CAN...

Page 829: ...abled As a consequence the TRQ bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events Successful transmission of the message frame Arbitration loss while sending the message frame Error occurrence while sending the message frame The events arbitration loss and error occurrence can be distinguished by checking the CINTS4 and CINTS3 bits of the CnINTS re...

Page 830: ... 2 Each signals are not generated to outside but generated into the CAN module Operation Mode Transmissi on of data remote frame Transmiss ion of ACK Transmiss ion of error overload frame Transmissi on retry Automatic Block Transmissi on ABT Set of VALID bit Store Data to message buffer Initialization Mode No No No No No No No Normal Operation Mode Yes Yes Yes Yes No Yes Yes Normal Operation Mode ...

Page 831: ...les its level upon occurrence of the selected event during data frame reception in Reference Figure 18 34 the SOF is used as the trigger event source To capture a timer value by using the TSOUT signal the capture timer unit must detect the capture signal at both the rising edge and falling edge This time stamp function is controlled by the TSLOCK bit of the CnTS register When TSLOCK is cleared to ...

Page 832: ...AN Controller as follows 5TQ SPT sampling point 17 TQ SPT TSEG1 1 8 TQ DBT data bit time 25 TQ DBT TSEG1 TSEG2 1TQ TSEG2 SPT 1 TQ SJW synchronization jump width 4TQ SJW DBT SPT 4 TSEG1 16 3 Setting value of TSEG1 3 0 15 1 TSEG2 8 0 Setting value of TSEG2 2 0 7 Notes 1 TQ 1 fTQ fTQ CAN protocol layer basic system clock 2 TSEG1 3 0 Bits 3 to 0 of CAN bit rate register CnBTR 3 TSEG2 2 0 Bits 10 to 8 ...

Page 833: ...22 1 9 6 6 1110 101 72 7 22 1 11 5 5 1111 100 77 3 21 1 4 8 8 1011 111 61 9 21 1 6 7 7 1100 110 66 7 21 1 8 6 6 1101 101 71 4 21 1 10 5 5 1110 100 76 2 21 1 12 4 4 1111 011 81 0 20 1 3 8 8 1010 111 60 0 20 1 5 7 7 1011 110 65 0 20 1 7 6 6 1100 101 70 0 20 1 9 5 5 1101 100 75 0 20 1 11 4 4 1110 011 80 0 20 1 13 3 3 1111 010 85 0 19 1 2 8 8 1001 111 57 9 19 1 4 7 7 1010 110 63 2 19 1 6 6 6 1011 101 ...

Page 834: ...73 3 15 1 8 3 3 1010 010 80 0 15 1 10 2 2 1011 001 86 7 15 1 12 1 1 1100 000 93 3 14 1 1 6 6 0110 101 57 1 14 1 3 5 5 0111 100 64 3 14 1 5 4 4 1000 011 71 4 14 1 7 3 3 1001 010 78 6 14 1 9 2 2 1010 001 85 7 14 1 11 1 1 1011 000 92 9 13 1 2 5 5 0110 100 61 5 13 1 4 4 4 0111 011 69 2 13 1 6 3 3 1000 010 76 9 13 1 8 2 2 1001 001 84 6 13 1 10 1 1 1010 000 92 3 12 1 1 5 5 0101 100 58 3 12 1 3 4 4 0110 ...

Page 835: ... 1 4 3 3 0110 010 72 7 11 1 6 2 2 0111 001 81 8 11 1 8 1 1 1000 000 90 9 10 1 1 4 4 0100 011 60 0 10 1 3 3 3 0101 010 70 0 10 1 5 2 2 0110 001 80 0 10 1 7 1 1 0111 000 90 0 9 1 2 3 3 0100 010 66 7 9 1 4 2 2 0101 001 77 8 9 1 6 1 1 0110 000 88 9 8 1 1 3 3 0011 010 62 5 8 1 3 2 2 0100 001 75 0 8 1 5 1 1 0101 000 87 5 7Note 1 2 2 2 0011 001 71 4 7Note 1 4 1 1 0100 000 85 7 6Note 1 1 2 2 0010 001 66 7...

Page 836: ... 2 1100 001 87 5 500 1 00000000 16 1 13 1 1 1101 000 93 8 500 2 00000001 8 1 1 3 3 0011 010 62 5 500 2 00000001 8 1 3 2 2 0100 001 75 0 500 2 00000001 8 1 5 1 1 0101 000 87 5 250 2 00000001 16 1 1 7 7 0111 110 56 3 250 2 00000001 16 1 3 6 6 1000 101 62 5 250 2 00000001 16 1 5 5 5 1001 100 68 8 250 2 00000001 16 1 7 4 4 1010 011 75 0 250 2 00000001 16 1 9 3 3 1011 010 81 3 250 2 00000001 16 1 11 2 ...

Page 837: ... 0100 001 75 0 83 3 12 00001011 8 1 5 1 1 0101 000 87 5 33 3 10 00001001 24 1 7 8 8 1110 111 66 7 33 3 10 00001001 24 1 9 7 7 1111 110 70 8 33 3 12 00001011 20 1 7 6 6 1100 101 70 0 33 3 12 00001011 20 1 9 5 5 1101 100 75 0 33 3 15 00001110 16 1 7 4 4 1010 011 75 0 33 3 15 00001110 16 1 9 3 3 1011 010 81 3 33 3 16 00001111 15 1 6 4 4 1001 011 73 3 33 3 16 00001111 15 1 8 3 3 1010 010 80 0 33 3 20 ...

Page 838: ...1 5 5 5 1001 100 68 8 500 2 00000001 16 1 7 4 4 1010 011 75 0 500 2 00000001 16 1 9 3 3 1011 010 81 3 500 2 00000001 16 1 11 2 2 1100 001 87 5 500 2 00000001 16 1 13 1 1 1101 000 93 8 500 4 00000011 8 1 3 2 2 0100 001 75 0 500 4 00000011 8 1 5 1 1 0101 000 87 5 250 4 00000011 16 1 3 6 6 1000 101 62 5 250 4 00000011 16 1 5 5 5 1001 100 68 8 250 4 00000011 16 1 7 4 4 1010 011 75 0 250 4 00000011 16 ...

Page 839: ...7 7 1111 110 70 8 33 3 24 00010111 20 1 9 5 5 1101 100 75 0 33 3 24 00010111 20 1 11 4 4 1110 011 80 0 33 3 30 00011101 16 1 7 4 4 1010 011 75 0 33 3 30 00011101 16 1 9 3 3 1011 010 81 3 33 3 32 00011111 15 1 8 3 3 1010 010 80 0 33 3 32 00011111 15 1 10 2 2 1011 001 86 7 33 3 37 00100100 13 1 6 3 3 1000 010 76 9 33 3 37 00100100 13 1 8 2 2 1001 001 84 6 33 3 40 00100111 12 1 5 3 3 0111 010 75 0 33...

Page 840: ...p the program referring to recommended processing procedure in this chapter Figure 18 35 Initialization Note OPMODE Normal operation mode normal operation mode with ABT receive only mode sin gle shot mode self test mode START Set CnGMCS register Set CnBRP register CnBTR register Set CnIE register Set CnMASK register Initialize message buffers Set CnCTRL register set OPMODE bit END Set CnGMCTRL reg...

Page 841: ...et a message buffer Note OPMODE Normal operation mode normal operation mode with ABT receive only mode sin gle shot mode self test mode START Set CnBRP register CnBTR register Set CnIE register Set CnMASK register Set CnCTRL register Set OPMODE END Clear OPMODE INIT mode No Yes Set CCERC bit Yes No Initialize message buffers CnERC and CnINFO register clear START Set CnBRP register CnBTR register S...

Page 842: ... to 0 Reference Figure 18 38 shows the processing for a receive message buffer MT 2 0 bits of CnMCONFm register 001B to 101B START Set CnMCONFm register END RDY 1 No Yes Clear RDY bit RDY 0 Set CnMIDHm register CnMIDLm register Transmit message buffer Clear CnMDATAm register Set CnMCTRLm register Set RDY bit Set CnMDLCm register No No Yes Yes START Set CnMCONFm register END RDY 1 No Yes Clear RDY ...

Page 843: ...ption by waiting additional 4 CAN data bits Reference Figure 18 39 shows the processing for a transmit message buffer during transmission MT 2 0 bits of CnMCONFm register 000B START Set message buffers END RDY 1 No Yes Clear RDY bit RDY 0 RSTAT 0 or VALID 1 Note1 No Clear VALID bit Set RDY bit Yes Yes No Wait for 4 CAN data bitsNote2 START Set message buffers END RDY 1 No Yes Clear RDY bit RDY 0 R...

Page 844: ...CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Remote frame Data frame Transmit abort process Clear RDY bit Transmit Set TRQ bit Yes Wait for 1CAN data bits No START END RDY 0 No Yes Data frame or remote frame Set RDY bit Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set Cn...

Page 845: ... remote frame Set RDY bit Yes No Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set TRQ bit Remote frame Data frame START END TRQ 0 No Yes Clear RDY bit RDY 0 Data frame or remote frame Set RDY bit Yes No Set CnMDATAxm register Set CnMDLCm regist...

Page 846: ...t should be set to 1 after the TSTAT bit is cleared to 0 Checking the TSTAT bit and setting the ABTTRG bit to 1 must be processed consecutively START Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers END ABTTRG 0 No Yes Clear RDY bit RDY 0 Set RDY bit Yes No Set ABTTRG bit Set all ABT transmit messages TSTAT 0 Yes No Yes No START Set C...

Page 847: ...ncel any sleep mode requests before processing TX interrupts START END Clear RDY bit RDY 0 Data frame or remote frame Set RDY bit Yes No Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set TRQ bit Remote frame Data frame Transmit completion interr...

Page 848: ...inconsistent Consider to scan all con figured transmit buffers for completed transmissions START END TOVF 1 Data frame or remote frame Set RDY bit Yes No Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set TRQ bit Remote frame Data frame Transmit ...

Page 849: ...Consider to scan all con figured transmit buffers for completed transmissions START END TOVF 1 Data frame or remote frame Set RDY bit Yes No Set CnMDATAxm register Set CnMDLCm register Clear RTR bit of CnMCONFm register Set CnMIDLm and CnMIDHm registers Set CnMDLCm register Set RTR bit of CnMCONFm Set CnMIDLm and CnMIDHm registers Set TRQ bit Remote frame Data frame Read CnTGPT register Clear TOVF...

Page 850: ...n be periodically checked by a user application or can be checked after the transmit completion interrupt 4 Do not execute any new transmission request including in the other message buffers while transmission abort processing is in progress Figure 18 46 Transmission Abort Processing Except for ABT Transmission Normal Operation Mode with ABT START Read CnLOPT register END No Yes Clear TRQ bit TSTA...

Page 851: ... including in the other message buffers while transmission abort processing is in progress START Read CnLOPT register END No Yes Clear TRQ bit TSTAT 0 Message buffer to be aborted matches CnLOPT register No Wait for 11 CAN data bits Transmission successful Transmit abort request was successful Yes No ABTTRG 0 Clear ABTTRG bit Yes START Read CnLOPT register END No Yes Clear TRQ bit TSTAT 0 Message ...

Page 852: ...quest after the ABTTRG bit is cleared after ABT mode is aborted following the procedure shown in Reference Figure 18 47 or Reference Figure 18 48 When clearing a trans mission request in an area other than the ABT area follow the procedure shown in Reference Figure 18 45 on page 850 START END No Clear ABTTRG bit ABTTRG 0 Transmission start No Clear TRQ bit of message buffer whose transmission was ...

Page 853: ...p mode request after the ABTTRG bit is cleared after ABT mode is stopped following the procedure shown in Reference Figure 18 47 or Reference Figure 18 48 When clearing a trans mission request in an area other than the ABT area follow the procedure shown in Reference Figure 18 45 on page 850 START END No Clear ABTTRG bit ABTTRG 0 Transmission start pointer clear No Transmit abort Yes Set ABTCLR bi...

Page 854: ...had been executed If MBON is detected to be cleared at any check the actions and results of the processing have to be discarded and processed again after MBON is set again It is recommended to cancel any sleep mode requests before processing RX interrupts START END No Read CnMDATAxm CnMDLCm CnMIDLm and CnMIDHm registers DN 0 AND MUC 0 Read CnLIPT register Yes Generation of receive completion inter...

Page 855: ...er MBON is set again It is recommended to cancel any sleep mode requests before processing RX interrupts 2 If ROVF was set once the receive history list is inconsistent Consider to scan all config ured receive buffers for receptions START Clear ROVF bit No ROVF 1 Read CnRGPT register Yes Generation of receive completion interrupt Clear DN bit Read CnMDATAxm CnMDLCm CnMIDLm CnMIDHm registers DN 0 A...

Page 856: ...ve to be discarded and pro cessed again after MBON is set again 2 If ROVF was set once the receive history list is inconsistent Consider to scan all config ured receive buffers for receptions START CINTS1 1 Yes No Clear CINTS1 bit Clear ROVF bit No ROVF 1 Read CnRGPT register Yes Clear DN bit Read CnMDATAxm CnMDLCm CnMIDLm CnMIDHm registers DN 0 AND MUC 0Note RHPM 1 END Yes Yes No Correct data is ...

Page 857: ...et PSMODE1 bit PSMODE1 1 CAN stop mode Request CAN sleep mode again Clear OPMODE Yes No Yes No Access to registers other than the CnCTRL and CnGMCTRL registers INIT mode Yes No Clear CINTS5 bit Set CnCTRL register Set OPMODE START when PSMODE 1 0 00B PSMODE0 1 Set PSMODE0 bit CAN sleep mode CAN sleep mode END Yes No Set PSMODE1 bit PSMODE1 1 CAN stop mode CAN stop mode Request CAN sleep mode again...

Page 858: ...top mode Clear PSMODE1 bit CAN sleep mode Clear CINTS5 bit Clear PSMODE0 bit Releasing CAN sleep mode by CAN bus activity Dominant edge on CAN detected START END Releasing CAN sleep mode by user Clear PSMODE0 bit CAN stop mode Clear PSMODE1 bit CAN sleep mode Clear CINTS5 bit Clear PSMODE0 bit Releasing CAN sleep mode by CAN bus activity Dominant edge on CAN detected ...

Page 859: ...ts 128 times on the bus again Remark OPMODE Normal operation mode normal operation mode with ABT receive only mode single shot mode self test mode START Access to registers other than CnCTRL and CnGMCTRL registers Set CnCTRL register Clear OPMODE Forced recovery from bus off END BOFF 1 Yes No Set CCERC bit Set CnCTRL register Set OPMODE Wait for recovery from bus off Set CnCTRL register Set OPMODE...

Page 860: ...bus again Remark OPMODE Normal operation mode normal operation mode with ABT receive only mode single shot mode self test mode START Access to registers other than CnCTRL and CnGMCTRL registers Set CnCTRL register Clear OPMODE Forced recovery from bus off END BOFF 1 Yes No Set CCERC bit Set CnCTRL register Set OPMODE Wait for recovery from bus off Set CnCTRL register Set OPMODE Yes No Clear all TR...

Page 861: ...bit START GOM 0 Clear GOM bit END Yes No INIT mode Shutdown successful GOM 0 EFSD 0 START GOM 0 Clear GOM bit END Yes No INIT mode Shutdown successful GOM 0 EFSD 0 Shutdown successful GOM 0 EFSD 0 START GOM 0 Clear GOM bit END Yes No Shutdown successful GOM 0 EFSD 0 Set EFSD bit Must be a subsequent write START GOM 0 Clear GOM bit END Yes No Shutdown successful GOM 0 EFSD 0 Shutdown successful GOM...

Page 862: ...state read CnLEC register No Yes No Error interrupt Check CAN module state read CnINFO register Clear CINTS3 bit CINTS4 1 Clear CINTS4 bit No Yes START Clear CINTS2 bit CINTS2 1 CINTS3 1 END Yes Check CAN protocol error state read CnLEC register No Yes No Error interrupt Check CAN module state read CnINFO register Clear CINTS3 bit CINTS4 1 Clear CINTS4 bit No Yes ...

Page 863: ...CPU standby mode please check if the CAN sleep mode has been reached However after check of the CAN sleep mode until the CPU is set in the CPU standby mode the CAN sleep mode may be cancelled by wakeup from CAN bus STAR T END SetPS MODE0 bit Yes No CINTS5 bit 1 PSMODE0 bit 1 MBON bit 0 No Yes Yes No Clear CINT S5 bit CANsleep mode SetCP U standb y mode ...

Page 864: ... interrupts Caution The CAN stop mode can only be released by writing 01B to the PSMODE 1 0 bit of the CnCTRL register and not by a change in the CAN bus state STAR T END SetPS MODE0 bit PSMODE0 bit 1 MBON bit 0 Yes No PSMODE1 bit 1 No Yes CANstop mode Yes No SetPS MODE1 bit Clear CINT S5 bit Note SetCP U standb y mode CANsleep mode ...

Page 865: ...iguration 1 Random number register RNG The RNG register is a 16 bit register that holds the random number After read access to this register a certain time is required to generate the next random number If a consecutive read access takes place before the new random number has been generated the read access will be delayed The RNG register is read only in 16 bit units Reset input causes an undefine...

Page 866: ...in time to generate the next random number Moreover when a consecutive read access takes place before the new random number has been generated the read access will be delayed The access timing to the RNG register is as follows Single read access to RNG register when VSWC register 13H Consecutive read access to RNG register Tsingle 102 5 fXX 1 Tconsecutive Tsingle 1024 fXX 1 ...

Page 867: ...utput direction can be specified in 1 bit units Noise removal circuit provided for external interrupts and timer inputs Edge detect function for external interrupts rising falling both edges Security features for port 5 and 6 shared as 3 phase PWM timer outputs Emergency shut off feature Software protection feature ...

Page 868: ... CT and CD The port configuration is shown in Figure 20 1 below Figure 20 1 Port Configuration Port 0 Port 1 Port 3 Port 4 P00 P04 P10 P17 P20 P27 P30 P37 P40 P45 Port 2 Port 5 Port 6 P50 P57 P60 P67 P70 P75 P80 P86 Port 7 Port 8 P96 Port 9 P90 Port 10 Port AL Port AH Port DL Port DH Port CS Port CM Port CT Port CD P100 P102 PAL0 PAL15 PAH0 PAH5 PDL0 PDL15 PDH0 PDH15 PCS4 PCM0 PCT4 PCT5 PCD2 PCD5 ...

Page 869: ... I O port Serial interface I O CSIB0 CSIB1Note 1E 2 4C Port 5 P50 to P57 8 bit I O port Timer output TMR0 11 13 Port 6 P60 to P67 8 bit I O port Timer I O TMR1 12 13 14 Port 7 P70 to P75 6 bit I O port Timer I O TMT0 TMT1 6 8 Port 8 P80 to P86 7 bit I O port Serial interface I O CSI30 1S 2 4 5 7 Port 9 P90 to P96 7 bit I O port Serial interface I O CSI31Note 1S 2 4 5 7 Port 10 P100 to P102 3 bit I...

Page 870: ...t types 1 Port type 1 Port type 1 provides a general purpose I O port with peripheral output function Figure 20 2 Port Type 1 Remark m port number n port bit number Selector Selector Selector Peripheral output function Address NPB Pmn Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN ...

Page 871: ...pose I O port with peripheral output function This type is similar to port type 1 but features a Schmitt trigger input buffer characteristic Figure 20 3 Port Type 1S Remark m port number n port bit number Selector Selector Selector Peripheral output function Address NPB Pmn Pnm PMnm PMCnm WRPMC WRPM WRPORT RDIN ...

Page 872: ...al output function In peripheral function mode a control signal is provided to enable or disable the output Figure 20 4 Port Type 1E Remark m port number n port bit number Selector Selector Selector Peripheral output function Selector Peripheral output function enable 1 enabled 0 Hi Z Address NPB Pmn Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN ...

Page 873: ...D00 4 Port type 2 Port type 2 provides a general purpose I O port with peripheral input function Figure 20 5 Port Type 2 Remark m port number n port bit number Selector Selector Address Peripheral input function NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 874: ...ose I O port with peripheral input function This type is similar as port type 2 but in port mode the peripheral input function is forced to high level Figure 20 6 Port Type 2A Remark m port number n port bit number Selector Selector Address Peripheral input function NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 875: ... a general purpose I O port with peripheral input function This type is similar to type 2 but features CMOS input buffer characteristic Figure 20 7 Port Type 2C Remark m port number n port bit number Selector Selector Address Peripheral input function NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 876: ...User s Manual U16580EE3V1UD00 7 Port type 3 Port type 3 provides a general purpose input port with NMI interrupt input function Figure 20 8 Port Type 3 Filter Edge detection NMI ESN0 ESN1 Address Selector NPB P00 WRINTM RDIN RDINTM ...

Page 877: ...ipheral I O function Peripheral output enable is controlled by the corresponding peripheral function Figure 20 9 Port Type 4 Remark m port number n port bit number Address Peripheral function output control Peripheral output function Peripheral input function Selector Selector Selector NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 878: ...pheral I O function Peripheral output enable is controlled by the corresponding peripheral function Figure 20 10 Port Type 4C Remark m port number n port bit number Address Peripheral function output control Peripheral output function Peripheral input function Selector Selector Selector NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 879: ...peripheral I O function If the peripheral input function is disabled the value of the peripheral input signal is fixed to low level Figure 20 11 Port Type 5 Remark m port number n port bit number Address Peripheral output function Peripheral input function Selector Selector Selector NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 880: ... purpose I O port with peripheral output function and digitally filtered peripheral input function Figure 20 12 Port Type 6 Remark m port number n port bit number Address Peripheral output function Peripheral input function Selector Selector Selector Filter CLK NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 881: ...ripheral output function and external interrupt input capability Figure 20 13 Port Type 7 Remark m port number n port bit number x external interrupt number Address Peripheral output function Selector Selector Selector Filter Edge detection INTx ESx0 ESx1 Address Selector NPB Pmn PMmn PMCmn WRPMC WRPM WRINTM WRPORT RDIN RDINTM Pmn ...

Page 882: ...y filtered peripheral input function and external interrupt input capability Figure 20 14 Port Type 8 Remark m port number n port bit number x external interrupt number Selector Selector Address Peripheral input function Filter Edge detection ESx0 ESx1 Address Selector CLK INTx NPB Pmn PMmn PMCmn WRPMC WRPM WRINTM WRPORT RDIN RDINTM Pmn ...

Page 883: ...nput noise filter is bypassed for peripheral input function Remark The peripheral input signal provided by port type 9 is fixed to high level if peripheral input function is disabled Figure 20 15 Port Type 9 Remark m port number n port bit number x external interrupt number Selector Selector Address Peripheral input function Edge detection ESx0 ESx1 Address Selector INTx NPB Pmn PMmn PMCmn WRPMC W...

Page 884: ...10 Port type10 provides a general purpose I O port with digitally filtered peripheral input function Figure 20 16 Port Type 10 Remark m port number n port bit number Selector Selector Address Peripheral input function Filter CLK NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 885: ...but all port registers are write protected against unintended change due to system or software malfunction Writing to the port registers of type 11 is only possible immediately after a write access to the PRCMD register Figure 20 17 Port Type 11 Remark m port number n port bit number Selector Selector Selector Peripheral output function Address PRCMD NPB Pmn PMmn PMCmn WRPMC WRPM WRPORT RDIN Pmn ...

Page 886: ...c type 1S but all port registers are write protected against unintended change due to system or software malfunction Writing to the port registers of type 12 is only possible immediately after a write access to the PRCMD register Figure 20 18 Port Type 12 Remark m port number n port bit number Address Peripheral output function Peripheral input function Selector Selector Selector Filter CLK PRCMD ...

Page 887: ...nction This type is similar to the port logic type 11 but the output driver can be shut down immediately by the ESOx input signal x 0 1 All port registers are write protected against unintended change due to system or software malfunction Writing to the port registers of type 13 is only possible immediately after a write access to the PRCMD register ...

Page 888: ... bit number x index of ESO signal x 0 1 WRPMC WRPM WRPORT RDIN Peripheral output function Selector Selector Selector Address PMmn PMCmn Pmn Pmn NPB Analog filter ESOx analog delay 10 ns ESOxED0 ESOxED1 ESOxEN ESOxST PRCMD WRPESCn WRESOSTn 1 set request by active level 1 set request by active edge pulse width 10ns ...

Page 889: ...ion and peripheral output function This type is similar to the port type 12 but the output driver can be shut down immediately by the ESOx input signal x 0 1 All port registers are write protected against unintended change due to system or software malfunction Writing to the port registers of type 13 is only possible immediately after a write access to the PRCMD register ...

Page 890: ... ESO signal x 0 1 Peripheral input function PRCMD WRPMC WRPM WRPORT RDIN Peripheral output function Pmn Address Selector Selector Selector Filter CLK Pmn PMmn PMCmn NP B Analog filter ESOx analog delay 10 ns 1 set request by active level 1 set request by active edge pulse width 10ns ESOxED0 ESOxED1 ESOxEN ESOxST PRCMD WRPESCn WRESOSTn ...

Page 891: ...al interrupt input function This type is similar as port type 3 Difference is the additional filtered peripheral input function support Figure 20 21 Port Type 15 Remark m port number n port bit number x external interrupt number Edge detection INTx ESx0 ESx1 Address Selector NPB Pnm WRINTM RDIN RDINTM CLK Peripheral input function Filter ...

Page 892: ...external interrupt input function This type is similar as port type 15 Difference is the analog filter instead of digital filter Figure 20 22 Port Type 15A Remark m port number n port bit number x external interrupt number Edge detection INTx ESx0 ESx1 Address Selector NPB Pnm WRINTM RDIN RDINTM Peripheral input function Analog filter ...

Page 893: ...ster Port mode AL low byte PMALL R W R W 0xFF 0xFFFFF020 Port mode register Port mode AL PMAL R W 0xFFFF 0xFFFFF021 Port mode register Port mode AL high byte PMALH R W R W 0xFF 0xFFFFF022 Port mode register Port mode AH PMAH R W R W 0xFF 0xFFFFF024 Port mode register Port mode DL low byte PMDLL R W R W 0xFF 0xFFFFF024 Port mode register Port mode DL PMDL R W 0xFFFF 0xFFFFF025 Port mode register Po...

Page 894: ...0xFFFFF40A Port register port 5 P5 R W R W undef 0xFFFFF40C Port register port 6 P6 R W R W undef 0xFFFFF40E Port register port 7 P7 R W R W undef 0xFFFFF410 Port register port 8 P8 R W R W undef 0xFFFFF412 Port register port 9 P9 R W R W undef 0xFFFFF414 Port register port 10 P10 R W R W undef 0xFFFFF422 Port mode register port 1 PM1 R W R W 0xFF 0xFFFFF424 Port mode register port 2 PM2 R W R W 0...

Page 895: ...F44E Port mode control register port 7 PMC7 R W R W 0x00 0xFFFFF450 Port mode control register port 8 PMC8 R W R W 0x00 0xFFFFF452 Port mode control register port 9 PMC9 R W R W 0x00 0xFFFFF454 Port mode control register port 10 PMC10 R W R W 0x00 Table 20 2 Peripheral Registers of I O Ports 3 3 Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits ...

Page 896: ...8 Bits 16 Bits 0xFFFFF880 Interrupt mode register 0 INTM0 R W R W 0x00 0xFFFFF882 Interrupt mode register 1 INTM1 R W R W 0x00 0xFFFFF884 Interrupt mode register 2 INTM2 R W R W 0x00 0xFFFFF886 Interrupt mode register 3 INTM3 R W R W 0x00 0xFFFFF888 Port 5 emergency shut off control register PESC5 R W R W 0x00 0xFFFFF88A Port 5 emergency shut off control register ESOST5 R W R W 0x00 0xFFFFF88C Por...

Page 897: ...nly in 8 bit or 1 bit units Reset input causes an undefined register content Figure 20 23 Port Register 0 P0 Remark n 0 to 4 Port Alternate Function Remark Port Type Port 0 P00 NMI Non maskable interrupt 3 P01 INTP0 ESO0 External interrupt request input Emergency output shut off input TMR0 15A P02 INTP1 ESO1 External interrupt request input Emergency output shut off input TMR1 P03 INTP2 ADTRG0 Ext...

Page 898: ...e control register 1 PMC1 Table 20 5 Alternate Function Pins and Port Types of Port 1 Port Alternate Function Remark Port Type Port 1 P10 TIP00 TEVTP1 TOP00 Timer input TMP0 TMP1 Timer output TMP0 6 P11 TIP01 TTRGP1 TOP01 Timer input TMP0 TMP1 Timer output TMP0 P12 TIP10 TTRGP0 TOP10 Timer input TMP0 TMP1 Timer output TMP1 P13 TIP11 TEVTP0 TOP11 Timer input TMP0 TMP1 Timer output TMP1 P14 TIP20 TE...

Page 899: ...register that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 25 Port Mode Register 1 PM1 Remark n 0 to 7 After reset Undefined R W Address FFFFF402H 7 6 5 4 3 2 1 0 P1 P17 P16 P15 P14 P13 P12 P11 P10 P1n Input Output Data Control of Pin P1n 0 Input mode Low level is input Output mode Low level is outpu...

Page 900: ...MC11 PMC10 PMC17 Port Control Mode Specification of Pin P17 0 I O port mode 1 Control mode alternate function PMC16 Port Control Mode Specification of Pin P16 0 I O port mode 1 Control mode alternate function PMC15 Port Control Mode Specification of Pin P15 0 I O port mode 1 Control mode alternate function PMC14 Port Control Mode Specification of Pin P14 0 I O port mode 1 Control mode alternate fu...

Page 901: ...de 1 Control mode alternate function PMC11 Port Control Mode Specification of Pin P11 0 I O port mode 1 Control mode alternate function PMC10 Port Control Mode Specification of Pin P10 0 I O port mode 1 Control mode alternate function PM13 Function 0 TOP11 output mode 1 TIP11 TEVTP0 input mode PM12 Function 0 TOP10 output mode 1 TIP10 TTRGP0 input mode PM11 Function 0 TOP01 output mode 1 TIP01 TTR...

Page 902: ...able 20 6 Alternate Function Pins and Port Types of Port 2 Port Alternate Function Remark Port Type Port 2 P20 TIP40 TEVTP5 TOP40 Timer input TMP4 TMP5 Timer output TMP4 output 6 P21 TIP41 TTRGP5 TOP41 Timer input TMP4 TMP5 Timer output TMP4 output P22 TIP50 TTRGP4 TOP50 Timer input TMP4 TMP5 Timer output TMP5 output P23 TIP51 TEVTP4 TOP51 Timer input TMP4 TMP5 Timer output TMP5 output P24 TIP60 T...

Page 903: ...or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 28 Port Mode Register 2 PM2 Remark n 0 to 7 PM2 is an 8 bit read write register It is the port mode register of Port 2 PM2 determines the input or output direction of the respective port pin After reset Undefined R W Address FFFFF404H 7 6 5 4 3 2 1 0 P2 P27 P26 P25 P24 P23 P22 P21 P20 P2n Input Output Data Control o...

Page 904: ...MC21 PMC20 PMC27 Port Control Mode Specification of Pin P27 0 I O port mode 1 Control mode alternate function PMC26 Port Control Mode Specification of Pin P26 0 I O port mode 1 Control mode alternate function PMC25 Port Control Mode Specification of Pin P25 0 I O port mode 1 Control mode alternate function PMC24 Port Control Mode Specification of Pin P24 0 I O port mode 1 Control mode alternate fu...

Page 905: ...de 1 Control mode alternate function PMC21 Port Control Mode Specification of Pin P21 0 I O port mode 1 Control mode alternate function PMC20 Port Control Mode Specification of Pin P20 0 I O port mode 1 Control mode alternate function PM23 Function 0 TOP51 output mode 1 TIP51 TEVTP4 input mode PM22 Function 0 TOP50 output mode 1 TIP50 TTRGP4 input mode PM21 Function 0 TOP41 output mode 1 TIP41 TTR...

Page 906: ...MC3 The external interrupt request inputs shared with the input port functionality of port 3 are always enabled in input port mode Table 20 7 Alternate Function Pins and Port Types of Port 3 Note Alternate function not available on μPD70F3447 Port Alternate Function Remark Port Type Port 3 P30 RXDC0 INTP4 Serial interface UARTC0 input External interrupt request input 9 P31 TXDC0 Serial interface U...

Page 907: ...that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 31 Port Mode Register 3 PM3 Remark n 0 to 7 After reset Undefined R W Address FFFFF406H 7 6 5 4 3 2 1 0 P3 P37 P36 P35 P34 P33 P32 P31 P30 P3n Input Output Data Control of Pin P3n 0 Input mode Low level is input Output mode Low level is output 1 Input...

Page 908: ...ort mode the corresponding peripheral input signal alternate function is forced to high level internally 2 Alternate function not available on μPD70F3447 After reset 00H R W Address FFFFF446H 7 6 5 4 3 2 1 0 PMC3 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC37 Port Control Mode Specification of Pin P37 0 I O port mode 1 FCTXD1 output modeNote 2 PMC36 Port Control Mode Specification of Pin P3...

Page 909: ... mode PMC32 Port Control Mode Specification of Pin P32 0 I O port modeNote 1 RXDC1 input mode External interrupt request input mode INTP5 PMC31 Port Control Mode Specification of Pin P31 0 I O port mode 1 TXDC0 output mode PMC30 Port Control Mode Specification of Pin P30 0 I O port modeNote 1 RXDC0 input mode External interrupt request input mode INTP4 PM32 Function 0 Output mode 1 Input mode Exte...

Page 910: ... or control mode for alternate function can be specified in 1 bit units by using the port mode control register 4 PMC4 Table 20 8 Alternate Function Pins and Port Types of Port 4 Note Alternate function not available on μPD70F3447 Port Alternate Function Remark Port Type Port 4 P40 SIB0 Serial interface CSIB0 input 2 P41 SOB0 Serial interface CSIB0 output 1E P42 SCKB0 Serial interface CSIB0 I O 4C...

Page 911: ...ster that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 34 Port Mode Register 4 PM4 Remark n 0 to 5 After reset Undefined R W Address FFFFF408H 7 6 5 4 3 2 1 0 P4 0 0 P45 P44 P43 P42 P41 P40 P4n Input Output Data Control of Pin P4n 0 Input mode Low level is input Output mode Low level is output 1 Inpu...

Page 912: ...on μPD70F3447 After reset 00H R W Address FFFFF448H 7 6 5 4 3 2 1 0 PMC4 0 0 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 PMC45 Port Control Mode Specification of Pin P45 0 I O port mode 1 SCKB1 I O mode input or output mode controlled by CSIB1 Note PMC44 Port Control Mode Specification of Pin P44 0 I O port mode 1 SOB1 output modeNote PMC43 Port Control Mode Specification of Pin P43 0 I O port mode 1 SIB1...

Page 913: ... using the port mode control register 5 PMC5 Emergency shut off by ES0 input signal of output buffers P51 to P56 can be controlled by port emergency shut off control register 5 PESC5 and emergency shut off status register 5 ESOST5 Security feature to protect the timer output signals of TMR0 from unintended CPU interference Registers P5 PM5 PMC5 PESC5 and ESOST5 can only be written in a special seq...

Page 914: ...at specifies the input or output mode Writing to the PM5 register is only possible in a specific sequence where a write access to the command register PRCMD must be made before a write access to the PM5 register is accepted A read operation in between the two write operations is allowed i e read modify write is possible on register PM5 For details refer to 3 4 8 Specific registers This register ca...

Page 915: ... the PMC5 register is accepted A read operation in between the two write operations is allowed i e read modify write is possible on register PMC5 For details refer to 3 4 8 Specific registers on page 139 This register can be read or written in 8 bit or 1 bit units Reset input sets this register to 00H Figure 20 38 Port Mode Control Register 5 PMC5 Remark n 0 to 7 After reset 00H R W Address FFFFF4...

Page 916: ...put shut off function may be unintentionally triggered or a trigger event may be lost Remarks 1 The output buffers of ports P51 to P56 are forcibly disabled high impedance output as long as ESO0EN and ESO0ST are set to 1 2 Setup of the emergency shut off function must be performed in the following sequence Otherwise the output shut off function may be unintentionally triggered or a trigger event m...

Page 917: ...4 8 Specific registers This register can be read or written in 8 bit or 1 bit units Reset input sets this register to 00H Figure 20 40 Port Emergency Shut Off Status Register 5 ESOST5 Remarks 1 Writing the emergency shut off status flag ESO0ST is only possible if the ES0EN bit of the PESC5 register is cleared 0 2 The ESO0ST flag can only be cleared by CPU to 0 Setting the ESO0ST flag to 1 is not p...

Page 918: ...r 6 PMC6 Emergency shut off by ES0 input signal of output buffers P61 to P66 can be controlled by port emergency shut off control register 6 PESC6 and emergency shut off status register 6 ESOST6 Security feature to protect the timer output signals of TMR0 from unintended CPU interference Registers P6 PM6 PMC6 PESC6 and ESOST6 can only be written in a special sequence Table 20 10 Alternate Function...

Page 919: ...at specifies the input or output mode Writing to the PM6 register is only possible in a specific sequence where a write access to the command register PRCMD must be made before a write access to the PM6 register is accepted A read operation in between the two write operations is allowed i e read modify write is possible on register PM6 For details refer to 3 4 8 Specific registers This register ca...

Page 920: ...to 3 4 8 Specific registers This register can be read or written in 8 bit or 1 bit units Reset input sets this register to 00H Figure 20 43 Port Mode Control Register 6 PMC6 1 2 After reset 00H R W Address FFFFF44CH 7 6 5 4 3 2 1 0 PMC6 PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PMC67 Port Control Mode Specification of Pin P67 0 I O port mode 1 Control mode PMC66 Port Control Mode Specificati...

Page 921: ...e Specification of Pin P62 0 I O port mode 1 Control mode PMC61 Port Control Mode Specification of Pin P61 0 I O port mode 1 Control mode PMC60 Port Control Mode Specification of Pin P60 0 I O port mode 1 Control mode PM63 Function 0 TOR13 output mode 1 TIR12 input mode PM62 Function 0 TOR12 output mode 1 TIR11 input mode PM61 Function 0 TOR11 output mode 1 TIR10 input mode PM63 Function 0 TOR10 o...

Page 922: ...ut off function may be unintentionally triggered or a trigger event may be lost Remarks 1 The output buffers of ports P61 to P66 are forcibly disabled high impedance output as long as ESO1EN and ESO1ST are set to 1 2 Setup of the emergency shut off function must be performed in the following sequence Otherwise the output shut off function may be unintentionally triggered or a trigger event may be ...

Page 923: ...ecific registers on page 139 This register can be read or written in 8 bit or 1 bit units Reset input sets this register to 00H Figure 20 45 Port Emergency Shut Off Status Register 6 ESOST6 Remarks 1 Writing the emergency shut off status flag ESO1ST is only possible if the ES1EN bit of the PESC6 register is cleared 0 2 The ESO1ST flag can only be cleared by CPU to 0 Setting the ESO1ST flag to 1 is...

Page 924: ... control register 7 PMC7 The external interrupt request input shared with the input port functionality of port 7 is always enabled in input port mode Table 20 11 Alternate Function Pins and Port Types of Port 7 Port Alternate Function Remark Port Type Port 7 P70 TIT00 TEVT1 TOT00 Timer input TMT0 TMT1 Timer output TMT0 6 P71 TIT01 TTRGT1 TOT01 Timer input TMT0 TMT1 Timer output TMT0 P72 TECRT0 INT...

Page 925: ...ster that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 47 Port Mode Register 7 PM7 Remark n 0 to 5 After reset Undefined R W Address FFFFF40EH 7 6 5 4 3 2 1 0 P7 0 0 P75 P74 P73 P72 P71 P70 P7n Input Output Data Control of Pin P7n 0 Input mode Low level is input Output mode Low level is output 1 Inpu...

Page 926: ...PMC7 1 2 After reset 00H R W Address FFFFF44EH 7 6 5 4 3 2 1 0 PMC7 0 0 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC75 Port Control Mode Specification of Pin P75 0 I O port mode 1 Control mode PMC74 Port Control Mode Specification of Pin P74 0 I O port mode 1 Control mode PMC73 Port Control Mode Specification of Pin P73 0 I O port mode 1 Control mode PM75 Function 0 AFO output mode 1 TECRT1 input mode ...

Page 927: ...al interrupt request input mode INTP12 PMC71 Port Control Mode Specification of Pin P71 0 I O port mode 1 Control mode PMC70 Port Control Mode Specification of Pin P70 0 I O port mode 1 Control mode PM72 Function 0 Output mode 1 Input mode External interrupt request input mode INTP12 PM71 Function 0 TOT01 output mode 1 TIT01 TTRGT1 input mode PM70 Function 0 TOT00 output mode 1 TIT00 TEVTT1 input ...

Page 928: ...xternal interrupt request inputs shared with the input port functionality of port 8 are always enabled in input port mode Table 20 12 Alternate Function Pins and Port Types of Port 8 Port Alternate Function Remark Port Type Port 8 P80 SI30 Serial interface CSI30 input 2 P81 SO30 Serial interface CSI30 output 1S P82 SCK30 Serial interface CSI30 I O 4 P83 SCS300 INTP6 Serial interface CSI30 output E...

Page 929: ...r that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 50 Port Mode Register 8 PM8 Remark n 0 to 6 After reset Undefined R W Address FFFFF410H 7 6 5 4 3 2 1 0 P8 0 P86 P85 P84 P83 P82 P81 P80 P8n Input Output Data Control of Pin P8n 0 Input mode Low level is input Output mode Low level is output 1 Input...

Page 930: ...82 PMC81 PMC80 PMC86 Port Control Mode Specification of Pin P86 0 I O port mode 1 Control mode PMC85 Port Control Mode Specification of Pin P85 0 I O port mode 1 Control mode PMC84 Port Control Mode Specification of Pin P84 0 I O port mode 1 Control mode PM86 Function 0 SCS303 output mode 1 SSB0 input mode PM85 Function 0 Output mode 1 Input mode External interrupt request input mode INTP8 PM85 Fu...

Page 931: ...Port Control Mode Specification of Pin P82 0 I O port mode 1 SCK30 I O mode PMC81 Port Control Mode Specification of Pin P81 0 I O port mode 1 SO30 output mode PMC80 Port Control Mode Specification of Pin P80 0 I O port mode 1 SI30 input mode PM83 Function 0 Output 1 Input External interrupt request input mode INTP6 PM83 Function 0 SCS300 output mode 1 External interrupt request input mode INTP6 ...

Page 932: ... functionality of port 9 are always enabled in input port mode Table 20 13 Alternate Function Pins and Port Types of Port 9 Note Alternate function not available on μPD70F3447 Port Alternate Function Remark Port Type Port 9 P90 SI31Note Serial interface CSI31 inputNote 2 P91 SO31Note Serial interface CSI31 outputNote 1S P92 SCK31Note Serial interface CSI31 I ONote 4 P93 SCS310Note INTP9 Serial int...

Page 933: ...r that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 53 Port Mode Register 9 PM9 Remark n 0 to 6 After reset Undefined R W Address FFFFF412H 7 6 5 4 3 2 1 0 P9 0 P96 P95 P94 P93 P92 P91 P90 P9n Input Output Data Control of Pin P9n 0 Input mode Low level is input Output mode Low level is output 1 Input...

Page 934: ...t available Figure 20 54 Port Mode Control Register 9 PMC9 1 2 Note Alternate function not available on μPD70F3447 After reset 00H R W Address FFFFF452H 7 6 5 4 3 2 1 0 PMC9 0 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC96 Port Control Mode Specification of Pin P96 0 I O port mode 1 Control modeNote PMC95 Port Control Mode Specification of Pin P95 0 I O port mode 1 Control modeNote PM96 Function ...

Page 935: ...fication of Pin P92 0 I O port mode 1 SCK31 I O modeNote PMC91 Port Control Mode Specification of Pin P91 0 I O port mode 1 SO31 output modeNote PMC90 Port Control Mode Specification of Pin P90 0 I O port mode 1 SI31 input modeNote PM94 Function 0 Output mode 1 Input mode External interrupt request input mode INTP10 PM94 Function 0 SCS311 output mode 1 External interrupt request input mode INTP10 ...

Page 936: ...t mode register 10 PM10 Port mode or control mode for alternate function can be specified in 1 bit units by using the port mode control register 10 PMC10 Table 20 14 Alternate Function Pins and Port Types of Port 10 Note Alternate function not available on μPD70F3447 Port Alternate Function Remark Port Type Port 10 P100 TCLR0Note TICC00Note TOP81 Timer input ITENC0 Note Timer output TMP8 6 P101 TC...

Page 937: ... register that specifies the input or output mode This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 56 Port Mode Register 10 PM10 Remark n 0 to 2 After reset Undefined R W Address FFFFF414H 7 6 5 4 3 2 1 0 P10 0 0 0 0 0 P102 P101 P100 P10n Input Output Data Control of Pin P10n 0 Input mode Low level is input Output mode Low level is output...

Page 938: ...set PMC102 to 1 when PM102 is set 1 Figure 20 57 Port Mode Control Register 10 PMC10 Note Alternate function not available on μPD70F3447 After reset 00H R W Address FFFFF454H 7 6 5 4 3 2 1 0 PMC10 0 0 0 0 0 PMC102 PMC101 PMC100 PMC102 Port Control Mode Specification of Pin P102 0 I O port mode 1 Control mode PMC101 Port Control Mode Specification of Pin P101 0 I O port mode 1 TCUD0 input modeNote ...

Page 939: ...lternate function can be specified in 1 bit units by using the port mode control register AL PMCAL Table 20 15 Alternate Function Pins and Port Types of Port AL Note Alternate function not available on μPD70F3447 Caution On the μPD70F31187 in single chip mode 1 or in ROM less mode this port has exter nal address bus function only Reprogramming of port AL to port mode is not possi ble in these mode...

Page 940: ...Reset input causes an undefined register content Figure 20 58 Port Register AL PAL Remark n 0 to 15 After reset Undefined R W Address FFFFF000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PAL PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 PALH PALL After reset Undefined R W Address FFFFF000H 7 6 5 4 3 2 1 0 PALL PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 After reset U...

Page 941: ...it units Reset input sets this register to FFFFH Figure 20 59 Port Mode Register AL PMAL Remark n 0 to 15 After reset FFFFH R W Address FFFFF020H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMAL PMAL 15 PMAL 14 PMAL 13 PMAL 12 PMAL 11 PMAL 10 PMAL 9 PMAL 8 PMAL 7 PMAL 6 PMAL 5 PMAL 4 PMAL 3 PMAL 2 PMAL 1 PMAL 0 PMALH PMALL After reset FFH R W Address FFFFF020H 7 6 5 4 3 2 1 0 PMALL PMAL7 PMAL6 PMAL5 PMA...

Page 942: ...0H or 00H respectively In single chip mode 1 and ROM less mode μPD70F31187 only FFFFH or FFH respectively 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns FFFFH or FFH respectively 3 Alternate function not available on μPD70F3447 Remark n 0 to 15 After resetNote 1 0000H FFFFH R WNote 2 Address FFFFF040H 15 14 13 12 11 1...

Page 943: ...modes Reading and writing of the port register PAH and port mode register PMAH is possible but has no effect Reading of the port mode control regis ter PMCAH is possible and the result is always 3FH Writing of the port mode control register PMCAH is not possible 2 Control registers a Port register AH PAH The PAH register is an 8 bit register that controls reading the pin levels and writing the out...

Page 944: ...47 do not set PMCAHn bits to 1 since the corresponding alternate function is not available Figure 20 63 Port Mode Control Register AH PMCAH Notes 1 In single chip mode 0 00H In single chip mode 1 and ROM less mode μPD70F31187 only 3FH 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns 3FH 3 Alternate function not availabl...

Page 945: ...or alternate function can be specified in 1 bit units by using the port mode control register DL PMCDL Table 20 17 Alternate Function Pins and Port Types of Port DL Note Alternate function not available on μPD70F3447 Caution On the μPD70F31187 in single chip mode 1 or in ROM less mode this port has exter nal data bus function only Reprogramming of port DL to port mode is not possible in these mode...

Page 946: ...Reset input causes an undefined register content Figure 20 64 Port Register DL PDL Remark n 0 to 15 After reset Undefined R W Address FFFFF004H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDL PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLH PDLL After reset Undefined R W Address FFFFF004H 7 6 5 4 3 2 1 0 PDLL PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 After reset U...

Page 947: ...it units Reset input sets this register to FFFFH Figure 20 65 Port Mode Register DL PMDL Remark n 0 to 15 After reset FFFFH R W Address FFFFF024H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMDL PMDL 15 PMDL 14 PMDL 13 PMDL 12 PMDL 11 PMDL 10 PMDL 9 PMDL 8 PMDL 7 PMDL 6 PMDL 5 PMDL 4 PMDL 3 PMDL 2 PMDL 1 PMDL 0 PMDLH PMDLL After reset FFH R W Address FFFFF024H 7 6 5 4 3 2 1 0 PMDLL PMDL7 PMDL6 PMDL5 PMD...

Page 948: ...0 0000H or 00H respectively In single chip mode 1 and ROM less mode μPD70F31187 only FFFFH or FFH respectively 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns FFFFH or FFH respectively 3 Alternate function not available on μPD70F3447 Remark n 0 to 15 After resetNote 1 0000H FFFFH R WNote 2 Address FFFFF044H 15 14 13 12...

Page 949: ...r alternate function can be specified in 1 bit units by using the port mode control register DH PMCDH Table 20 18 Alternate Function Pins and Port Types of Port DH Note Alternate function not available on μPD70F3447 Caution On the μPD70F31187 in single chip mode 1 or in ROM less mode this port has exter nal data bus function only Reprogramming of port DH to port mode is not possible in these modes...

Page 950: ...Reset input causes an undefined register content Figure 20 67 Port Register DH PDH Remark n 0 to 15 After reset Undefined R W Address FFFFF006H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDH PDH15 PDH14 PDH13 PDH12 PDH11 PDH10 PDH9 PDH8 PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 PDHH PDHL After reset Undefined R W Address FFFFF006H 7 6 5 4 3 2 1 0 PDHL PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 After reset U...

Page 951: ...it units Reset input sets this register to FFFFH Figure 20 68 Port Mode Register DH PMDH Remark n 0 to 15 After reset FFFFH R W Address FFFFF026H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PMDH PMDH 15 PMDH 14 PMDH 13 PMDH 12 PMDH 11 PMDH 10 PMDH 9 PMDH 8 PMDH 7 PMDH 6 PMDH 5 PMDH 4 PMDH 3 PMDH 2 PMDH 1 PMDH 0 PMDHH PMDHL After reset FFH R W Address FFFFF026H 7 6 5 4 3 2 1 0 PMDHL PMDH7 PMDH6 PMDH5 PMD...

Page 952: ...H or 00H respectively In single chip mode 1 and ROM less mode μPD70F31187 only FFFFH or FFH respectively 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns FFFFH or FFH respectively 3 Alternate function not available on μPD70F3447 Remark n 0 to 15 After resetNote 1 0000H FFFFH R WNote 2 Address FFFFF046H 15 14 13 12 11 10...

Page 953: ...and writing of the port register PCS and port mode register PMCS is possible but has no effect Reading of the port mode control register PMCCS is possible and the result is always 1BH Writing of the port mode control register PMCCS is not possible 2 Control registers a Port register CS PCS The PCS register is an 8 bit register that controls reading the pin levels and writing the output levels of p...

Page 954: ...and single chip mode 1 Caution On μPD70F3447 do not set PMCCSn bits to 1 since the corresponding alternate func tion is not available Figure 20 72 Port Mode Control Register CS PMCCS Notes 1 In single chip mode 0 00H In single chip mode 1 and ROM less mode 1BH 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns 1BH 3 Alter...

Page 955: ...ding and writing of the port register PCT and port mode register PMCT is possible but has no effect Reading of the port mode control register PMCCT is possible and the result is always 30H Writing of the port mode control register PMCCT is not possible 2 Control registers a Port register CT PCT The PCT register is an 8 bit register that controls reading the pin levels and writing the output levels...

Page 956: ...put or output mode of port pins PCT4 and PCT5 This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 74 Port Mode Register CT PMCT After reset FFH R W Address FFFFF02AH 7 6 5 4 3 2 1 0 PMCT 1 1 PMCT5 PMCT4 1 1 1 1 PMCTn Input Output Mode Control of Pin PCTn in Port Mode 0 Output mode 1 Input mode ...

Page 957: ...lternate func tion is not available Figure 20 75 Port Mode Control Register CT PMCCT Notes 1 In single chip mode 0 00H In single chip mode 1 and ROM less mode 30H 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns 30H 3 Alternate function not available on μPD70F3447 Remark n 4 5 After resetNote 1 00H 3FH R WNote 2 Address...

Page 958: ...ding and writing of the port register PCM and port mode register PMCM is possible but has no effect Reading of the port mode control regis ter PMCCM is possible and the result is always 01H Writing of the port mode control register PMCCM is not possible 2 Control registers a Port register CM PCM The PCM register is an 8 bit register that controls reading the pin levels and writing the output level...

Page 959: ... of port pins PCM0 PCM1 PCM6 and PCM7 This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 77 Port Mode Register CM PMCM Remark n 0 1 6 7 After reset FFH R W Address FFFFF02CH 7 6 5 4 3 2 1 0 PMCM PMCM7 PMCM6 1 1 1 1 PMCM1 PMCM0 PMCMn Input Output Mode Control of Pin PCMn in Port Mode 0 Output mode 1 Input mode ...

Page 960: ... On μPD70F3447 do not set PMCCMn bits to 1 since the corresponding alternate function is not available Figure 20 78 Port Mode Control Register CM PMCCM Notes 1 In single chip mode 0 00H In single chip mode 1 and ROM less mode 01H 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns 01H 3 Alternate function not available on ...

Page 961: ...us function only Reprogramming of port CD to port mode is not possi ble in these modes Reading and writing of the port register PCD and port mode register PMCD is possible but has no effect Reading of the port mode control regis ter PMCCD is possible and the result is always 3CH Writing of the port mode control register PMCCD is not possible 2 Control registers a Port register CD PCD The PCD regis...

Page 962: ...ctions User s Manual U16580EE3V1UD00 Remark n 2 to 5 PCDn Input Output Data Control of Pin PCDn 0 Input mode Low level is input Output mode Low level is output 1 Input mode High level is input Output mode High level is output ...

Page 963: ...t mode of port pins PCD2 to PCD5 This register can be read or written in 8 bit or 1 bit units Reset input sets this register to FFH Figure 20 80 Port Mode Register CD PMCD Remark n 2 to 5 After reset FFH R W Address FFFFF02EH 7 6 5 4 3 2 1 0 PMCD 1 1 PMCD5 PMCD4 PMCD3 PMCD2 1 1 PMCDn Input Output Mode Control of Pin PCDn in Port Mode 0 Output mode 1 Input mode ...

Page 964: ...e 0 00H In single chip mode 1 and ROM less mode 3CH 2 On the μPD70F31187 in single chip mode 1 or in ROM less mode this register can not be written Reading is possible and returns 3CH 3 Alternate function not available on μPD70F3447 After resetNote 1 00H 3FH R WNote 2 Address FFFFF04EH 7 6 5 4 3 2 1 0 PMCCD 0 0 PMCCD5 PMCCD4 PMCCD3 PMCCD2 0 0 PMCCD5 Port Control Mode Specification of Pin PCD5 0 I ...

Page 965: ...50 ns fXX 64 MHz fXX 64 1 µs fXX 64 MHz Maskable Interrupt Forced output stop function TMR A D converter ADC P01 INTP0 ESO0 P02 INTP1 ESO1 Analog Delay 60 ns to 200 ns P03 INTP2 ADTRG0 P04 INTP3 ADTRG1 Digital delay 4 to 5 clocks fXX 16 250 ns fXX 64 MHz fXX 64 1 µs fXX 64 MHz Maskable Interrupt Asynchronous serial Interface UART C P30 RXDC0 INTP4 P32 RXDC1 INTP5 Maskable Interrupt Clocked serial ...

Page 966: ...21 TIP41 TTRGP5 TOP41 P22 TIP50 TTRGP4 TOP50 P23 TIP51 TEVTP4 TOP51 P24 TIP60 TEVTP7 TOP60 P25 TIP61 TTRGP7 TOP61 P26 TIP70 TTRGP6 TOP70 P27 TIP71 TEVTP6 TOP71 Digital delay 4 to 5 clocks fXX 16 250 ns fXX 64 MHz fXX 64 1 µs fXX 64 MHz Timer R TMR P60 TOR10 TTRGR1 P61 TOR11 TIR10 P62 TOR12 TIR11 P63 TOR13 TIR12 P64 TOR14 TIR13 P67 TOR17 TEVTR1 Timer T TMT P70 TIT00 TEVTT1 TOT00 P71 TIT01 TTRGT1 TO...

Page 967: ...23 TIP51 TEVTP4 TOP51 Pin group 6 P24 TIP60 TEVTP7 TOP60 P25 TIP61 TTRGP7 TOP61 P26 TIP70 TTRGP6 TOP70 P27 TIP71 TEVTP6 TOP71 Pin group 7 P60 TOR10 TTRGR1 P61 TOR11 TIR10 P62 TOR12 TIR11 P63 TOR13 TIR12 P64 TOR14 TIR13 P67 TOR17 TEVTR1 After reset 00H R W Address FFFFFtA0H 7 6 5 4 3 2 1 0 NRC NRC7 NRC6 NRC5 NRC4 NRC3 NRC2 NRC1 NRC0 NRC7 Noise elimination clock setting for pin group 7Note 0 fXX 16 ...

Page 968: ...TOT00 P71 TIT01 TTRGT1 TOT01 P72 TECRT0 INTP12 P73 TIT10 TTRGT0 TOT10 P74 TIT11 TEVTT0 TOT11 P75 TECRT1 AFO Cautions 1 If the input pulse lasts for the duration of 4 to 5 clocks it is undefined whether the pulse is detected as a valid edge or eliminated as noise So that the pulse is actually detected as a valid edge the same pulse level must be input for the duration of 5 clocks or more 2 If noise...

Page 969: ...969 Chapter 20 Port Functions User s Manual U16580EE3V1UD00 MEMO ...

Page 970: ...970 Chapter 20 Port Functions User s Manual U16580EE3V1UD00 ...

Page 971: ...l except the DCK DRST DMS DDI DDO RESET X2 VDD10 to VDD15 VSS10 to VSS15 VDD30 to VDD37 VSS30 to VSS37 CVDD CVSS AVDD AVREF0 AVREF1 AVSS0 and AVSS1 pins enter the high impedance state Therefore if an external device always requires a defined input level e g external memory a pull up or pull down resistor must be connected to each concerned output pin to prevent signal lines from floating If no res...

Page 972: ...ed using the oscillator output clock fX After 214 oscillator clocks fX the PLL output clock becomes the system clock fXX and the internal system reset is released synchronously to the system clock Figure 21 1 Reset Timing Remarks 1 If no clock is supplied to V850E PH2 i e the oscillator does not work the internal system reset will not be released independently from input level of the external RESE...

Page 973: ...of data stored in the internal RAM is checked by its parity bit A maskable interrupt INTPERR is generated if a parity mismatch is detected on iRAM read operation In this case the address of the erroneous data is latched in the RAMPADD register and the erroneous byte s are indicated in the RAMERR register Caution Ensure that all internal RAM data is initialized on a word 32 bit base by a write oper...

Page 974: ...n 8 bit or 1 bit units Reset input clears this register to 00H Figure 22 1 Internal RAM Parity Error Status Register RAMERR After reset 00H R W Address FFFFF4C0H 7 6 5 4 3 2 1 0 RAMERR 0 0 0 0 RAE3 RAE2 RAE1 RAE0 RAEn Internal RAM Parity Error Flag 0 No parity error detected in internal RAM 1 Parity error detected in internal RAM for byte position n Remark The RAEn bit can be both read and written...

Page 975: ...ter is read before the respective RAEn flag is set the read value might be invalid Figure 22 2 Internal RAM Parity Error Address Register RAMPADD After reset 8000H R W Address FFFFF4C2H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAMPADD 1 RAMPA DD14 RAMPA DD13 RAMPA DD12 RAMPA DD11 RAMPA DD10 RAMPA DD9 RAMPA DD8 RAMPA DD7 RAMPA DD6 RAMPA DD5 RAMPA DD4 RAMPA DD3 RAMPA DD2 0 0 RAMPAD14 to RAMPADD2 Intern...

Page 976: ...976 Chapter 22 Internal RAM Parity Check Function User s Manual U16580EE3V1UD00 MEMO ...

Page 977: ...manual 1 Debug interface This interface establishes communication with the host machine by using the DRST DCK DMS DDI and DDO signals via a N Wire type emulator The communication specifications of N Wire are used for this interface It does not support a boundary scan function 2 On chip debug On chip debugging can be performed by providing wiring and connectors for debugging on the target system Co...

Page 978: ...ing on the debugger used 8 Debug monitor function During debugging a memory space for debugging that differs from the user memory space is used background monitor format The user program can be executed starting from any address While execution of the user program is stopped the user resources such as memory and I O can be read or written and the user program can be downloaded 9 Mask function RESE...

Page 979: ...m pitch 20 pin general purpose connector as the emulator connector Connectors other than the KEL connector may not be supported depending on the emulator so when using a connector refer to the manual of the emulator used 23 2 1 KEL connector When the IE V850E1 CD NW is used use of the following connector is recommended Part number 8830E 026 170S Straight type 8830E 026 170L Right angle type Figure...

Page 980: ...ation of the emulator connector target system side and Table 23 1 shows the pin functions Figure 23 2 Pin Configuration of Emulator Connector on Target System Side Caution Design the board based on the dimensions of the connector when actually mounting the connector on the board Board edge Top View B12 A12 B2 A2 B13 A13 B1 A1 ...

Page 981: ...wed from the device side Pin No Pin Name I O Pin Function A1 Reserved 1 Connect to GND A2 Reserved 2 Connect to GND A3 Reserved 3 Connect to GND A4 Reserved 4 Connect to GND A5 Reserved 5 Connect to GND A6 Reserved 6 Connect to GND A7 DDI Input Data input for N Wire interface A8 DCK Input Clock input for N Wire interface A9 DMS Input Transfer mode select input for N Wire interface A10 DDO Output D...

Page 982: ...onnected to VSS3 via an internal pull down resistor Cautions 1 The DDO signal is 3 3 V output and the input level of the DDI DCK DMS and DRST signals is TTL level 2 A 3 3 V interface may not be supported so a level shifter may be required by some N Wire type emulators Refer to the manual of the emulator used Note that the IE V850E1 CD NW supports a 5 V interface V850E PH2 FLMD0 Reserved 1 Reserved...

Page 983: ...erefore do not use the device used in debugging for a mass production product 2 If a reset RESET signal input from the target system or reset input by an internal reset source occurs during RUN program execution the break function may malfunction 3 Even if reset is masked by using the mask function the I O buffers port pins etc are set to the reset state when the RESET signal is input 4 RESET sign...

Page 984: ...984 Chapter 23 On Chip Debug Function OCD User s Manual U16580EE3V1UD00 MEMO ...

Page 985: ...F3447 384 KB Block size μPD70F3481 128 blocks of 4 KB μPD70F3447 96 blocks of 4 KB Write voltage Erase write with single voltage Rewriting method Rewriting by communication with dedicated flash programmer via serial interface on board off board programming Rewriting flash memory by user program self programming 64 KB boot block cluster with write prohibit function supported protection function Int...

Page 986: ...eral I O area 4 KB Block 14 4 KB Block 15 4 KB Block 16 4 KB Block 13 4 KB 0000 D000H 0000 CFFFH 0000 E000H 0000 DFFFH 0000 F000H 0000 EFFFH 0001 0000H 0000 FFFFH 0001 1000H 0001 0FFFH Block 122 4 KB Block 121 4 KB Block 123 4 KB Block 124 4 KB Block 125 4 KB Block 127 4 KB Block 126 4 KB 0007 F000H 0007 EFFFH 0007 E000H 0007 DFFFH 0007 D000H 0007 CFFFH 0007 C000H 0007 BFFFH 0007 B000H 0007 AFFFH ...

Page 987: ...00 DFFFH 0000 F000H 0000 EFFFH 0001 0000H 0000 FFFFH 0001 1000H 0001 0FFFH Block 90 4 KB Block 89 4 KB Block 91 4 KB Block 92 4 KB Block 93 4 KB Block 95 4 KB Block 94 4 KB 0005 F000H 0005 EFFFH 0005 E000H 0005 DFFFH 0005 D000H 0005 CFFFH 0005 C000H 0005 BFFFH 0005 B000H 0005 AFFFH 0005 A000H 0005 9FFFH 0005 9000H 0005 8FFFH 0005 FFFFH Block 0 4 KB Block 1 4 KB Block 2 4 KB Block 3 4 KB 0000 2000H...

Page 988: ...h memory can be rewritten under various conditions such as while communicating with an external device Table 24 1 Rewrite Method Rewrite Method Functional Outline Operation Mode Off board programming Flash memory can be rewritten before the device is mounted on the target system by using a dedicated flash programmer and a dedicated program adapter board Flash memory programming mode On board progr...

Page 989: ...ory blocks are erased yes yes Chip erasure The contents of the entire memory area are erased all at once yes no Write Writing to specified addresses and a verify check to see if write level is secured are performed yes yes Verify check sum Data read from the flash memory is compared with data transferred from the flash programmer yes no Can be read by user program Blank check The erasure status of...

Page 990: ...Can always be read or rewritten regardless of protection function setting Chip erase command prohibit Execution of block erase and chip erase commands on all the blocks is prohibited Once prohibition is set setting of prohibition cannot be initialized because the chip erase command cannot be executed Block erase command Chip erase command Program command Program command prohibit Write and block er...

Page 991: ...ollowing shows the environment required for writing programs to the flash memory of the V850E PH2 Figure 24 3 Environment Required for Writing Programs to Flash Memory A host machine is required for controlling the dedicated flash programmer UARTC0 or CSIB0 is used for the interface between the dedicated flash programmer and the V850E PH2 to perform writing erasing etc A dedicated program adapter ...

Page 992: ...er UARTC0 2 CSIB0 Serial clock 2 4 kHz to 2 5 MHz MSB first Figure 24 5 Communication with Dedicated Flash Programmer CSIB0 Dedicated flash programmer PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XXX YYY XXXXX XXXXXX XXXX XXXX YYYY STATUS VDD1 VDD3 VSS1 VSS3 RESET TXDC0 RXDC0 FLMD1 FLMD1 VDD2 VDD GND RESET RxD TxD FLMD0 FLMD0 V850E PH2 Dedicated flash programmer PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XX...

Page 993: ...clock and the V850E PH2 operates as a slave When the PG FP4 is used as the dedicated flash programmer it generates the following signals to the V850E PH2 For details refer to the PG FP4 User s Manual U15260E Dedicated flash programmer PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XXX YYY XXXXX XXXXXX XXXX XXXX YYYY STATUS VDD1 VDD3 V V SS1 SS3 RESET SOB0 SIB0 SCKB0 PCM0 FLMD1 FLMD1 VDD2 VDD GND RESET SI ...

Page 994: ...connected Do not need to be connected Table 24 4 Signal Connections of Dedicated Flash Programmer PG FP4 PG FP4 V850E PH2 Processing for Connection Signal Name I O Pin Function Pin Name UARTC0 CSIB0 CSIB0 HS FLMD0 Output Write enable disable FLMD0 FLMD1 Output Write enable disable FLMD1 Note 1 Note 1 Note 1 VDD VDD voltage generation Voltage monitor VDD3x Note 2 Note 2 Note 2 VDD2 VDD2 voltage gen...

Page 995: ...h memory control The following shows the procedure for manipulating the flash memory Figure 24 7 Procedure for Manipulating Flash Memory Start Select communication system Manipulate flash memory End Yes Supplies FLMD0 pulse No End Switch to flash memory programming mode ...

Page 996: ...ollows depending on the communication mode Caution When UARTC0 is selected the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse Number of FLMD0 Pulses Communication Mode Remarks 0 UARTC0 Communication rate 9 600 bps after reset LSB first 8 CSIB0 V850E PH2 performs slave operation MSB first 11 CSIB0 HS Others RFU Setting...

Page 997: ...I0 HS Blank check Block blank check command Checks if the contents of the memory in the specified block have been correctly erased Erase Chip erase command Erases the contents of the entire memory Block erase command Erases the contents of the memory of the specified block Write Write command Writes the specified address range and executes a contents verify check Verify Verify command Compares the...

Page 998: ...ndling is required when the external device does not acknowledge the status immediately after a reset 1 FLMD0 pin In the normal operation mode input a voltage of VSS3 level to the FLMD0 pin In the flash memory programming mode supply a write voltage of VDD3 level to the FLMD0 pin Because the FLMD0 pin serves as a write protection pin in the self programming mode a voltage of VDD3 level must be sup...

Page 999: ...he connection of the FLMD1 pin Figure 24 11 FLMD1 Pin Connection Example Caution If the VDD3 signal is input to the FLMD1 pin from another device during on board writing and immediately after reset isolate this signal Table 24 6 Relationship Between FLMD0 and FLMD1 Pins and Operation Mode when Reset is Released FLMD0 FLMD1 Operation Mode 0 Don t care Normal operation mode VDD3 0 Flash memory progr...

Page 1000: ...r device output a conflict of signals occurs To avoid the conflict of signals isolate the connection to the other device or set the other device to the output high impedance status Figure 24 12 Conflict of Signals Serial Interface Input Pin Table 24 7 Pins Used by Serial Interfaces Serial Interface Used Pins UARTC0 TXDC0 RXDC0 CSIB0 SOB0 SIB0 SCKB0 CSIB0 HS SOB0 SIB0 SCKB0 PCM0 Input pin Conflict ...

Page 1001: ... the connection to the other device Figure 24 13 Malfunction of Other Device Pin Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode if the signal the V850E PH2 outputs affects the other device isolate the signal on the other device side Pin Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode if the...

Page 1002: ...mory programming are in the same status as that immediately after reset If the external device connected to each port does not recognize the status of the port immediately after reset pins require appropriate processing such as connecting to VDD3 via a resistor or connecting to VSS3 via a resistor 6 Other signal pins Connect X1 and X2 in the same status as that in the normal operation mode During ...

Page 1003: ... the flash memory with a user application program the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory Consequently the user program can be upgraded and constant data can be rewritten in the field Figure 24 15 Concept of Self Programming For further details refer to the self programming application note U16929E Application program Se...

Page 1004: ...nd boot block cluster physical addresses 10000H to 1FFFFH is prohibited the boot block swap has to be done twice With this second swap the logical address will be relocated to the physical address For further information refer to the application note Self Programming Library for embedded Single Voltage FLASH U16929EE Caution Program flow into and out of the 2nd boot block cluster physical addresse...

Page 1005: ...d With the V850E PH2 a user handler can be registered to an entry RAM area by using a library function so that interrupt servicing can be performed by internal RAM or external memory execution Rewriting blocks 16 to 31 1 Boot swap st Block 32 Block m Block 31 Block 0 Block 15 Block 16 Block 32 Block m Block 31 Block 0 Block 15 Block 16 Block 32 Block m Block 31 Block 0 Block 15 Block 16 Rewriting ...

Page 1006: ...1006 Chapter 24 Flash Memory User s Manual U16580EE3V1UD00 MEMO ...

Page 1007: ...ximum ratings are not exceeded The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance Parameter Symbol Conditions Ratings Unit Supply voltage VDD1 Note 2 0 5 to 2 0 V VDD3 Note 4 0 5 to 4 6 V CVDD 0 5 to 2 0 V AVDD VDD3 0 5 V AVDD VDD3 0 5 V 0 5 to 4 6 V VSS1 Note 1 0 5 to 0 5 V VSS3 Note 3 0 5 to 0 5 V C...

Page 1008: ...40 C to 85 C μPD70F3187 A1 TA 40 C to 110 C μPD70F3187 A2 TA 40 C to 125 C 25 2 1 Capacitance Table 25 2 Capacitance 25 2 2 Operating conditions Table 25 3 Operating Conditions TA 25 C VDD1x CVDD VDD3x AVDD VSS1x CVSS VSS3x AVSSx 0 V Parameter Symbol Conditions MIN TYP MAX Unit Input capacitance CI fC 1 MHz Un measured pins returned to 0 V 15 pF Output capacitance CO 15 pF I O capacitance CIO 15 p...

Page 1009: ...verse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as CVSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fet...

Page 1010: ...bol Conditions MIN TYP MAX Unit Input voltage high VIH1 PAL0 to PAL15 PAH0 to PAH5 PDL0 to PDL15 PDH0 to PDH15 PCS0 PCS1 PCS3 PCS4 PCD2 to PCD5 PCT4 PCT5 PCM0 PCM1 PCM6 PCM7 DCK DMS DDI DDO 0 7 VDD3 VDD3 0 3 V VIH3 P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P45 P50 to P57 P60 to P67 P70 to P75 P80 to P86 P90 to P96 P100 to P102 RESET MODE0 to MODE2 DRST Input voltage low VIL1 PAL0 to PAL15...

Page 1011: ...ter VDD3x AVDD 3 0 V to 3 6 V VDD1x CVDD 1 35 V to 1 65 V VSS1x CVSS VSS3x AVSSx 0 V μPD70F3187 TA 40 C to 85 C μPD70F3187 A1 TA 40 C to 110 C μPD70F3187 A2 TA 40 C to 125 C Output pin load capacitance CL 35 pF Figure 25 2 AC Test Input Output Waveform Figure 25 3 AC Test Load Condition Test Points 0 8 VDD5x 0 2 VDD5x VDD5x 0 V Test Points 0 8 VDD3x 0 2 VDD3x VDD3x 0 V DUT Load on test CL 50 pF ...

Page 1012: ...Number of waits due to external wait signal WAIT 6 n 0 1 3 4 Parameter Symbol MIN MAX Unit Data input set up time vs address 10 tSAID 2 wAS wD w T 30 ns Data input set up time vs RD 11 tSRDID 1 5 wD w T 30 ns RD Low level width 12 tWRDL 1 5 wD w T 15 ns RD High level width 13 tWRDH 0 5 wAS i T 15 ns Address CSn RD delay time 14 tDARD 0 5 wAS T 20 ns RD address delay time 15 tDRDA iT 2 ns Data inpu...

Page 1013: ...rical Specifications User s Manual U16580EE3V1UD00 Figure 25 4 External Asynchronous Memory Access Read Timing CSn A0 to A21 RD 16 13 12 15 17 10 11 output output in out output 14 WAIT input 31 32 BEN0 to BEN3 WR D0 to D31 ...

Page 1014: ...WC2 register wD 1 5 w Number of waits due to external wait signal WAIT 6 n 0 1 3 4 Parameter Symbol MIN MAX Unit Address CSn WR delay time 20 TDAWR 1 wAS T 20 ns Address set up vs WR 21 TSAWR 1 5 wAS wD w T 10 ns WR address delay time 22 TDWRA 0 5 i T 5 ns WR High level width 23 TWWRH 1 5 i wAS T 15 ns WR Low level width 24 TWWRL 0 5 w wD T 12 ns Data output set up time vs WR 25 TSODWR 0 5 wAS wD ...

Page 1015: ...ser s Manual U16580EE3V1UD00 Figure 25 5 External Asynchronous Memory Access Write Timing 23 21 22 20 24 25 26 in output read write output output output in output write write RD CSn WAIT input 31 32 A0 to A21 BEN0 to BEN3 WR D0 to D31 D0 to D31 ...

Page 1016: ...ive is applied to the RESET pin at any time if the voltage power of VDD1x is below its operating condition range Parameter Symbol MIN MAX Unit RESET high level width tWRSH 500 ns RESET low level width tWRSL 500 ns VDD3x VDD1x power up delay tDVR 0 ns VDD3x VDD1x power down delay tDVF 0 ns RESET hold time tDVRR 1 µs RESET setup time tDVRF 0 ns tWRSH tWRSL RESET DD3 RESET tDVF tDVRF tDVRR V DD1 V DD...

Page 1017: ...level width tWNIH NRC0 bit 0 96 T 10 ns NRC0 bit 1 384 T 10 ns NMI low level width tWNIL NRC0 bit 0 96 T 10 ns NRC0 bit 1 384 T 10 ns INTPx high level width tWITH NRC1 bit 0 96 T 10 ns NRC1 bit 1 384 T 10 ns INTPx low level width tWITL NRC1 bit 0 96 T 10 ns NRC1 bit 1 384 T 10 ns INTP0 INTP1 high level width tWTIH 500 ns INTP0 INTP1 low level width tWTIL 500 ns tWNIH tWNIL NMI tWITH tWITL INTPx IN...

Page 1018: ...5 C μPD70F3187 A1 TA 40 C to 110 C μPD70F3187 A2 TA 40 C to 125 C 25 5 1 Timer characteristics Table 25 10 Timer P Characteristics Figure 25 8 Timer P Characteristics Remark m 0 to 7 n 0 to 1 x 3 to 6 depending on the pin group the TIPmn belongs to refer to 20 4 Noise Elimina tion on page 965 Parameter Symbol Condition MIN MAX Unit TIPmn input high level width tWTIPH NRCx bit 0 96 T 10 ns NRCx bit...

Page 1019: ...ics Remark m 0 1 n 0 to 3 x 0 to 7 y 0 to 7 x y Parameter Symbol Condition MIN MAX Unit TIR1n input high level width tWTIRH NRC7 bit 0 96 T 10 ns NRC7 bit 1 384 T 10 ns TIR1n input low level width tWTIRL NRC7 bit 0 96 T 10 ns NRC7 bit 1 384 T 10 ns TORmx to TORmy output delay tDTORTOR 15 ns tWTIRH tWTIRL TIRmn TORmx TORmy tDTORTOR tDTORTOR ...

Page 1020: ... Characteristics Figure 25 10 Timer T Characteristics Remark m 0 1 n 0 1 Parameter Symbol Condition MIN MAX Unit TITmn input high level width tWTITH NRC2 bit 0 96 T 10 ns NRC2 bit 1 384 T 10 ns TITmn input low level width tWTITL NRC2 bit 0 96 T 10 ns NRC2 bit 1 384 T 10 ns tWTIPH tWTIPL TIPmn ...

Page 1021: ...n output low level width tWSKLM 0 5 tCYSKM 10 ns SIBn input setup time vs SCKBn tSSISKM 20 ns SIBn input hold time vs SCKBn tHSKSIM 10 ns SOBn output delay vs SCKBn tDSKSOM 10 ns SOBn output hold time vs SCKBn tHSKSOM 0 5 tCYSKM 10 ns CBnSCK2 to CBnSCK0 111B Parameter Symbol MIN MAX Unit SCKBn input clock cycle time tCYSKS 125 ns SCKBn input high level width tWSKHS 0 5 tCYSKS 10 ns SCKBn input low...

Page 1022: ...D00 Figure 25 11 CSIB Timing in Master Mode CKP DAP bits 00B or 11B Figure 25 12 CSIB Timing in Master Mode CKP DAP bits 01B or 10B tCYSKM tWSKLM tDSKSOM tHSKSOM tSSISKM tHSKSIM tWSKHM SCKBn SOBn SIBn tCYSKM tWSKHM tDSKSOM tHSKSOM tSSISKM tHSKSIM tWSKLM SCKBn SOBn SIBn ...

Page 1023: ...UD00 Figure 25 13 CSIB Timing in Slave Mode CKP DAP bits 00B or 11B Figure 25 14 CSIB Timing in Slave Mode CKP DAP bits 01B or 10B tCYSKS tWSKLS tDSKSOS tHSKSOS tSSISKS tHSKSIS tWSKHS SCKBn SOBn SIBn tCYSKS tWSKHS tDSKSOS tHSKSOS tSSISKS tHSKSIS tWSKLS SCKBn SOBn SIBn ...

Page 1024: ...s SO3n output delay vs SCK3n tDSKSOM 10 ns SO3n output hold time vs SCK3n tHSKSOM 0 5 tCYSKM 10 ns SCS3nm inactive width tWSKCSB 0 5 tCYSKM 10 ns SCS3nm setup time vs SCK3n tSCSZCK0 tCYK 10 ns tSCSZCK1 tCYSKM tCYK 10 ns tSCSZCK2 tCYSKM tCYK 10 ns SCS3nm hold time vs SCK3n tHSKCSZ0 tCYK 10 ns tHSKCSZ1 0 5 tCYSKM 10 ns CKS3n2 to CKS3n0 111B Parameter Symbol MIN MAX Unit CSI3 operation clock cycle ti...

Page 1025: ...25 15 CSI3 Timing in Master Mode CKP DAP bits 00B or 11B Figure 25 16 CSI3 Timing in Master Mode CKP DAP bits 01B or 10B tCYK tCYSKM tWSKLM tDSKSOM tHSKSOM tSSISKM tHSKSIM tWSKHM Clock SCK3n SO3n SI3n tCYK tCYSKM tWSKHM tDSKSOM tHSKSOM tSSISKM tHSKSIM tWSKLM Clock SCK3n SO3n SI3n ...

Page 1026: ... 25 17 CSI3 Timing in Slave Mode CKP DAP bits 00B or 11B Figure 25 18 CSI3 Timing in Slave Mode CKP DAP bits 01B or 10B tCYK tCYSKS tWSKLS tDSKSOS tHSKSOS tSSISKS tHSKSIS tWSKHS Clock SCK3n SO3n SI3n tCYK tCYSKS tWSKHS tDSKSOS tHSKSOS tSSISKS tHSKSIS tWSKLS Clock SCK3n SO3n SI3n ...

Page 1027: ... Master Mode only CSIT 0 CSWE 0 CSMD 0 Figure 25 20 CSI3 Chip Select Timing Master Mode only CSIT 0 CSWE 1 CSMD 0 tHSKCSZ0 tSCSZCK0 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n tHSKCSZ0 tSCSZCK1 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n ...

Page 1028: ...ter Mode only CSIT 0 CSWE 1 CSMD 1 Figure 25 22 CSI3 Chip Select Timing Master Mode only CSIT 1 CSWE 0 CSMD 0 tHSKCSZ0 tWSKCSB tSCSZCK0 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n tHSKCSZ1 tSCSZCK0 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n ...

Page 1029: ...ter Mode only CSIT 1 CSWE 1 CSMD 0 Figure 25 24 CSI3 Chip Select Timing Master Mode only CSIT 1 CSWE 1 CSMD 1 tHSKCSZ1 tSCSZCK1 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n tHSKCSZ1 tWSKCSB tSCSZCK2 SCK3n SCS3n0 to SCS3n3 Continous transmission start SO3n output timing INTCSI3n ...

Page 1030: ...to 9 Parameter Symbol MIN TYP MAX Unit Resolution 10 Bit Overall error 4 LSB Conversion time TCONV 2 8 µs Sampling time TSAM 0 375 1 5 µs Analog input voltage VIAN AVSS AVDD V Analog supply current IAVDD 2 4 mA Reference voltage AVREF AVDD AVDD V Table 25 18 Analog Input Characteristics Parameter Symbol MIN TYP MAX Unit Equivalent circuit parameters R1 600 Ω R2 160 Ω C1 15 pF C2 3 5 pF C3 5 8 pF A...

Page 1031: ...3 0 V to 3 6 V VDD1x CVDD 1 35 V to 1 65 V VSS1x CVSS VSS3x AVSSx 0 V Table 25 19 Flash Memory Basic Characteristics Parameter Condition Symbol MIN TYP MAX Unit Number of rewrites CWRT 100 times block Ambient programming temperature TAPRG 40 100 C Data retention time 6000 h key on time 15 years Table 25 20 Flash Memory Programming Characteristics Parameter Symbol MIN TYP MAX Unit Write time 30 300...

Page 1032: ...eter Symbol MIN TYP MAX Unit VDD setup time to FLMD0 tDRPSR 0 ns VDD setup time to RESET tDRRR 2 ms FLMD0 setup time to RESET tPSRRF 2 ms FLMD0 count start time from RESET tRFCF 10 ms FLMD0 count time tCOUNT 10 ms FLMD0 counter high level width low level width tCH tCL 10 µs FLMD0 RESET input VDD3 0 V VDD3 0 V 0 V VDD1 VDD1x tCL tCOUNT tCH tRFCF tPSRRF tDRPSR tDRRR 0 V VDD3 VDD3x ...

Page 1033: ...0 0 2 H 0 22 I 0 10 S 3 8 MAX K 1 3 0 2 L 0 5 0 2 M 0 17 N 0 10 P 3 2 0 1 0 05 0 04 J 0 5 T P P208GD 50 LML MML SML WML 7 0 03 0 07 R 5 5 J I N S S detail of lead end Q 0 4 0 1 M NOTE Each lead centerline is located within 0 10 mm of its true position T P at maximum material condition 1 208 52 53 156 157 105 104 C A B Q R H K M L D P G F S A 30 6 0 2 D 30 6 0 2 ...

Page 1034: ...1 A2 S y e S x b A B M ZE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ZD B A S w B S w A INDEX MARK D E YWVUT RPNML K J HGF EDCB A ITEM DIMENSIONS D E w e A A1 A2 b x y y1 ZD ZE 21 00 0 10 21 00 0 10 1 33 0 30 1 83 0 17 1 00 0 50 0 10 UNIT mm 0 60 0 10 0 15 0 15 0 35 1 00 1 00 P256F1 100 JN4 256 PIN PLASTIC BGA 21x21 ...

Page 1035: ...rs The number of days refers to storage at 25 C 65 RH MAX after the dry pack has been opened Caution Do not use two or more soldering methods in combination except partial heating method Table 27 1 Soldering Conditions Soldering Method Soldering Condition Symbol of Recommended Soldering Condition Infrared reflow Package peak temperature tbd C Time tbd seconds max tbd C min Number of times tbd max ...

Page 1036: ...1036 Chapter 27 Recommended Soldering Conditions User s Manual U16580EE3V1UD00 MEMO ...

Page 1037: ...Rn0 to ADCRn9 581 ADCRn0H to ADCRn9H 581 ADDMAn 584 Address wait control register 175 ADMn0 576 ADMn1 577 ADMn2 579 ADTRSELn 580 Anytime rewrite TMP 274 TMR 345 347 Anytime write TMT 483 AWC 175 B Batch rewrite TMP 277 TMR 345 352 TMT 485 Baud rate generator 47 Baud rate generator 3n 693 BCC 177 BCT0 150 BCT1 150 BEC 154 BPC 122 BRG3n 693 BSC 152 Bus clock dividing control register 178 Bus control...

Page 1038: ...n module bit rate register CnBTR 792 CANn module control register CnCTRL 781 CANn module error counter register CnERC 787 CANn module information register CnINFO 786 CANn module interrupt enable register CnIE 788 CANn module interrupt status register CnINTS 790 CANn module last error information register CnLEC 785 CANn module last in pointer register CnLIPT 793 CANn module last out pointer registe...

Page 1039: ... 98 CPU register set 86 CSC0 147 CSC1 147 CSIB transmit data register 648 CSIBn control register 0 649 CSIBn control register 1 651 CSIBn control register 2 652 CSIBn receive data register 647 CSIBn status register 654 CSIBUF status register 3n 688 CSIC3n 682 CSIL3n 691 CSIM3n 680 CTBP 93 CTPC 92 CTPSW 92 D Data space 100 Data wait control registers 0 1 174 DBPC 93 DBPSW 93 Debug control unit 47 D...

Page 1040: ...7 199 DVC 178 DWC0 174 DWC1 174 E ECR 90 ECT 94 Edge detection 228 EFG 95 EIPC 89 EIPSW 89 Endian configuration register 154 EP 251 Exception cause register 90 Exception status flag 251 Exception trap 252 Exception debug trap status saving registers 93 External bus interface 145 F FEPC 90 FEPSW 90 Flash memory programming mode 96 Floating point arithmetic control register 94 Floating point arithme...

Page 1041: ...able interrupts 229 Priorities 232 Restore 231 Memory controller 46 Memory map 101 N NMI edge detection specification 228 NMI status saving registers 90 Noise removal time control register 82 Non maskable interrupt 224 Restore 227 Non maskable interrupt status flag 228 Non port pins 54 Normal operating mode 96 NP 228 NRC 82 O On chip peripheral I O area 106 Operating modes 96 P PC 87 Peripheral ar...

Page 1042: ...e pulse unit 47 Receive data buffer register 3n 685 Reload TMP 277 TMT 485 Reload mode TMR 345 ROM 46 ROM less mode 96 S SAR2 195 SAR3 195 Serial interface 47 SESA10 549 SFA3n 688 SFCS3n 686 SFCS3nL 686 SFDB3n 687 SFDB3nH 687 SFDB3nL 687 SFN3n 692 SFR area 106 Signal edge selection register 10 549 Single chip modes 0 1 96 SIRB3n 685 SIRB3nH 685 SIRB3nL 685 Software exception 249 Specific registers...

Page 1043: ... register 5 321 TMRn control register 0 324 TMRn control register 1 326 TMRn counter read register 322 TMRn dead time setting register 0 323 TMRn dead time setting register 1 323 TMRn I O control register 0 328 TMRn I O control register 3 331 TMRn I O control register 4 332 TMRn option register 0 333 TMRn option register 1 335 TMRn option register 2 337 TMRn option register 3 339 TMRn option regis...

Page 1044: ...20 TRnCCR5 321 TRnCNT 322 TRnCTL0 324 TRnCTL1 326 TRnDTC0 323 TRnDTC1 323 TRnIOC0 328 TRnIOC3 331 TRnIOC4 332 TRnOPT0 333 TRnOPT1 335 TRnOPT2 337 TRnOPT3 339 TRnOPT6 341 TRnOPT7 342 TRnSBC 322 TTnCCR0 461 TTnCCR1 462 TTnCNT 464 TTnCTL0 465 TTnCTL1 467 TTnCTL2 469 TTnIOC0 471 TTnIOC1 472 TTnIOC2 473 TTnIOC3 474 TTnOPT0 476 TTnOPT1 477 TTnOPT2 479 TTnTCW 464 TUM10 545 U UARTCn Receive error interrup...

Page 1045: ...ive data register 623 UARTCn status register 620 UARTCn status register 1 622 UARTCn transmit data register 624 UCnCTL0 612 UCnCTL1 614 UCnCTL2 615 UCnOPT1 618 UCnRX 623 UCnRXL 623 UCnSTR 620 UCnSTR1 622 UCnTX 624 UCnTXL 624 V VSWC 142 143 W Word access 32 bits 164 ...

Page 1046: ...1046 Appendix A Index User s Manual U16580EE3V1UD00 MEMO ...

Page 1047: ... changed Caution 2 added 3 4 8 1 p 127 3 4 10 DMA wait control register 0 DMAWC0 set value changed 3 4 10 p 130 Figure 4 11 Bus Clock Dividing Control Register DVC address value changed 4 7 2 p 166 Table 3 5 Peripheral I O Registers changed 3 4 6 p 101 104 107 Chapter 5 2 Burst Mode Flash removed 5 2 p 180 6 1 Features of the DMA added 6 1 p 181 Figure 6 1 DMA Transfer Memory Start Address Registe...

Page 1048: ... 9 27 Basic Operation Timing in PWM Mode remark 2 changed 9 5 6 p 283 284 10 3 7 TMRn I O control register 4 TRnIOC4 description changed 10 3 7 p 318 Figure 10 19 TMRn Option Register 0 TRnOPT0 changed 10 3 8 p 320 10 3 11 TMRn option register 3 TRnOPT3 Caution changed 10 3 11 p 325 Figure 10 35 A D Conversion Trigger Output Controller changed 10 8 p 362 Figure 10 56 High Accuracy T PWM Mode Block...

Page 1049: ... 1 1 buffer mode operation timer trigger select 1 buffer timer event signals s names changed 14 6 1 1 p 580 Table 14 6 Correspondence Between Analog Input Pins and ADCRnm Register 1 Buffer Mode Timer Trigger Select 1 Buffer changed 14 6 1 p 581 Figure 14 15 Example of 1 Buffer Mode Operation Timer Trigger Select 1 Buffer ANIn1 changed 14 6 1 p 581 14 6 1 2 4 buffer mode operation timer trigger sel...

Page 1050: ...l Asynchronous Memory Access Read Timing values changed Remark 6 added 25 4 1 p 1002 Figure 25 4 External Asynchronous Memory Access Read Timing changed 25 4 1 p 1003 Table 25 7 External Asynchronous Memory Access Write Timing parameters and values changed Remark 6 added 25 4 2 p 1004 Figure 25 5 External Asynchronous Memory Access Write Timing changed 25 4 2 p 1005 Table 25 8 Reset Timing RESET h...

Page 1051: ...3 p 683 Figure 17 5 Chip Select CSI Buffer Register 3n SFCS3n SFCS3nL Note added 17 3 4 p 684 Figure 17 6 Transmit Data CSI Buffer Register 3n SFDB3n SFDB3nL SFDB3nH Note added 17 3 5 p 685 Figure 17 7 CSIBUF Status Register 3n SFA3n 1 3 Note added 17 3 6 p 686 Figure 17 8 Transfer Data Length Select Register 3n CSIL3n Note added 17 3 7 p 689 Figure 17 9 Transfer Data Number Specification Register...

Page 1052: ...1052 User s Manual U16580EE3V1UD00 ...

Page 1053: ......

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