NEC MuPD70F3187, User Manual

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Chapter 10 16-bit Inverter Timer/Counter R
User’s Manual U16580EE3V1UD00
10.10.5 PWM mode
(1) Outline of PWM mode
When, in the PWM mode, the duty is set to the TRnCCR1 to TRnCCR5 registers, the cycle is set
to the TRnCCR0 register, and TRnCE = 1 is set, variable duty PWM output is performed from pins
TORn1 to TORn5.
Simultaneously with the start of count up operation, pins TORn1 to TORn5 becomes high level,
and upon a match between the counter and the TRnCCR1 to TRnCCR5 registers, becomes low
level. Next, the TORn1 to TORn5 pins become high level upon a match with the TRnCCR0
register. The TORn0 pin performs toggle output upon a match with the TRnCCR0 buffer register.
During count operation, a compare match interrupt (INTTRnCC0) is output upon a match between
the counter and TRnCCR0 register, and compare match interrupts (INTTRnCC1 to INTTRnCC5)
are output upon a match between the counter and TRnCCR1 to TRnCCR5 registers.
The TRnCCR0 to TRnCCR5 registers can be rewritten during count operation. Compare register
reload occurs upon a match between the counter value and the TRnCCR0 buffer register.
However, since the next reload timing becomes valid when the TRnCCR1 register is written to,
write the same value to the TRnCCR1 register even when wishing to rewrite only the value of the
TRnCCR0 register. Reloading is not performed if only the TRnCCR0 register is rewritten.
In the PWM mode, the TRnCCR0 to TRnCCR3 registers have their function fixed as compare
registers, so the capture function cannot be used.