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Bank 3 Prototyping Area
Figure 14. Bank 3 Prototyping Area
Table 19. CPLD Connectivity to Bank 3 Prototyping Area
Bank 3 Lattice
Lattice
Location
Schematic
Name
7
CPLD
Bank
CPLD
Pin
HDL Name
Physical Channel
Name
A18
Bank3_IO(104)
3
C14
cBank3ioA(0) Bank3_PortA_DIO0
A17
Bank3_IO(105)
3
C15
cBank3ioA(1) Bank3_PortA_DIO1
A16
Bank3_IO(106)
3
D13
cBank3ioA(2) Bank3_PortA_DIO2
A15
Bank3_IO(107)
3
D14
cBank3ioA(3) Bank3_PortA_DIO3
A14
Bank3_IO(108)
3
D15
cBank3ioA(4) Bank3_PortA_DIO4
A13
Bank3_IO(109)
3
D16
cBank3ioA(5) Bank3_PortA_DIO5
A12
Bank3_IO(110)
3
E12
cBank3ioA(6) Bank3_PortA_DIO6
A11
Bank3_IO(111)
3
E13
cBank3ioA(7) Bank3_PortA_DIO7
A10
Bank3_IO(112)
3
E14
cBank3ioB(0) Bank3_PortB_DIO0
A9
Bank3_IO(113)
3
E15
cBank3ioB(1) Bank3_PortB_DIO1
7
In the silkscreen, these signals are marked as CPLD(Pin Number) for space reasons.
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SLSC-12101 User Guide