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SLSC Interrupt
This entity implements an interrupt block that complies with Section 8.1 of the
Switch Load
and Signal Conditioning Design Specifications
. It is configurable through generic constants. It
can handle edge-sensitive and level-sensitive signals. The configuration on the sensitivity is
controlled through kSensitivity. The incoming interrupts should be synchronous to Clk.
Table 6. Register Descriptions for the Interrupt Block
Register
Name
Address
Type
Explanation
Status
kRegisterBase
R
A 1 indicates that an interrupt has occurred. The
interrupt is propagated to IntIn# only if the
corresponding bit has been enabled.
Mask
kRegist 1 R
A 1 indicates that the corresponding interrupt is
enabled.
Enable
kRegist 2 Strobe Writing a 1 enables the corresponding interrupt
and turns the corresponding bit in the Mask
Register into 1. Writing a 0 has no effect.
Disable
kRegist 3 Strobe Writing a 1 disables the corresponding interrupt
and turns the corresponding bit in the Mask
Register into a 0. Writing a 0 has no effect.
Ack
kRegist 4 Strobe Writing a 1 to the corresponding bit removes the
interrupt condition. This bit is self-clearing.
Writing a 0 has no effect.
Table 7. Signal Descriptions of the Interrupt Component
Signal Name
Direction
Explanation
Generics
kRegisterBase
N/A
Defines the base address of the block. This address will
also correspond to the Status register. The next four
consecutive addresses are assigned to Mask,
InterruptEnable, InterruptDisable, and Ack.
kNumberOfInterrupts N/A
Determines the number of interrupts implemented.
Acceptable values range from 1 to 64.
kSensitivity
N/A
Determines the sensitivity of the corresponding line of
cInterruptsIn. A 0 defines a level sensitive interrupts,
while a 1 defines an edge sensitive.
Signals
aReset
In
Board reset signal.
SLSC-12101 User Guide
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