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Table 7. Signal Descriptions of the Interrupt Component (Continued)
Signal Name
Direction
Explanation
Clk
In
Stable clock provided by the CPLD.
cRdyRst
In
Ready/Rst signal. The Block follows the reset
requirements defined in Chapter 6 of the
Switch Load and
Signal Conditioning Design Specifications
. Additionally,
this implementation disables and clears all interrupts
when the module goes to Reset.
cRegPortOut
Out
Signals to the EdBlock Register Port.
cRegPortIn
In
Signals from the EdBlock Register Port.
cInterrupt_n
Out
Interrupt signal of the SLSC interface.
cInterruptsIn
In
Drive 1 to these signals to generate an interrupt. The
sensitivity of each of these signals is configured by
kSensitivity.
Instantiation of the Interrupt Block
You can instantiate the interrupt block in your design as follows.
LED Implementation
This entity provides an LED controller for 2-pin bicolor LEDs. In this case, the entity has two
green/red dual LEDs. The block allows control of the LEDs and illuminates them green, red,
and yellow either in a solid or blinking pattern. The yellow color is achieved by alternating
between red and green at approximately 300 Hz.
This component has a single register; the address is defined by the kAddress generic.
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SLSC-12101 User Guide