Table 16. CPLD Connectivity to Bank 2 Prototyping Area (Continued)
Bank 2 Lattice
Lattice
Location
Schematic Name
CPLD
Bank
CPLD
Pin
HDL Name
Physical Channel
Name
AE18
Bank2_IO(91)
2
D5
cBank2ioE(5) Bank2_PortE_DIO5
AE17
Bank2_IO(92)
2
D6
cBank2ioE(6) Bank2_PortE_DIO6
AE16
Bank2_IO(93)
2
D7
cBank2ioE(7) Bank2_PortE_DIO7
AE15
Bank2_IO(94)
2
D8
cBank2ioF(0) Bank2_PortF_DIO0
AE14
Bank2_IO(95)
2
D9
cBank2ioE(1) Bank2_PortF_DIO0
AE13
Bank2_IO(96)
2
E10
cBank2ioE(2) Bank2_PortF_DIO0
AE12
Bank2_IO(97)
2
E11
cBank2ioE(3) Bank2_PortF_DIO0
AE11
Bank2_IO(98)
2
E6
cBank2ioE(4) Bank2_PortF_DIO0
AE10
Bank2_IO(99)
2
E7
cBank2ioE(5) Bank2_PortF_DIO0
AE9
Bank2_IO(100)
2
E8
cBank2ioE(6) Bank2_PortF_DIO0
AE8
Bank2_IO(101)
2
E9
cBank2ioE(7) Bank2_PortF_DIO0
Table 17. Connector 2 Connectivity to Bank 2 Prototyping Area
Connector J2
J2 Pin Schematic Name
5
Lattice
Coordinate
(Bank 2)
J2 Pin Schematic Name
6
Lattice
Coordinate
(Bank 2)
1
Front2_IO(1)
A24
23
Front2_IO(23)
D24
2
Front2_IO(2)
A23
24
Front2_IO(24)
D23
3
Front2_IO(3)
A22
25
Front2_IO(25)
D22
4
Front2_IO(4)
A21
26
Front2_IO(26)
D21
5
Front2_IO(5)
A20
27
Front2_IO(27)
D20
6
Front2_IO(6)
A19
28
Front2_IO(28)
D19
7
Front2_IO(7)
A18
29
GND
GND
8
Front2_IO(8)
A17
30
Front2_IO(30)
D17
5
In the silkscreen, these signals are marked IO2(Pin Number) for space reasons
6
In the silkscreen, these signals are marked IO2(Pin Number) for space reasons
30
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SLSC-12101 User Guide