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Figure 8. Bank 3 and Bank 4 Voltage Setting Header
Logic Analyzer Connector
A 43-pin MICTOR Connector is placed between the CPLD and SLSC Interface connector for
direct monitoring of the signals using a logic analyzer. In addition to the SLSC signals, 17
debug lines are connected directly from the CPLD to the connector. In the shipping CPLD
image, two of these lines are controlled by DIO ports, one line is a copy of the internal 40
MHz clock, and 14 lines are only driven to GND. You can use all 17 lines to monitor internal
signals of your design. See pinout sections for more information on the signal routing to this
connector.
Description of the Module Controller HDL
General Architecture
The SLSC-12101 Module Controller instantiated in the MAX V CPLD is implemented in
VHDL. The top-level file is
Slsc12101Top.vhd
. The design uses an instance of EdBlock
(
EdBlock.vhd
) to handle the communication between the SLSC chassis and the Module
Controller. The design features an SPI Channel selector which can be used for future SPI
channel expansion in the SLSC architecture. This channel expansion can be used in this
module to access temperature sensors in the prototyping area.
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SLSC-12101 User Guide