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Table 16. CPLD Connectivity to Bank 2 Prototyping Area (Continued)
Bank 2 Lattice
Lattice
Location
Schematic Name
CPLD
Bank
CPLD
Pin
HDL Name
Physical Channel
Name
C8
Bank2_IO(62)
2
A9
cBank2ioB(3) Bank2_PortB_DIO3
E8
Bank2_IO(64)
2
B10
cBank2ioB(4) Bank2_PortB_DIO4
E9
Bank2_IO(65)
2
B11
cBank2ioB(5) Bank2_PortB_DIO5
E10
Bank2_IO(66)
2
B12
cBank2ioB(6) Bank2_PortB_DIO6
E11
Bank2_IO(67)
2
B13
cBank2ioB(7) Bank2_PortB_DIO7
E12
Bank2_IO(68)
2
B14
cBank2ioC(0) Bank2_PortC_DIO0
E13
Bank2_IO(69)
2
B16
cBank2ioC(1) Bank2_PortC_DIO1
E14
Bank2_IO(70)
2
B3
cBank2ioC(2) Bank2_PortC_DIO2
E15
Bank2_IO(71)
2
B4
cBank2ioC(3) Bank2_PortC_DIO3
E16
Bank2_IO(72)
2
B5
cBank2ioC(4) Bank2_PortC_DIO4
E17
Bank2_IO(73)
2
B6
cBank2ioC(5) Bank2_PortC_DIO5
E18
Bank2_IO(74)
2
B7
cBank2ioC(6) Bank2_PortC_DIO6
E19
Bank2_IO(75)
2
B8
cBank2ioC(7) Bank2_PortC_DIO7
AC8
Bank2_IO(78)
2
C11
cBank2ioD(0) Bank2_PortD_DIO0
AC9
Bank2_IO(79)
2
C12
cBank2ioD(1) Bank2_PortD_DIO1
AC10
Bank2_IO(80)
2
C13
cBank2ioD(2) Bank2_PortD_DIO2
AC11
Bank2_IO(81)
2
C4
cBank2ioD(3) Bank2_PortD_DIO3
AC12
Bank2_IO(82)
2
C5
cBank2ioD(4) Bank2_PortD_DIO4
AC13
Bank2_IO(83)
2
C6
cBank2ioD(5) Bank2_PortD_DIO5
AC14
Bank2_IO(84)
2
C7
cBank2ioD(6) Bank2_PortD_DIO6
AC15
Bank2_IO(85)
2
C8
cBank2ioD(7) Bank2_PortD_DIO7
AC16
Bank2_IO(86)
2
C9
cBank2ioE(0) Bank2_PortE_DIO0
AC17
Bank2_IO(87)
2
D10
cBank2ioE(1) Bank2_PortE_DIO1
AC18
Bank2_IO(88)
2
D11
cBank2ioE(2) Bank2_PortE_DIO2
AC19
Bank2_IO(89)
2
D12
cBank2ioE(3) Bank2_PortE_DIO3
AE19
Bank2_IO(90)
2
D4
cBank2ioE(4) Bank2_PortE_DIO4
SLSC-12101 User Guide
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