supplies and can provide up to 2 A. In addition to the limitations imposed by the current limits
on the different rails on the module, you should also consider the power dissipation limitations
as defined in the
Switch Load and Signal Conditioning Module Design Specifications
.
Table 3. Bank Rail Available Voltages and Current Limits
Bank
Available Voltages
Maximum Current
1
3.3 V fixed, provided by the SLSC backplane
400 mA
2
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
2 A
3
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
2 A
4
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
2 A
Peripheral Implementations
Along with EdBlock, the Module Development Kit provides a few examples of useful
instances that can be used directly with EdBlock to implement common functionality to
interact with a wide range of devices that can be placed in the prototyping area or with
peripherals already present on the board.
File Name
Notes
Interrupt.vhd
Customizable entity that implements interrupts which follow
the
Switch Load and Signal Conditioning Design Specifications
and are compatible with the EdBlock register map.
IoPort.vhd
Customizable entity that implements digital I/O compatible
with the EdBlock register map.
Leds.vhd
LED controller compatible with the EdBlock register map that
allows the control of bi-color LEDs for the SLSC-12101.
SpiChannelSelect.vhd
Customizable entity that allows switching SPI channels for all
the slaves in the SLSC-12101.
Digital Input and Output
The
IoPort.vhd
file allows the implementation of bi-directional signals on the CPLD. The
entity is configurable via generics to set its address base and its port size. Each instantiated
block will add three registers of the same size that are defined by the generic kPortSize.
Because of this, if the entity is instantiated, you should avoid adding other registers in the
range kAddress to kA 2 where kAddress is the address generic of the entity.
The maximum length of kPortSize is 64.
SLSC-12101 User Guide
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© National Instruments
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