File Name
Notes
EdBlock.vhd
Top-level file of the component which can be instantiated
in a CPLD top-level design. It handles incoming SLSC
frames, handles errors when detected, and executes the
corresponding register access when valid frames are
received.
Spi.vhd
,
Control.vhd
,
CrcGen.vhd
,
ShiftRegister.vhd
Sub-components of the EdBlock.
PkgEdBlock.vhd
Contains the RegisterRead and RegisterWrite functions
and records to easily implement registers in a top-level
design.
PkgSlscProtocol.vhd
Contains constants relevant to the SLSC Specifications
1.0.
Error Detection Block Instantiation
You can instantiate the Error Detection block in your design as follows:
Variable Voltage Power Supplies
The MAX V supports VCCIO of 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V in order to use several
I/O standards. The SLSC-12101 has user-configurable power supplies for three of the four
CPLD banks. The voltages are set by placing a jumper in the corresponding header connecting
the pair labeled with the desired voltage. The jumper should be placed on the board before the
module is inserted in the SLSC chassis.
Once a voltage is set for a bank, all the signals on that bank need to use an I/O standard
supported by that voltage. For more information about the supported I/O standards and rules to
interconnect I/O standards with the MAX V CPLD, refer to Altera's
MAX V Device Handbook
.
The voltages of all the banks are also routed to the prototyping area to allow the circuits built
there to use it. The maximum current that can be withdrawn from each bank depends on the
maximum current the source can provide, as well as the estimated current used by the CPLD.
Bank 1 is powered directly from the SLSC chassis and, by SLSC Specification 1.0, the module
shall not withdraw more than 400 mA. Banks 2-4 take their power from 24 V on-board power
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SLSC-12101 User Guide