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Table 19. CPLD Connectivity to Bank 3 Prototyping Area (Continued)

Bank 3 Lattice

Lattice

Location

Schematic

Name

7

CPLD

Bank

CPLD

Pin

HDL Name

Physical Channel

Name

 

 

 

 

 

 

A8

Bank3_IO(114)

3

E16

cBank3ioB(2) Bank3_PortB_DIO2

C7

Bank3_IO(115)

3

F11

cBank3ioB(3) Bank3_PortB_DIO3

C8

Bank3_IO(116)

3

F12

cBank3ioB(4) Bank3_PortB_DIO4

C9

Bank3_IO(117)

3

F13

cBank3ioB(5) Bank3_PortB_DIO5

C10

Bank3_IO(118)

3

F14

cBank3ioB(6) Bank3_PortB_DIO6

C11

Bank3_IO(119)

3

F15

cBank3ioB(7) Bank3_PortB_DIO7

C12

Bank3_IO(120)

3

F16

cBank3ioC(0) Bank3_PortC_DIO0

C13

Bank3_IO(122)

3

G12

cBank3ioC(1) Bank3_PortC_DIO1

C14

Bank3_IO(123)

3

G13

cBank3ioC(2) Bank3_PortC_DIO2

C15

Bank3_IO(124)

3

G14

cBank3ioC(3) Bank3_PortC_DIO3

C16

Bank3_IO(125)

3

G15

cBank3ioC(4) Bank3_PortC_DIO4

C17

Bank3_IO(126)

3

G16

cBank3ioC(5) Bank3_PortC_DIO5

C18

Bank3_IO(133)

3

J13

cBank3ioC(6) Bank3_PortC_DIO6

AB7

Bank3_IO(134)

3

J14

cBank3ioD(0) Bank3_PortD_DIO0

AB8

Bank3_IO(135)

3

J15

cBank3ioD(1) Bank3_PortD_DIO1

AB9

Bank3_IO(136)

3

J16

cBank3ioD(2) Bank3_PortD_DIO2

AB10

Bank3_IO(138)

3

K12

cBank3ioD(3) Bank3_PortD_DIO3

AB11

Bank3_IO(139)

3

K13

cBank3ioD(4) Bank3_PortD_DIO4

AB12

Bank3_IO(140)

3

K14

cBank3ioD(5) Bank3_PortD_DIO5

AB13

Bank3_IO(141)

3

K15

cBank3ioD(6) Bank3_PortD_DIO6

AB14

Bank3_IO(142)

3

K16

cBank3ioD(7) Bank3_PortD_DIO7

AB15

Bank3_IO(143)

3

L11

cBank3ioE(0) Bank3_PortE_DIO0

AB16

Bank3_IO(144)

3

L12

cBank3ioE(1) Bank3_PortE_DIO1

AB17

Bank3_IO(145)

3

L13

cBank3ioE(2) Bank3_PortE_DIO2

AB18

Bank3_IO(146)

3

L14

cBank3ioE(3) Bank3_PortE_DIO3

7

In the silkscreen, these signals are marked as CPLD(Pin Number) for space reasons.

SLSC-12101 User Guide

  | 

© National Instruments

  | 

33

Summary of Contents for SLSC-12101

Page 1: ...pers quickly prototype designs The module is Level 2 compatible but can be Level 1 compatible if you configure the rear I O signals properly The SLSC 12101 features a MAX V CPLD as a module controller...

Page 2: ...cations It is the user s responsibility to make sure that the product is modified and used in a way that complies with local rules regulations and best practices Note All specifications and certificat...

Page 3: ...nd used the way it is shipped Note The SLSC chassis and SLSC modules do not support hot plug in The entire chassis must be powered down when a module is installed or removed 1 Ensure the CPLD power su...

Page 4: ...odule presence Once the module is detected the Ready LED should be lit green 4 Access the module s properties and physical channels Use a host computer with LabVIEW and the NI SLSC driver installed an...

Page 5: ...rear connectors power supplies and ground Module controller Implemented in a MAX V CPLD handles the communication with the SLSC chassis and controls the peripherals Variable power supplies for CPLD B...

Page 6: ...ity type 2 SLSC Rear I O Compatibility Glyph This indicates RTI compatibility type which is left blank for customization See the Switch Load and Signal Conditioning Module Design Specifications for mo...

Page 7: ...ents and wires or for attaching standard headers to connect to jumpers or secondary PCBs Figure 4 Prototyping Area Hole Array Details 2 54 mm 0 100 in 2 54 mm 0 100 in 1 02 mm 0 040 in plated Prototyp...

Page 8: ...ctrical Features The Input Rails and Fuse The module takes its power from the 24 V and 3 3 V provided by the chassis 3 3 V is only used for the VCCO of Bank 1 and other support circuitry such as the 4...

Page 9: ...imated current used by the CPLD Bank 1 is powered directly from the SLSC chassis and by SLSC Specification 1 0 the module shall not withdraw more than 400 mA Banks 2 4 take their power from 24 V on bo...

Page 10: ...ock Generator The module has pads for you to add an SI5356A clock generator should you need more clocks in your design This clock generator can provide up tp four different frequencies on eight pins E...

Page 11: ...3 V rails provided by the backplane go through bridge resistors that can be removed so that current measurements can be performed Resistor R 16 connects the backplane 24 V rail to the module and W1 p...

Page 12: ...s to monitor internal signals of your design See pinout sections for more information on the signal routing to this connector Description of the Module Controller HDL General Architecture The SLSC 121...

Page 13: ...p vhd Top level file which can be compiled to generate a programming bitfile for the CPLD SlscCpldTop qpf Quartus II project file SlscCpldTop qsf Quartus II settings file SlscCpldTop sdc Constraints f...

Page 14: ...e power supplies for three of the four CPLD banks The voltages are set by placing a jumper in the corresponding header connecting the pair labeled with the desired voltage The jumper should be placed...

Page 15: ...rupt vhd Customizable entity that implements interrupts which follow the Switch Load and Signal Conditioning Design Specifications and are compatible with the EdBlock register map IoPort vhd Customiza...

Page 16: ...Explanation Generics kAddress N A Defines the base address of the block This address will also correspond to the Output register The next two consecutive addresses are assigned to Direction and Input...

Page 17: ...sk Register into 1 Writing a 0 has no effect Disable kRegisterBase 3 Strobe Writing a 1 disables the corresponding interrupt and turns the corresponding bit in the Mask Register into a 0 Writing a 0 h...

Page 18: ...signal of the SLSC interface cInterruptsIn In Drive 1 to these signals to generate an interrupt The sensitivity of each of these signals is configured by kSensitivity Instantiation of the Interrupt Bl...

Page 19: ...ther the LED is lit and in which color b 00 Off b 01 Red b 10 Green b 11 Yellow ReadyMode 2 1 Determines how the LED lights b 0 solid b 1 toggles PowerColor 3 5 2 Determines whether the LED is lit and...

Page 20: ...ects to the Power green anode Instantiating the LEDs Component You can instantiate the LEDs component as follows Creating Registers Read and write registers can easily be implemented using the EdBlock...

Page 21: ...with the RegisterWrite Function Other Auxiliary Files These files contain constants used in the shipping version of the CPLD You can change these values or create your own files to better fit your des...

Page 22: ...tor Pin Schematic Name CPLD Bank CPLD Pin Pin Name 1 CPLD_TCK 1 P3 TCK 2 GND 3 CPLD_TDO 1 M5 TDO 4 3 3 V 5 CPLD_TMS 1 N4 TMS 6 NC 7 NC 8 NC 9 CPLD_TDI 1 L6 TDI 10 GND Pinouts Front I O Connector Pinou...

Page 23: ...0 characteristic impedance traces and have a 33 2 series resistor places near the CPLD All connections between XJ2 and the RTI prototyping area are routed with 50 characteristic impedance without any...

Page 24: ...a box around them The box can be a rectangle around adjacent holes connected to traces An example of this type of hole is C18 of Bank 3 An example of a rectangle enclosing adjacent holes are holes AB7...

Page 25: ...ank1_PortA_DIO0 E13 Bank1_IO 20 1 G4 cBank1ioA 1 Bank1_PortA_DIO1 E14 Bank1_IO 22 1 H1 cBank1ioA 2 Bank1_PortA_DIO2 AC13 Bank1_IO 23 1 H2 cBank1ioA 3 Bank1_PortA_DIO3 AC14 Bank1_IO 24 1 H3 cBank1ioA 4...

Page 26: ...IO 30 D17 9 Front1_IO 9 A16 31 Front1_IO 31 D16 10 Front1_IO 10 A15 32 Front1_IO 32 D15 11 Front1_IO 11 A14 33 Front1_IO 33 D14 12 Front1_IO 12 A13 34 Front1_IO 34 D13 13 Front1_IO 13 A12 35 Front1_IO...

Page 27: ...cellaneous Signals In Bank 1 Prototyping Area Miscellaneous Signals Coordinate Signal Coordinate Signal A1 D1 3 3 V B2 B24 GND A25 D15 3 3 V E25 AC25 GND AD1 3 3 V AD2 AD24 GND AE1 3 3 V C24 GND AD25...

Page 28: ...k2_PortA_DIO1 C17 Bank2_IO 53 2 A12 cBank2ioA 2 Bank2_PortA_DIO2 C16 Bank2_IO 54 2 A13 cBank2ioA 3 Bank2_PortA_DIO3 C15 Bank2_IO 55 2 A15 cBank2ioA 4 Bank2_PortA_DIO4 C14 Bank2_IO 56 2 A2 cBank2ioA 5...

Page 29: ...E17 Bank2_IO 73 2 B6 cBank2ioC 5 Bank2_PortC_DIO5 E18 Bank2_IO 74 2 B7 cBank2ioC 6 Bank2_PortC_DIO6 E19 Bank2_IO 75 2 B8 cBank2ioC 7 Bank2_PortC_DIO7 AC8 Bank2_IO 78 2 C11 cBank2ioD 0 Bank2_PortD_DIO...

Page 30: ...E7 cBank2ioE 5 Bank2_PortF_DIO0 AE9 Bank2_IO 100 2 E8 cBank2ioE 6 Bank2_PortF_DIO0 AE8 Bank2_IO 101 2 E9 cBank2ioE 7 Bank2_PortF_DIO0 Table 17 Connector 2 Connectivity to Bank 2 Prototyping Area Conn...

Page 31: ...17 GND GND 39 Front2_IO 39 D8 18 Front2_IO 18 A7 40 Front2_IO 40 D7 19 Front2_IO 19 A6 41 Front2_IO 41 D6 20 Front2_IO 20 A5 42 Front2_IO 42 D5 21 Front2_IO 21 A4 43 Front2_IO 43 D4 22 Front2_IO 22 A3...

Page 32: ...k3_IO 106 3 D13 cBank3ioA 2 Bank3_PortA_DIO2 A15 Bank3_IO 107 3 D14 cBank3ioA 3 Bank3_PortA_DIO3 A14 Bank3_IO 108 3 D15 cBank3ioA 4 Bank3_PortA_DIO4 A13 Bank3_IO 109 3 D16 cBank3ioA 5 Bank3_PortA_DIO5...

Page 33: ...G15 cBank3ioC 4 Bank3_PortC_DIO4 C17 Bank3_IO 126 3 G16 cBank3ioC 5 Bank3_PortC_DIO5 C18 Bank3_IO 133 3 J13 cBank3ioC 6 Bank3_PortC_DIO6 AB7 Bank3_IO 134 3 J14 cBank3ioD 0 Bank3_PortD_DIO0 AB8 Bank3_I...

Page 34: ...ank3_PortF_DIO2 AD12 Bank3_IO 154 3 N14 cBank3ioF 3 Bank3_PortF_DIO3 AD11 Bank3_IO 155 3 N15 cBank3ioF 4 Bank3_PortF_DIO4 AD10 Bank3_IO 156 3 N16 cBank3ioF 5 Bank3_PortF_DIO5 AD9 Bank3_IO 157 3 P14 cB...

Page 35: ...163 4 M12 cBank4ioA 2 Bank4_PortA_DIO2 A14 Bank4_IO 164 4 M6 cBank4ioA 3 Bank4_PortA_DIO3 A13 Bank4_IO 165 4 M7 cBank4ioA 4 Bank4_PortA_DIO4 A12 Bank4_IO 168 4 N10 cBank4ioA 5 Bank4_PortA_DIO5 A11 Ban...

Page 36: ...Bank4_PortC_DIO2 AB13 Bank4_IO 198 4 R8 cBank4ioC 3 Bank4_PortC_DIO3 AB14 Bank4_IO 199 4 R9 cBank4ioC 4 Bank4_PortC_DIO4 AB15 Bank4_IO 200 4 T10 cBank4ioC 5 Bank4_PortC_DIO5 AB16 Bank4_IO 201 4 T11 cB...

Page 37: ...Coordinate Signal A1 BANK4_VCC AD25 BANK4_VCC B1 BANK4_VCC C1 AB1 GND A25 BANK4_VCC B2 B24 GND B25 BANK4_VCC C25 AB25 GND AC1 BANK4_VCC AC2 AC24 GND AD1 BANK4_VCC A24 GND AC25 BANK4_VCC A23 VCC 5 V R...

Page 38: ...B7 G14 C7 E14 D7 C14 E7 B14 A8 I15 B8 G15 C8 E15 D8 C15 E8 B15 A9 GND B9 GND C9 GND D9 GND E9 GND A10 I16 B10 G16 C10 E16 D10 C16 E10 B16 A11 I17 B11 G17 C11 E17 D11 C17 E11 B17 A15 I18 B15 G18 C15 E1...

Page 39: ...3 6 G C 3 6 H B 3 6 Table 25 RTI Miscellaneous Signals Miscellaneous Signals Coordinate Signal Coordinate Signal B1 I1 GND J3 J6 24 V A2 GND A7 A26 GND B2 C2 3 3 V J7 J26 GND D2 E2 Bank 2 VCC D26 E26...

Page 40: ...l CPLDESET 1 K4 aReset_n Module Reset Table 27 Rotary Switch Connectivity to the CPLD Rotary Switch SW1 pin Schematic Name CPLD Bank CPLD Pin HDL Name Physical Channel Name 1 Switch 0 3 H16 aSwitch 0...

Page 41: ..._CLK 1 C2 aSpi0Clk 2 2 SPI0_MISO 1 C3 aSpi0Miso 3 3 SPI0_MOSI 1 D1 aSpi0Mosi 4 SPI0_CS 0 1 D2 aSpi0Ss 0 4 SPI0_CS 1 1 D3 aSpi0Ss 1 6 6 L0_CT 1 F1 aL0Ct 5 5 L0_INT 1 F2 aL0Int 1 1 SPI1_CLK 1 E1 aSpi1Cl...

Page 42: ...ced with another label such as one with the corporate logo of the module developer On the front panel cover or remove the model name and description SLSC 12101 Prototyping Module Customize LED and con...

Page 43: ...CER 0603 H 039 IN 1 VENKEL C0603X7R500 104KNP C014 C015 C020 C023 CAP SM 10 UF 50 V 20 X7S 1210 H 106 IN 4 TAIYO YUDEN UMK325C7106MM T C016 C021 CAP SM 10 UF 25 V 10 X7R 1210 H 083 IN 2 MURATA GRM32DR...

Page 44: ...MURATA GRM32ER61C226KE20L C062 C064 C066 C067 C072 C073 C074 C081 C082 C083 C084 C085 C086 C087 C088 C089 C091 C094 C095 C096 C097 C098 C099 C100 C101 C102 C103 C104 C105 CAP SM 0 1 UF 16 V 10 X7R CE...

Page 45: ...0 J011 CONN RCPT HDR D SUB 44 POS PWB MT 2 TE CONNECTIVITY 5748482 5 J017 CONN MICTOR 38 RCPT SM W THRU HOLE GROUND BUS VERT KEYED H 242 IN 1 TE CONNECTIVITY 5767171 1 J018 CONN SM HDR 2X5 100 POST H...

Page 46: ...R002 RES SM 45 3 K 1 16 W 0 5 25 PPM THIN FILM 0402 H 016 IN 1 THIN FILM TECHNOLOGY RR0510P4532D C R003 R010 RES SM 10 7 K 1 16 W 0 5 25 PPM THIN FILM 0402 H 016 IN 2 IRC PCF W0402LF 03 1072 D P LT R0...

Page 47: ...Part Number R012 R014 RES SM 10 1 10 W 50 V 1 THICK FILM 0603 H 020 IN 2 VENKEL CR0603 10W 10R0FT R015 RES SM 0 015 1 W 1 THIN FILM 0815 H 022 IN 1 THIN FILM TECHNOLOGY RL3720WTR015F C R016 R168 RES...

Page 48: ...93 R094 R095 R096 R097 R098 R099 R100 R101 R102 R103 R104 R105 R106 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 R128 R129 R130 R131 R132 R137 R138 R139 R140 R1...

Page 49: ...8K20FKED R024 R107 R109 RES SM 4 7 K OHM 1 16 W 1 THICK FILM 0402 H 016 IN 3 KOA RK73H1ETTP4701F R025 R029 R166 RES SM 1 K 1 16 W 5 THIN FILM 25 PPM 0402 H 016 IN 3 THINFILM RR0510P102D C R030 R033 R0...

Page 50: ...D C R176 R182 R187 R277 R278 RES SM 10 K 1 16 W 50 V 1 THICK FILM 0402 H 014 IN 5 VISHAY DALE CRCW040210K0FKEDC R177 R186 R188 R201 R202 R203 R204 R205 R206 R207 R208 R209 R219 R220 R221 R222 R223 R22...

Page 51: ...981DT R181 RES SM 2 K 1 16 W 5 THIN FILM 25 PPM 0402 H 016 IN 1 THINFILM RR0510P202D C R184 RES SM 10 7 K 1 16 W 0 5 25 PPM THIN FILM 0402 H 016 IN 1 IRC PCF W0402LF 03 1072 D P LT R185 RES SM 49 9 1...

Page 52: ...H 016 IN 1 KOA RK73Z1ETTP R274 R287 R288 RES SM 10 K 1 16 W 5 THIN FILM 25 PPM 0402 H 016 IN 3 VENKEL TFCR0402 16W E 1002DT R280 RES SM 124 1 16 W 0 1 25 PPM THIN FILM 0402 H 016 IN 1 VENKEL TFCR0402...

Page 53: ...U009 IC SM ADP2114ACPZ STEP DOWN SWITCHING REGULATOR LFCSP H 039 IN 2 ANALOG DEVICES ADP2114ACPZ R7 U006 OSC SM 40 000 MHZ 3 3 V LOW CURRENT CONSUMPTION CRYSTAL OSCILLATOR 4 PIN H 047 IN 1 EPSON SG 31...

Page 54: ...TYPE A PRESSFIT H 319 IN 1 ERNI 354142 XJ003 CONN HDR RA UNIV PWR MODULE 8 POS PRESSFIT H 385 IN 1 TE CONNECTIVITY 120958 1 Worldwide Support and Services NI corporate headquarters is located at 1150...

Page 55: ...nts EULAs and third party legal notices in the readme file for your NI product Refer to the Export Compliance Information at ni com legal export compliance for the NI global trade compliance policy an...

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