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Programming Model

1-33

CPU Control Register

The CPU Control Register is accessed via the RD[32:39] data lines of the
upper Falcon device. This 8-bit register is defined as follows:

LEMODE Little Endian Mode. This bit must be set in conjunction

with the LEND bit in the Raven for little-endian mode.

P0/1_TBENProcessor 0/1 Time Base Enable. When this bit is cleared,

the TBEN pin of Processor 0/1 will be driven low.

REG

CPU Control Register - $FEF88300

BIT

FIELD

LEM

1_TB

0_TB

OPER

R/W

RESET

Summary of Contents for MVME2700 Series

Page 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you should be familiar with the publications listed in Appendix A Related Documentation The following conventions are used in this document bold is used for user input that you type just as it appears Bold is also used for commands options and arguments to commands and names of ...

Page 4: ...turers with a flammability rating of 94V 0 WARNING This equipment generates uses and can radiate electro magnetic energy It may cause or be susceptible to electro magnetic interference EMI if not installed and used in a cabinet with adequate EMI protection Motorola and the Motorola symbol are registered trademarks of Motorola Inc PowerStackTM VMEmoduleTM and VMEsystemTM are trademarks of Motorola ...

Page 5: ... or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 6: ... Cache Control Register SXCCR 1 31 CPU Control Register 1 33 ISA Local Resource Bus 1 34 W83C553 PIB Registers 1 34 PC87308VUL Super I O ISASIO Strapping 1 34 NVRAM RTC Watchdog Timer Registers 1 34 Module Configuration and Status Registers 1 35 CPU Configuration Register 1 36 Base Module Feature Register 1 37 Base Module Status Register BMSR 1 38 Seven Segment Display Register 1 39 VME Registers ...

Page 7: ... PCI Map Decoders 2 11 PCI Configuration Space 2 12 PCI Write Posting 2 12 PCI Master 2 13 Generating PCI Memory and I O Cycles 2 13 Generating PCI Configuration Cycles 2 15 Generating PCI Special Cycles 2 15 Generating PCI Interrupt Acknowledge Cycles 2 16 Endian Conversion 2 16 When MPC Devices are Big Endian 2 16 When MPC Devices are Little Endian 2 17 Cycles Originating From PCI 2 18 Error Han...

Page 8: ...sters 2 47 PCI Slave Attribute Offset 0 1 2 and 3 Registers 2 48 CONFIG_ADDRESS 2 49 PCI I O CONFIG_ADDRESS Register 2 50 PCI I O CONFIG_DATA Register 2 51 Raven Interrupt Controller Implementation 2 52 Introduction 2 52 The Raven Interrupt Controller RavenMPIC Features 2 52 Architecture 2 52 CSR s Readability 2 53 Interrupt Source Priority 2 53 Processor s Current Task Priority 2 53 Nesting of In...

Page 9: ...ected Errors Vector Priority Register 2 74 Raven Detected Errors Destination Register 2 75 Interprocessor Interrupt Dispatch Registers 2 76 Interrupt Task Priority Registers 2 76 Interrupt Acknowledge Registers 2 78 End of Interrupt Registers 2 78 Programming Notes 2 79 External Interrupt Service 2 79 Reset State 2 80 Operation 2 81 Interprocessor Interrupts 2 81 Dynamically Changing I O Interrupt...

Page 10: ...t 3 20 Blocks A and or B Present Blocks C and or D present 3 21 DRAM Arbitration 3 21 Chip Defaults 3 22 External Register Set 3 22 CSR Accesses 3 23 Programming Model 3 24 CSR Architecture 3 24 Register Summary 3 29 Detailed Register Bit Descriptions 3 32 Vendor Device Register 3 33 Revision ID General Control Register 3 34 DRAM Attributes Register 3 36 DRAM Base Register 3 37 CLK Frequency Regis...

Page 11: ... Architectural Overview 4 2 VMEbus Interface 4 4 PCI Bus Interface 4 5 Interrupter and Interrupt Handler 4 6 DMA Controller 4 7 Registers Universe Control and Status Registers UCSR 4 7 Universe Register Map 4 8 PCI Reset Problems Associated with the Initial Version of the Universe Chip 4 14 Problem Description 4 14 Examples 4 16 Example 1 MVME2600 Series Board Exhibits Problem 4 16 Example 2 MVME3...

Page 12: ...olvement 5 14 PCI Domain 5 14 PCI SCSI 5 14 PCI Ethernet 5 15 PCI Graphics 5 15 Universe s Involvement 5 15 VMEbus Domain 5 15 ROM Flash Initialization 5 16 APPENDIX A Related Documentation Overview A 1 MCG Customer Services A 2 Motorola Computer Group Documents A 3 Manufacturers Documents A 5 Related Specifications A 10 GLOSSARY Abbreviations Acronyms and Terms to Know GL 1 INDEX ...

Page 13: ...xiv ...

Page 14: ... Falcon Internal CSRs 3 24 Figure 3 5 Data Path for Writes to the Falcon Internal CSRs 3 25 Figure 3 6 Memory Map for Byte Reads to the CSR 3 26 Figure 3 7 Memory Map for Byte Writes to the Internal Register Set and Test SRAM 3 27 Figure 3 8 Memory Map for 4 Byte Reads to the CSR 3 28 Figure 3 9 Memory Map for 4 Byte Writes to the Internal Register Set and Test SRAM 3 28 Figure 3 10 PowerPC Data t...

Page 15: ...xvi ...

Page 16: ...le 1 26 Table 1 15 System Register Summary 1 27 Table 1 16 Strap Pins Configuration for the PC87308VUL 1 34 Table 1 17 MK48T59 559 Access Registers 1 35 Table 1 18 Module Configuration and Status Registers 1 36 Table 1 19 VME Registers 1 40 Table 1 20 Z8536 Z85230 Access Registers 1 45 Table 1 21 Z8536 CIO Port Pins Assignment 1 46 Table 1 22 Interpretation of MID3 MID0 1 48 Table 1 23 PIB DMA Cha...

Page 17: ...Table 3 13 ROM Block A Size Encoding 3 46 Table 3 15 Read Write to ROM Flash 3 47 Table 3 14 rom_a_rv and rom_b_rv encoding 3 47 Table 3 16 ROM Block B Size Encoding 3 50 Table 3 17 Sizing Addresses 3 57 Table 3 18 PowerPC 60x Address to DRAM Address Mappings 3 58 Table 3 19 Syndrome Codes Ordered by Bit in Error 3 59 Table 3 20 Single Bit Errors Ordered by Syndrome Code 3 60 Table 3 21 PowerPC Da...

Page 18: ...lier version of the Universe chip For more details see PCI Reset Problems Associated with the Initial Version of the Universe Chip on page 4 14 Introduction This manual provides programming information for the MVME2600 and MVME2700 Single Board Computers SBCs Extensive programming information is provided for several Application Specific Integrated Circuit ASIC devices used on the boards Reference ...

Page 19: ...sk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition Note In some places in this document an underscore _ following the signal name is used to indicate an active...

Page 20: ...t in a register that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and 1 are used to describe the actual value that should be written to the bit or the value that it yields...

Page 21: ...MB 16 bit wide DRAM 16MB to 256MB ECC Protected Single bit Correction Double bit Detection Two way Interleaved NVRAM 8KB RTC MK48T59 559 Device Peripheral Support Two async serial ports Two sync async serial ports One IEEE1284 or printer Parallel Port 8 bit or 16 bit single ended SCSI interface AUI or 10Base T 100Base TX Ethernet interface NO Graphics Interface on MVME2600 series One PS 2 Keyboard...

Page 22: ...upt controller PCI devices include SCSI VME Ethernet and one PMC slot Standard I O functions are provided by the Super I O device which resides on the ISA bus The NVRAM RTC and the optional synchronous serial ports also reside on the ISA bus The general system block diagram for MVME2600 2700 series is shown below PMC Slots One 32 64 bit Slot Miscellaneous RESET ABORT Switch Status LEDs Table 1 1 M...

Page 23: ...3 604 FLASH 4MB or 8MB PHB MPIC RAVEN ASIC MEMORY CONTROLLER FALCON CHIPSET 64 BIT PMC SLOT PCI EXPANSION 33MHz 32 64 BIT PCI LOCAL BUS PIB W83C553 ETHERNET DEC21140 SCSI 53C825A VME BRIDGE UNIVERSE BUFFERS AUI 10BT 100BTX VME P2 VME P1 RTC NVRAM WD MK48T559 ISA REGISTERS SUPER I O PC87308 ESCC 85230 CIO Z8536 712 761 P2 I O OPTIONS MOUSE KBD FLOPPY LED PARALLEL SERIAL FRONT PANEL ISA BUS 66MHz MP...

Page 24: ...w 160 pin connectors as specified in the proposed VME64 Extension Standard It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors 3 3V supply is regulated onboard from the 5V power Front panel connectors on the MVME2600 2700 series board include a 6 pin circular DIN connector for the keyboard interface a 6 pin circular DIN connector for the mouse interface and a ...

Page 25: ...ted to P2 pin Z31 Additional PCI expansion is supported with a 114 pin Mictor connector This connection allows stacking of a carrier board to increase the I O capability such as a dual PMC carrier board Programming Model Memory Maps The following sections describe the memory maps for the MVME2600 2700 series Processor Memory Maps The Processor memory map is controlled by the Raven ASIC and the Fal...

Page 26: ...of ROM FLASH Bank A appears at this range after a reset if the rom_b_rv control bit is cleared If the rom_b_rv control bit is set then this address range maps to ROM FLASH Bank B Table 1 2 Default Processor Memory Map Processor Address Size Definition Notes Start End 0000 0000 7FFF FFFF 2G Not mapped 8000 0000 8001 FFFF 128K PCI ISA I O Space 1 8002 0000 FEF7 FFFF 2G 16M 640K Not mapped FEF8 0000 ...

Page 27: ...ze Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 2 4000 0000 FCFF FFFF 3G 48M PCI Memory Space 4000 0000 to FCFF FFFF 3 4 8 FD00 0000 FDFF FFFF 16M Zero Based PCI ISA Memory Space mapped to 00000000 to 00FFFFFF 3 8 FE00 0000 FE7F FFFF 8M Zero Based PCI ISA I O Space mapped to 00000000 to 007FFFFF 3 5 8 FE80 0000 FEF7 FFFF 7 5M Reserved FEF8 0000 FEF8 FFFF 64K...

Page 28: ...hown is the recommended setting which uses the Special PCI Slave Image and two of the four programmable PCI Slave Images 9 The only method to generate a PCI Interrupt Acknowledge cycle 8259 IACK is to perform a read access to the Raven s PIACK register at 0xFEFF0030 The following table shows the programmed values for the assoc iated Raven MPC registers for the processor CHRP memory map Table 1 4 R...

Page 29: ..._b_rv control bit is cleared If the rom_b_rv Table 1 5 PREP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 8000 0000 BFFF FFFF 1G Zero Based PCI I O Space 0000 0000 3FFFF FFFF 2 C000 0000 FCFF FFFF 1G 48M Zero Based PCI ISA Memory Space 0000 0000 3CFFFFFF 2 5 FD00 0000 FEF7 FFFF 40 5M Reserved FEF8 0000 FEF8 FFFF 64K F...

Page 30: ...accomplished via the CONFIG_ADD and CONFIG_DAT registers These two registers are implemented by the Raven ASIC In the CHRP memory map example the CONFIG_ADD and CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC respectively With the PREP memory map the CONFIG_ADD register and the CONFIG_DAT register are located at 0x80000CF8 and 0x80000CFC respectively Table 1 6 Raven MPC Register Valu...

Page 31: ...P compatible from the point of view of the PCI local bus Table 1 7 PCI CHRP Memory Map PCI Address Size Definition Notes Start End 0000 0000 top_dram dram_size Onboard ECC DRAM 1 4000 0000 EFFF FFFF 3G 256M VMEbus A32 D32 Super Program 3 F000 0000 F7FF FFFF 128M VMEbus A32 D16 Super Program 3 F800 0000 F8FE FFFF 16M 64K VMEbus A24 D16 Super Program 4 F8FF 0000 F8FF FFFF 64K VMEbus A16 D16 Super Pr...

Page 32: ...e mapping via the four PCI Slave Images in the Universe ASIC 4 Programmable mapping via the Special Slave Image SLSI in the Universe ASIC FC04 0000 FCFF FFFF 16M 256K PCI Memory Space FD00 0000 FDFF FFFF 16M PCI Memory Space or System Memory Alias Space mapped to 00000000 to 00FFFFFF 1 FE00 0000 FFFF FFFF 48M Reserved Table 1 7 PCI CHRP Memory Map Continued PCI Address Size Definition Notes Start ...

Page 33: ...ster Value Aliasing ON 14 RavenMPIC MBASE FC00 0000 FC00 0000 80 PSADD0 0000 3FFF 0100 3FFF 84 PSOFF0 PSATT0 0000 00FX 0000 00FX 88 PSADD1 0000 0000 FD00 FDFF 8C PSOFF1 PSATT1 0000 0000 0000 00FX 90 PSADD2 0000 0000 0000 0000 94 PSOFF2 PSATT2 0000 0000 0000 0000 98 PSADD3 0000 0000 0000 0000 9C PSOFF3 PSATT3 0000 0000 0000 0000 Table 1 9 Universe PCI Register Values for CHRP Memory Map Configurati...

Page 34: ... 130 LSI2_BD XXXX XXXX 134 LSI2_TO XXXX XXXX 13C LSI3_CTL 0000 0000 140 LSI3_BS XXXX XXXX 144 LSI3_BD XXXX XXXX 148 LSI3_TO XXXX XXXX 188 SLSI C0A053F8 Table 1 9 Universe PCI Register Values for CHRP Memory Map Continued Configuration Address Offset Configuration Register Name Register Value ...

Page 35: ...752M VMEbus A32 D32 Super Program 3 3000 0000 37FF FFFF 128M VMEbus A32 D16 Super Program 3 3800 0000 38FE FFFF 16M 64K VMEbus A24 D16 Super Program 4 38FF 0000 38FF FFFF 64K VMEbus A16 D16 Super Program 4 3900 0000 39FE FFFF 16M 64K VMEbus A24 D32 Super Data 4 39FF 0000 39FF FFFF 64K VMEbus A16 D32 Super Data 4 3A00 0000 3AFE FFFF 16M 64K VMEbus A24 D16 User Program 4 3AFF 0000 3AFF FFFF 64K VMEb...

Page 36: ...es for the associated Raven PCI registers for the PREP compatible memory map Table 1 11 Raven PCI Register Values for PREP Memory Map Configuration Address Offset Configuration Register Name Register Value 14 RavenMPIC MBASE FC00 0000 80 PSADD0 8000 FBFF 84 PSOFF0 PSATT0 8000 00FX 88 PSADD1 0000 0000 8C PSOFF1 PSATT1 0000 0000 90 PSADD2 0000 0000 94 PSOFF2 PSATT2 0000 0000 98 PSADD3 0000 0000 9C P...

Page 37: ...ddress Offset Configuration Register Name Register Value 100 LSI0_CTL C082 5100 104 LSI0_BS 0100 0000 108 LSI0_BD 3000 0000 10C LSI0_TO XXXX 0000 114 LSI1_CTL C042 5100 118 LSI1_BS 3000 0000 11C LSI1_BD 3800 0000 120 LSI1_TO XXXX 0000 128 LSI2_CTL 0000 0000 12C LSI2_BS XXXX XXXX 130 LSI2_BD XXXX XXXX 134 LSI2_TO XXXX XXXX 13C LSI3_CTL 0000 0000 140 LSI3_BS XXXX XXXX 144 LSI3_BD XXXX XXXX 148 LSI3_...

Page 38: ...or can access any address range in the VMEbus with the help from the address translation capabilities of the Universe ASIC The recommended mapping is shown in the Processor Memory Map section The following figure illustrates how the VMEbus master mapping is accomplished ...

Page 39: ... 1 Programmable mapping done by the Raven ASIC VMEBUS 11553 00 9609 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 VME A24 VME A16 PROGRAMMABLE SPACE PCI MEMORY PROCESSOR PCI MEMORY SPACE PCI ISA MEMORY SPACE PCI I O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY ...

Page 40: ...e ASIC allow other VMEbus masters to get to any devices on the MVME2600 2700 series The combination of the four Universe VME Slave Images and the four Raven PCI Slave Decoders offers a lot of flexibility for mapping the system resources as seen from the VMEbus In most applications the VMEbus only needs to see the system memory and perhaps the software interrupt registers SIR1 and SIR2 registers An...

Page 41: ...mmable mapping via the four VME Slave Images in the Universe ASIC 2 Programmable mapping via PCI Slave Images in the Raven ASIC 3 Fixed mapping via the PIB device 1896 9609 PCI Memory NOTE 2 NOTE 1 Software INT Registers Processor ISA Space Onboard Memory VMEbus NOTE 1 PCI I O Space NOTE3 ...

Page 42: ...ue CHRP Register Value PREP F00 VSI0_CTL C0F2 0001 C0F2 0001 F04 VSI0_BS 4000 0000 4000 0000 F08 VSI0_BD 4000 1000 4000 1000 F0C VSI0_TO C000 1000 C000 1000 F14 VSI1_CTL E0F2 00C0 E0F2 00C0 F18 VSI1_BS 1000 0000 1000 0000 F1C VSI1_BD 2000 0000 2000 0000 F20 VSI1_TO F000 0000 7000 0000 F28 VSI2_CTL 0000 0000 0000 0000 F2C VSI2_BS XXXX XXXX XXXX XXXX F30 VSI2_BD XXXX XXXX XXXX XXXX F34 VSI2_TO XXXX ...

Page 43: ...p PREP Map Range Mode 4000 0000 4000 0FFF A32 U S P D D08 16 32 4K PCI ISA I O Space 0000 1000 0000 1FFF PCI ISA I O Space 0000 1000 0000 1FFF 1000 0000 1FFF FFFF A32 U S P D D08 16 32 64 RMW 256M PCI ISA Memory Space On board DRAM 0000 0000 0FFF FFFF PCI ISA Memory Space On board DRAM 8000 0000 8FFF FFFF ...

Page 44: ...ol for an external register port This function is utilized by the MVME2600 2700 series to provide the system control registers The following sub sections describe these system registers in detail Table 1 15 System Register Summary BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FEF80400 System Configuration Register Upper Falcon s PR_STAT1 FEF80404 Memory ...

Page 45: ...may appropriately handle any software visible differences For the MVME2600 2700 series this field returns a value of FE SYSCLK System Clock Speed This field relays the system clock speed and the PCI clock speed information as follows SYSXC System External Cache Size This field reflects size of the look aside cache on the system bus REG System Configuration Register FEF80400 BIT 0 1 2 3 4 5 6 7 8 9...

Page 46: ...follows 0b1100 1M 0b1101 512K 0b1110 256K 0b1111 None P0 1STAT Value Processor 0 1 Present External In line Cache Size 0b0000 to 0b0011 Reserved Reserved 0b0100 YES 1M 0b0101 YES 512K 0b0110 YES 256K 0b0111 YES None 0b1000 to 0b1111 NO N A SYSXC Value External Look aside Cache Size ...

Page 47: ...Refresh When this bit is set it indicates that a DRAM block requires faster refresh rate If any of the four blocks requires faster refresh rate then the ram ref control bit should be set M_SPD 0 1 Memory Speed This field relays the memory speed information as follows REG Memory Configuration Register FEF80404 BIT 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 6...

Page 48: ...k consists of four FLASH devices System External Cache Control Register SXCCR The System Cache Control Register is accessed via the RD 32 39 data lines of the upper Falcon device This 8 bit register is defined as follows SXC_DIS_ System External Cache Enable When this bit is cleared it disables this cache from responding to any bus cycles ROM_A B_TYP 0 2 ROM FLASH Type 0b000 to 0b101 Reserved 0b11...

Page 49: ...This may be an issue if other devices cannot wait that long to become MPC bus master SXC_RST_System External Cache Reset When this bit is cleared it invalidates all tags and holds the cache in a reset condition There is a bug in Glance It really does not hold the chip in a reset condition The tag invalidate still works okay though SXC_MI_ System External Cache Miss Inhibit When this bit is cleared...

Page 50: ...as follows LEMODE Little Endian Mode This bit must be set in conjunction with the LEND bit in the Raven for little endian mode P0 1_TBENProcessor 0 1 Time Base Enable When this bit is cleared the TBEN pin of Processor 0 1 will be driven low REG CPU Control Register FEF88300 BIT 0 1 2 3 4 5 6 7 FIELD LEMODE P1_TBEN P0_TBEN OPER R R R W R W R R R R RESET X 0 1 1 X X X X ...

Page 51: ... Data Sheet for additional details and programming information The following table shows the hardware strapping for the Super I O device NVRAM RTC Watchdog Timer Registers The MK48T59 559 provides the MVME2600 2700 series with 8K of non volatile SRAM a time of day clock and a watchdog timer Accesses to the MK48T59559 are accomplished via three registers The NVRAM RTC Address Strobe 0 Register the ...

Page 52: ... of the NVRAM to the NVRAM RTC STB0 register 2 Write the high address A15 A8 of the NVRAM to the NVRAM RTC STB1 register and 3 Then read or write the NVRAM RTC Data Port Refer to the MK48T59 Data Sheet for additional details and programming information Module Configuration and Status Registers Four registers provide the configuration and status information about the board These registers are liste...

Page 53: ...ype and the System Configuration Register should be used to obtain information about the overall system CPUTYPE CPU Type This field will always read as E for the MVME2600 2700 series The System Configuration Register should be used for additional information Table 1 18 Module Configuration and Status Registers PCI I O Address Function 0000 0800 CPU Configuration Register 0000 0802 Base Module Feat...

Page 54: ...MC PCIX Slot 2 contains a PCI Mezzanine Card or a PCI device PMC1P_ PMC Slot 1 Present If set there is no PCI Mezzanine Card installed in the PMC Slot 1 If cleared the PMC Slot 1 contains a PMC VMEP_ VMEbus Present If set there is no VMEbus interface If cleared VMEbus interface is supported GFXP_ Graphics Present If set there is no on board Graphics interface If cleared there is an on board graphi...

Page 55: ...ule Type This eight bit field is used to provide the category of the base module and is defined as follows REG Base Module Status Register Offset 0803 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 FIELD BASE_TYPE OPER R RESET N A BASE_TYPE Value Base Module Type 0 to F9 Reserved FA Reserved Special with MVME712M I O and 100BaseT4 on row Z FB MVME2600 2700 with MVME712M I O FC MVME2600 2700 with MVME761 I O ...

Page 56: ...gisters provide the following functions for the VMEbus interface a software interrupt capability a location monitor function and a geographical address status For these registers to be accessible from the VMEbus the Universe ASIC must be programmed to map the VMEbus Slave Image 0 into the appropriate PCI I O address range Refer to the VMEbus Slave Map section for additional details The following t...

Page 57: ... this bit will set the SIG1 status bit SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit Table 1 19 VME Registers PCI I O Address Function 0000 1000 SIG LM Control Register 0000 1001 SIG LM Status Register 0000 1002 VMEbus Location Monitor Upper Base Address 0000 1003 VMEbus Location Monitor Lower Base Address 0000 1004 VMEbus Semaphore Register 1 0000 1005 VMEbus Semaphore Register 2 ...

Page 58: ... a method to generate interrupts The Universe ASIC is programmed so that this register can be accessed from the VMEbus to provide a capability to generate software interrupts to the onboard processor s from the VMEbus EN_SIG1 When the EN_SIG1 bit is set a LM SIG Interrupt 1 is generated if the SIG1 bit is asserted EN_SIG0 When the EN_SIG0 bit is set a LM SIG Interrupt 0 is generated if the SIG0 bi...

Page 59: ...R_LM1 control bit LM0 LM0 status bit This bit can be set by either the location monitor function or the SET_LM0 control bit LM0 correspond to offset 1 from the location monitor base address This bit can only be cleared by a reset or by writing a 1 to the CLR_LM0 control bit Location Monitor Upper Base Address Register The Location Monitor Upper Base Address Register is an 8 bit register located at...

Page 60: ...Semaphore Register 1 is an 8 bit register located at ISA I O address x1004 The Universe ASIC is programmed so that this register can be accessible from the VMEbus This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared When bit 7 is high this register will not latch in the new value if the new value has the most significant bit set REG Location Mo...

Page 61: ... an 8 bit read only register located at ISA I O address x1006 This register reflects the states of the geographical address pins at the 5 row 160 pin P1 connector Z85230 ESCC and Z8536 CIO Registers and Port Pins The Z85230 ESCC is used to provide the two sync async serial ports on some MVME2600 2700 series models The PCLK which can be used to derived the baud rates is 10 MHz Refer to the SCC User...

Page 62: ... is also defined to retrieve interrupt vectors from these devices The Z8536 CIO has higher priority than the Z85230 ESCC in the interrupt daisy chain The following list the registers associated with accessing these two devices Table 1 20 Z8536 Z85230 Access Registers PCI I O Address Function 0000 0840 Z85230 Port B Serial Port 4 Control 0000 0841 Z85230 Port B Serial Port 4 Data 0000 0842 Z85230 P...

Page 63: ...DSEL 0 Port 3 ID Select IDREQ_ 0 MODSEL 1 Port 4 ID Select PA4 RLB3_ Output Port 3 Remote Loopback PA5 DTR3_ Output Port 3 Data Terminal Ready PA6 BRDFAIL Output Board Fail When set will cause FAIL LED to be lit PA7 IDREQ_ Output Module ID Request low true PB0 TM4_ MID2 Input Port 4 Test Mode when IDREQ_ 1 Module ID Bit 2 when IDREQ_ 0 PB1 DSR4_ MID3 Input Port 4 Data Set Ready when IDREQ_ 1 Modul...

Page 64: ...the polarity of the Z8536 s port pins are software programmable PC0 Reserved I O Reserved PC1 Reserved I O Reserved PC2 Reserved I O Reserved PC3 Reserved I O Table 1 21 Z8536 CIO Port Pins Assignment Continued Port Pin Signal Name Direction Descriptions ...

Page 65: ...DREQ_ The waiting time should be about 4 microseconds because the sampling rate is about 1 6 microsecond with a 10MHz MXCLK clock Table 1 22 Interpretation of MID3 MID0 IDREQ_ LLB3_ MODSEL MID3 MID2 MID1 MID0 Serial Module Type Module Assembly Number 1 X X X X X Invalid module ID 0 0 0 0 0 0 Module 3 EIA232 DCE 01 W3876B01 0 0 0 0 0 1 Module 3 EIA232 DTE 01 W3877B01 0 0 0 0 1 0 Module 3 EIA530 DCE...

Page 66: ...6 bit DMA Channels only every other byte the even bytes from memory is valid Table 1 23 PIB DMA Channel Assignments PIB Priority PIB Label Controller DMA Assignment Highest Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx Channel 2 Floppy Drive Controller Channel 3 Parallel Port Channel 4 DMA2 Not available Cascaded from DMA1 Channel 5 Ser...

Page 67: ...1 50 Board Description and Memory Maps 1 ...

Page 68: ...duct This I O bus must be robust and efficient enough to handle the high bandwidth burst oriented traffic required for Ethernet SCSI graphics and VMEbus interfaces PCI is a high performance 32 bit or 64 bit burst mode synchronous bus capable of transfer rates of 132 MByte sec in 32 bit mode or 264 MByte sec in 64 bit mode While the PCI specification is relatively new it has received overwhelming s...

Page 69: ...ers Four independent software programmable slave map decoders Multi level write post FIFO for writes to PCI Support for MPC bus clock speeds up to 66 MHz Selectable big or little endian operation PCI Interface Fully PCI Rev 2 0 compliant 32 bit or 64 bit address data bus Support for accesses to all four PCI address spaces Single level write posting buffers for writes to the MPC bus Read ahead buff...

Page 70: ...Introduction 2 3 2 Four 31 bit tick timers Two 64 bit general purpose registers for cross processor messaging ...

Page 71: ...lock Diagram Figure 2 1 Raven Block Diagram 1914 9610 Data Path B Mux FIFO Endian Mux FIFO Endian Data Path A PCI Regs MPIC PCI Dec Mux Reg Mux Reg PCI Slave MPC Slave Reg Reg MPC Dec PCIADIN PCI Master Mux PCI MPC Master MPC Arbiter MPC Regs Raven PCI Bus MPC Bus Mux MPC ...

Page 72: ...ot provide data bus arbitration Determining data bus ownership is the responsibility of each MPC master and follows the ownership ordering established on the address bus The MPC Arbiter supports a total of four participants One participant is the Raven MPC master function which represents PCI initiated MPC transactions The remaining three participants are external to the Raven and are represented ...

Page 73: ...er that guarantees single level pipelined depth This mode is controlled by the GLMD bit within the MPC Arbiter Control register The default state is to have this mode disabled There is another special mode called Benign Address Retry Mode This mode was designed to compensate for an anomaly discovered when running a PPC603 and a pair of early release Falcon memory controllers It is possible that co...

Page 74: ...gisters from the MPC bus These registers may be accessed using only 1 2 3 4 or 8 byte operations The location of the MPC register file is fixed beginning at MPC address FEFE0000 or FEFF0000 depending on the state of the EXT01 bit at the time RST is MPC Address Function 00000000 7FFFFFFF System Memory 2G 80000000 FCFFFFFF PCI Memory 2G 48M FD000000 FDFFFFFFF ISA Memory 16M FE000000 FE7FFFFF Discont...

Page 75: ...sting and define the PCI transfer characteristics Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the MPC address and the result is used as the PCI address This offset allows PCI devices to reside at any PCI address independent of the MPC address map Care should be taken to assure that all programmable decoders decode uniqu...

Page 76: ...e line worth onto the MPC bus This will allow the PCI slave to receive long block transfers without stalling When programmed in read ahead mode the RAEN bit in the PSATTx register is set and the PCI slave receives a Memory Read Line or Memory Read Multiple command the MPC master will fetch data in bursts and store it in the FIFO The contents of the FIFO will then be used to attempt to satisfy the ...

Page 77: ...mental to the host CPU s performance The Bus Hog mode can be controlled by the BHOG bit within the GCSR The default state for BHOG is disabled MPC Bus Timer The MPC bus timer allows the current bus master to recover from a lock up condition caused when no slave responds to the transfer request The time out length of the bus timer is determined by the MBT field in the Global Control Status Register...

Page 78: ...of the MCLK input PCI Map Decoders The Raven contains four programmable decoders which provide windows into the MPC bus from the PCI bus The most significant 16 bits of the PCI address is compared with the address range of each map decoder and if the address falls within the specified range the access is passed on to the MPC bus For each map there is an independent set of attributes These attribut...

Page 79: ...its maximum bandwidth and the faster MPC bus to accept data in high performance cache line burst transfers Only one PCI transaction may be write posted at any given time If the Raven is busy processing a previous write posted transaction when a new PCI transaction begins the next PCI transaction will be delayed TRDY will not be asserted until the previous transaction has completed If during a tran...

Page 80: ... mode the PCI master will continue to transfer the remaining data in 32 bit mode The PCI Command Codes generated by the PCI master depend on the MPC transfer type TBST and the MEM field in the MSATTx registers Table 2 3 PCI Command Codes Generating PCI Memory and I O Cycles Each programmable slave may be configured to generate PCI I O or memory accesses through the MEM and IOM fields in its Attrib...

Page 81: ...MSOFFx register and map the result directly to PCI When MEM is clear and IOM is set the Raven will take the MPC address apply the offset specified in the MSOFFx register and map the result to PCI as shown in Figure 2 2 Figure 2 2 PCI Spread I O Cycle Mapping This CHRP compliant spread I O mode allows each PCI device s I O registers to reside on a different MPC memory page so device drivers can be ...

Page 82: ... to access PCI I O space with an MPC address of 80000000 The resource at CF8 is a 32 bit configuration address port and is referred to as the CONFIG_ADDRESS register The resource at CFC is a 32 bit configuration data port and is referred to as the CONFIG_DATA register Accessing a PCI functions s configuration port is a two step process Write the bus number physical device number function number an...

Page 83: ...knowledge cycle the Raven will present the resulting vector information obtained from the PCI bus as read data Endian Conversion The Raven supports both Big and Little Endian data formats Since PCI is inherently Little Endian conversion is necessary if all MPC devices are configured for Big Endian operation The Raven may be programmed to perform the Endian conversion described below When MPC Devic...

Page 84: ...der processor bus address bits are exclusive ORed with a three bit value that depends on the length of the operand as shown in Table 2 4 1916 9610 DH07 00 DH15 08 DH23 16 DH31 24 DL07 00 DL15 08 DL23 16 DL31 24 D0 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 AD63 56 AD55 48 AD47 40 AD39 32 AD31 24 AD23 16 AD15 08 AD07 00 DH07 00 DH15 08 DH23 16 DH31 24 DL07 00 DL15 08 DL23 ...

Page 85: ... mode The modification will be the same as that described in Section 3 7 2 above Since this method has some difficulties dealing with unaligned transfers the Raven will break up all unaligned PCI transfers into multiple aligned transfers on the MPC bus Error Handling The Raven will be capable of detecting and reporting the following errors to one or more MPC masters MPC address bus time out PCI ma...

Page 86: ... programmed to generate a machine check and or a standard interrupt The error response is programmed through the MPC Error Enable Register on a source by source basis When a machine check is enabled either the MID field in the MPC Error Attribute Register or the DFLT bit in the MEREN Register determine the master to which the machine check is directed For errors in which the master who originated ...

Page 87: ...ty If the MPC Slave function determines there will be contention between a cycle completing on the MPC bus and an incoming PCI cycle the MPC Slave will issue a retry for the current MPC transaction This retry will free up the MPC bus and allow the PCI initiated transaction to complete An idle MPC bus obviously gives immediate access to the pending PCI initiated transaction If the MPC bus is curren...

Page 88: ...as a programmable option to guarantee all PCI write posted transactions are completed before an MPC initiated read transaction may be allowed to complete This option is controlled by the FLBRD bit in the GSCR register If this bit is set all MPC read transactions will be retried until all posted PCI write transactions have completed It is recommended that this option be disabled and the FLBRD bit b...

Page 89: ...are accessible from the MPC bus through the Raven The MPC Registers are described first the PCI Configuration Registers are described next The following conventions are used in the Raven register charts R Read Only field R W Read Write field S Writing a ONE to this field sets this field C Writing a ONE to this field clears this field MPC Registers The Raven MPC register map is shown in Table 2 5 T...

Page 90: ... MSOFF1 MSATT1 FEFF0050 MSADD2 FEFF0054 MSOFF2 MSATT2 FEFF0058 MSADD3 FEFF005C MSOFF3 MSATT3 FEFF0060 FEFF0064 FFEF0068 FEFF006C FEFF0070 GPREG0 Upper FEFF0074 GPREG0 Lower FEFF078 GPREG1 Upper FEFF07C GPREG1 Lower Table 2 5 Raven MPC Register Map Continued Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 ...

Page 91: ... The Raven will always return 4801 This register is duplicated in the PCI Configuration Registers Revision ID Register REVID Revision ID This register identifies the Raven revision level This register is duplicated in the PCI Configuration Registers Address FEFF0000 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name VENID DEVID Oper...

Page 92: ...etion Please refer to the section on PCI MPC Contention Handling for more information BHOG Bus Hog If set the Raven MPC master will operate in the Bus Hog mode Bus Hog mode means the MPC master will continually request the MPC bus for the entire duration of each PCI transfer If Bus Hog is not enabled the MPC master will request the bus in a normal manner Please refer to the section on MPC Master f...

Page 93: ...aven internal MPIC interrupt controller is enabled This bit is set if EXT15 is high on the rising edge of RESET If cleared Raven detected errors will be passed on to processor 0 INT pin MIDx Master ID This field is encoded as shown below to indicate who is currently the MPC bus master When the internal MPC arbiter is enabled MARB is set these bits are controlled by the internal arbiter When the in...

Page 94: ...ects the state of one of the external interrupt input pins on the rising edge of RESET This register may be used to report hardware configuration parameters to system software MID Current MPC Data Bus Master 00 device on ABG0 01 device on ABG1 10 device on ABG2 11 Raven ...

Page 95: ...er on the bus when no bus requests are pending If cleared no MPC master will be granted the bus without first asserting its ABRx PKMD Bus Parking Mode When bus parking is enabled PKEN is set this bit defines the method used to determine which MPC master is parked on the bus If set the master specified in the DEFM field is parked on the bus when no bus requests are pending If cleared the last activ...

Page 96: ...arked on the bus when default parking is enabled DEFM only has meaning when PRKEN and PRKMD are both set Prescaler Adjust Register PADJ Prescaler Adjust This register is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is 1 MHz The scale factor is calculated as follows PADJ 256 Clk DEFM1 DEFM0 Parked Device 0 0 device on ABR0 0 1 device on ABR1 1 0 de...

Page 97: ...the MPC master For example in event of a PCI parity error for a transaction in which the Raven s PCI master was not involved the MPC master ID can not be determined When DFLT is set MCHK1 is used When DFLT is clear MCHK0 will be used Frequency PADJ 66 B4 50 CE 40 D8 33 DF 25 E7 Address FEFF0020 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 ...

Page 98: ...nable When this bit is set the SMA bit in the MERST register will be used to assert the MCHK output to the bus master which initiated the transaction When this bit is clear MCHK will not be asserted RTAM PCI Master Received Target Abort Machine Check Enable When this bit is set the RTA bit in the MERST register will be used to assert the MCHK output to the bus master which initiated the transactio...

Page 99: ...s bit is set the RTA bit in the MERST register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted MPC Error Status Register OVF Error Status Overflow This bit is set when any error is detected and any of the error status bits are already set It may be cleared by writing a 1 to it writing a 0 to it has no effect MATO MPC Ad...

Page 100: ...n the MEREN register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the MERAT register When the SERRI bit in the MEREN register is set the assertion of this bit will assert an interrupt through the MPIC interrupt controller SMA PCI Master Signalled Master Abort This bit is set when the PCI master signals master abort to terminate a PCI transaction It ...

Page 101: ...bits are set in the MERST register MPC Error Attribute Register MERAT If the PERR or SERR bits are set in the MERST register the contents of the MERAT register are zero If the MATO bit is set the register is defined by the following figure Address FEFF0028 Bit 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 Name MERAD Operation R Reset 00...

Page 102: ...er is defined by the following figure WP Write Post Completion This bit is set when the PCI master detects an error while completing a write post transfer MIDx MPC Master ID This field contains the ID of the MPC master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register COMMx PCI Command This field contains the PCI command of...

Page 103: ...ter will initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the Raven will present the resulting vector information obtained from the PCI bus as read data Address FEFF0030 Bit 0 1 2 3 4 5 6 7 8 9 1 0 ...

Page 104: ...ll be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming MPC address END End Address This field determines the end address of a particular memory area on the MPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming MPC address Address MSADD0 FEFF0040 MSADD1 FE...

Page 105: ...te a PCI cycle from the MPC bus the MPC address must be greater than or equal to the START field and less than or equal to the END field START Start Address This field determines the start address of a particular memory area on the MPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming MPC address END End Address This ...

Page 106: ...ding MPC slave is enabled for write transactions WPEN Write Post Enable If set write posting is enabled for the corresponding MPC slave MEM PCI Memory Cycle If set the corresponding MPC slave will generate transfers to or from PCI memory space When clear the corresponding MPC slave will generate transfers to or from PCI I O space using the addressing mode defined by the IOM field Address MSOFF0 MS...

Page 107: ...etermine the PCI address used for transfers from the MPC bus to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the MPC bus It is initialized to 8000 to facilitate a zero based access to PCI space REN Read Enable If set the corresponding MPC slave is enabled for read transactions WEN Write Enable If set the corresponding MPC slave is enabled for ...

Page 108: ...I Local Bus Specification Revision 2 0 The CONFIG_ADDRESS and CONFIG_DATA registers described in this section are accessed within PCI I O space All write operations to reserved registers will be treated as no ops That is the access will be completed normally on the bus and the data will be discarded Read accesses to reserved or unimplemented registers will be completed normally and a data value of...

Page 109: ...1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Bit DEVID VENID 00 PSTAT PCOMM 04 CLASS REVID 08 0C IOBASE 10 MEMBASE 14 18 7F PSADD0 80 PSOFF0 PSATT0 84 PSADD1 88 PSOFF1 PSATT1 8C PSADD2 90 PSOFF2 PSATT2 94 PSADD3 98 PSOFF3 PSATT3 9C 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Bit CONFIG_ADDRESS CF8 CONFIG_DATA CFC ...

Page 110: ... Raven will respond to PCI I O accesses when appropriate If cleared the Raven will not respond to PCI I O space accesses Offset 00 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name DEVID VENID Operation R R Reset 4801 1057 Offset 04 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 ...

Page 111: ...ast Back to Back Capable This bit indicates that the Raven is capable of accepting fast back to back transactions with different targets DPAR Data Parity Detected This bit is set when three conditions are met 1 the Raven asserted PERR itself or observed PERR asserted 2 the Raven was the PCI master for the transfer in which the error occurred 3 the PERR bit in the PCI Command Register is set This b...

Page 112: ...ty error even if parity error checking is disabled see bit PERR in the PCI Command Register It is cleared by writing it to 1 writing a 0 has no effect Revision ID Class Code Registers REVID Revision ID This register identifies the Raven revision level This register is duplicated in the MPC Registers CLASS Class Code This register identifies Raven as the following Base Class Code 06 PCI Bridge Devi...

Page 113: ...ne the I O space base address of the MPIC control registers The IOBASE decoder is disabled when the IOBASE value is zero Memory Base Register Offset 10 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name IOBASE IOBA RES IO MEM Operation R W R R R Reset 0000 0000 0 1 Offset 14 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 ...

Page 114: ... MPIC registers are not prefetchable MEMBA Memory Base Address These bits define the memory space base address of the MPIC control registers The MBASE decoder is disabled when the MBASE value is zero PCI Slave Address 0 1 2 and 3 Registers To initiate an MPC cycle from the PCI bus the PCI address must be greater than or equal to the START field and less than or equal to the END field Offset PSADD0...

Page 115: ...CI Slave Attribute Offset 0 1 2 and 3 Registers INV Invalidate Enable If set the MPC master will issue a transfer type code which specifies the current transaction should cause an invalidate for each MPC transaction originated by the corresponding PCI slave The transfer type codes generated are shown in Table 2 3 GBL Global Enable If set the MPC master will assert the GBL pin for each MPC transact...

Page 116: ...resses that would not normally be visible from PCI CONFIG_ADDRESS The routing of the MPC data bus to and from the CONFIG_ADDRESS register depends on the endian bit setting Refer to the sections on Endian Conversion and the LEND bit in the GCSR The following register diagrams have two additional rows of information These rows indicate the source bit positions on the MPC data bus when data is writte...

Page 117: ...nfiguration cycle This field must be all ones for Special cycles DEV Device Number For PCI Configuration cycles bits 15 through 11 identify the target physical PCI device number Raven does a decode of the Device Number field to assert the appropriate IDSEL line Values of 01 through 0a and 1f are illegal entries for the device number The Raven will drive all 0 s in bit position AD11 through AD31 if...

Page 118: ...a one enabling the translation of a subsequent host bus I O access to the CONFIG_DATA register into a configuration access on the PCI bus If bit 31 is zero and the processor initiates an I O read from or write to the CONFIG_DATA register the transaction is passed through to the PCI bus as a PCI I O transaction PCI I O CONFIG_DATA Register If the CONFIG_ADDRESS register is initialized for a PCI Con...

Page 119: ...t delivery for external I O interrupts Direct Multicast interrupt delivery for Interprocessor and timer interrupts Four Interprocessor Interrupt sources Four timers Processor initialization control Architecture The Raven PCI Slave implements two address decoders for placing the RavenMPIC registers in PCI IO or PCI Memory space Access to these registers require MPC and PCI bus mastership These acce...

Page 120: ... in the range from 0 to 15 where 15 is the highest In order for delivery of an interrupt to take place the priority of the source must be greater than that of the destination processor Therefore setting a source priority to zero inhibits that interrupt Processor s Current Task Priority Each processor has a task priority register which is set by system software to indicate the relative importance o...

Page 121: ...or the other processor or both processors There are four Interprocessor Interrupts IPI channels The interrupts are initiated by writing a bit in the IPI dispatch registers If subsequent IPIs are initiated before the first is acknowledged only one IPI will be generated The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor 8259 Compatibility The RavenM...

Page 122: ...ld be consistent Timers There is a divide by eight pre scaler which is synchronized to the Raven clock MPC processor clock The output of the prescaler enables the decrement of the four timers The timers may be used for system timing or to generate periodic interrupts Each timer has four registers which are used for configuration and control They are Current Count Register Base Count Register Vecto...

Page 123: ...ssor Therefore for externally sourced or I O interrupts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of the interrupt is greater than any interrupt which is in service for that processor and when the priority of that interrupt is t...

Page 124: ...very logic If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested the logic implementation this section can be skipped Figure 2 4 RavenMPIC Block Diagram 1917 9610 IPR Interrupt Selector_1 IRR_1 Interrupt Router ISR_1 interrupt signals Program Visible Registers Interrupt Selector_0 IRR_0 ISR_0 INT1 INT 0 ...

Page 125: ... generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers are used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when the MASK bit is lowe...

Page 126: ...e identification of each interrupt which is in service Therefore there is one bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router The Interrupt Router monitors the outputs from the ISRs Current Task Priority Registers Destination Registers and the IRRs to determine when to assert a processor s INT pin When considering the following rule sets it ...

Page 127: ...rupt The priority from IRR_0 is greater than the highest priority in ISR_0 The priority from IRR_0 is greater than the contents of task register_0 Set2 The source ID in IRR_0 is from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR_0 is not present is ISR_1 The priority from IRR_0 is greater than the highest priority in ISR_0 The priority from I...

Page 128: ...ress offset from the base address of the RavenMPIC registers in the MPC IO or MPC MEMORY space Note that this map does not depict linear addressing The Raven PCI SLAVE has two decoders for generating the RavenMPIC select These decoders will generate a select and acknowledge all accesses which are in a reserved 256K byte range If the index into that 256K block does not decode a valid RavenMPIC regi...

Page 129: ...STER 01150 TIMER 1VECTOR PRIORITY REGISTER 01160 TIMER 1DESTINATION REGISTER 01170 TIMER 2 CURRENT COUNT REGISTER 01180 TIMER 2 BASE COUNT REGISTER 01190 TIMER 2 VECTOR PRIORITY REGISTER 011a0 TIMER 2 DESTINATION REGISTER 011b0 TIMER 3 CURRENT COUNT REGISTER 011c0 TIMER 3 BASE COUNT REGISTER 011d0 TIMER 3 VECTOR PRIORITY REGISTER 011e0 TIMER 3 DESTINATION REGISTER 011f0 INT SRC 0 VECTOR PRIORITY R...

Page 130: ...10100 INT SRC 8 DESTINATION REGISTER 10110 INT SRC 9 VECTOR PRIORITY REGISTER 10120 INT SRC 9 DESTINATION REGISTER 10130 INT SRC 10 VECTOR PRIORITY REGISTER 10140 INT SRC 10 DESTINATION REGISTER 10150 INT SRC 11 VECTOR PRIORITY REGISTER 10160 INT SRC 11 DESTINATION REGISTER 10170 INT SRC 12 VECTOR PRIORITY REGISTER 10180 INT SRC 12 DESTINATION REGISTER 10190 INT SRC 13 VECTOR PRIORITY REGISTER 101...

Page 131: ...20060 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER P0 200a0 EOI REGISTER P0 200b0 IPI 0 DISPATCH REGISTER PROC 1 21040 IPI 1 DISPATCH REGISTER PROC 1 21050 IPI 2 DISPATCH REGISTER PROC 1 21060 IPI 3 DISPATCH REGISTER PROC 1 21070 CURRENT TASK PRIORITY REGISTER PROC 1 21080 IACK REGISTER P1 210a0 EOI REGISTER P1 210b0 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4...

Page 132: ...supported There are two CPUs supported by this design CPU 0 and CPU 1 VID VERSION ID Version ID for this interrupt controller This value reports what level of the specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification Offset 01000 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 ...

Page 133: ...put pin 0 In the pass through mode interrupt source 0 is passed directly through to the processor 0 INT pin MPIC is essentially disabled In the mixed mode 8259 interrupts are delivered using the priority and distribution mechanism of MPIC The Vector Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources Offset 01020 ...

Page 134: ...rocessor Init Register P1 PROCESSOR 1 Writing a 1 to P1 will assert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal P0 PROCESSOR 0 Writing a 1 to P0 will assert the Soft Reset input of processor 0 Writing a 0 to it will negate the SRESET signal Offset 01080 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 ...

Page 135: ...in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector Offse...

Page 136: ...o system initialization code must initialize this register to one eighth the MPIC clock frequency For the Raven implementation of MPIC a typical value would be 7de290 which is 66 8 MHz or 8 25 MHz Offset 010E0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name VECTOR Operation R R R R W Reset 00 00 00 FF Offset 010F0 Bit 3 1 3 0 2 9...

Page 137: ... Registers CI COUNT INHIBIT Setting this bit to one inhibits counting for this timer Setting this bit to zero allows counting to proceed Offset Timer 0 01100 Timer 1 01140 Timer 2 01180 Timer 3 011C0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER CURRENT COUNT T CC Operation R R Reset 0 00000000 Offset Timer 0 01110 Timer ...

Page 138: ...n the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR Thi...

Page 139: ...ssor 0 External Source Vector Priority Registers Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 3 011F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name TIMER DESTINATION P1 P0 Operation R R R R R W R W Reset 00 00 00 00 0 0 Offset Int Src 0 10000 Int Src 2 Int Src15 10020 101E0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 ...

Page 140: ... or negative edge Setting this bit to a one enables active high or positive edge Only External Interrupt Source 0 uses this bit in this register SENSE SENSE This bit sets the sense for external interrupts Setting this bit to a zero enables edge sensitive interrupts Setting this bit to a one enables level sensitive interrupts For external interrupt sources 1 through 15 setting this bit to a zero en...

Page 141: ...rrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated Offset Int Src 0 10010 Int Src 2 Int Src 15 10030 101F0 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name EXTERNAL SOURCE DESTINATION P1 P0 Operation R R R R R W R W Reset 00 00 0...

Page 142: ... that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgedment of the interrupt associated with this vector Raven Detected Errors Destination Register This register indicates the possible destinations for the Raven detected error interrupt source These interrupts operate in the Distributed interrupt de...

Page 143: ... Reading these registers returns zeros P1 PROCESSOR 1 The interrupt is directed to processor 1 P0 PROCESSOR 0 The interrupt is directed to processor 0 Interrupt Task Priority Registers Offset Processor 0 20040 20050 20060 20070 Processor 1 21040 21050 21060 21070 Bit 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name IPI DISPATCH P1 P0 ...

Page 144: ...er per processor Priority levels from 0 lowest to 15 highest are supported Setting the Task Priority Register to 15 masks all interrupts to this processor Hardware will set the task register to F when it is reset or when the Init bit associated with this processor is written to a one ...

Page 145: ...out a pending interrupt will return a value of FF hex End of Interrupt Registers EOI END OF INTERRUPT There is one EOI register per processor EOI Code values other than 0 are currently undefined Data values written to this register are ignored zero is assumed Writing to this register signals the end of processing for the highest priority interrupt currently in Offset Processor 0 200A0 Processor 1 ...

Page 146: ...t Acknowledge request to read the interrupt vector from the MPIC If the interrupt vector indicates the interrupt source is the 8259 the interrupt handler issues a second Interrupt Acknowledge request to read the interrupt vector from the 8259 The RavenMPIC does not interact with the vector fetch from the 8259 5 The interrupt handler saves the processor state and other interrupt specific informatio...

Page 147: ...ontroller ISA devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA device and system memory If interrupts from ISA devices are directly connected to the RavenMPIC bypassing the 8259 the device driver interrupt service routine must read status from the ISA device to ensure buffers between the device and system memory are flushed Reset State After a power on rese...

Page 148: ... for the originating processor Dynamically Changing I O Interrupt Configuration The interrupt controller provides a mechanism for safely changing the vector priority or destination of I O interrupt sources This is provided to support systems which allow dynamic configuration of I O devices In order to change the vector priority or destination of an active interrupt source the following sequence sh...

Page 149: ...he interrupt delivery modes Current Task Priority Level Each processor has a separate Current Task Priority Level register The system software uses this register to indicate the relative priority of the task running on the corresponding processor The interrupt controller will not deliver an interrupt to a processor unless it has a priority level which is greater than the current task priority leve...

Page 150: ... the task priority register should be updated only when the processor enter or exits an idle state Only when the task priority register is integrated within the processor such that it can be accessed as quickly as the MSRee bit for example should the architecture require the task priority register to be updated synchronously with instruction execution ...

Page 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...

Page 152: ...ormation for using the device in a system programming it in a system and testing it is contained here Bit Ordering Convention All Falcon bused signals are named using big endian bit ordering bit 0 is the most significant bit Features DRAM Interface Double bit error detect Single bit error correct on 72 bit basis Up to four blocks Programmable base address for each block Two way interleave factor B...

Page 153: ...Chip has no TEA_ pin ROM Flash Interface Two blocks with two 8 bit devices or two 32 bit devices per block Block Diagrams Figure 3 1 depicts a Falcon pair as it would be connected in a system Figure 3 2 shows the Falcon s internal data paths Figure 3 3 shows the overall DRAM connections ...

Page 154: ...ALCON FALCON Lower DRAM ARRAYS Check Data Upper DRAM ARRAYS Data 32Bits Lower DRAM Data 64 Bits Lower DRAM Address Control Lower DRAM Check bits 8 Bits Upper DRAM Data 64 Bits Upper DRAM Address Control Upper DRAM Check bits 8 Bits Upper PowerPC Data 32 Bits PowerPC Address Control Serial Bus PowerPC 60x Bus ...

Page 155: ...re 3 2 Falcon Internal Data Paths Simplified 1901 9609 64 Bits PowerPC Side RD 0 63 HAMGEN DFF s HAMGEN DRAM Side LATCHES CKD 0 7 MUX D 0 31 64 Bits 64 Bits Latched D 64 Bits Corrected Data 8 Bits 8 Bits 8 Bits SYNDEC 64 Bits Uncorrected Data 64 Bits ...

Page 156: ...PER DRAM BLOCK B UPPER DRAM BLOCK C UPPER DRAM BLOCK D UPPER BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ RD0 63 CKD0 7 1902 9609 LOWER FALCON UPPER FALCON DRAM BLOCK A LOWER DRAM BLOCK B LOWER DRAM BLOCK C LOWER DRAM BLOCK D LOWER BD_RAS_ CAS_ AC_RAS_ CAS_ RA OE_ WE_ RD0 63 CKD0 7 ...

Page 157: ...es the full 144 bit width of DRAM at once so that when the DRAM access time is reached not only is the first 64 bit double word of data ready to be transferred to the PowerPC 60x bus master but so is the next While the Falcon pair is presenting the first two double words to the PowerPC 60x bus it cycles CAS without cycling RAS to obtain the next two double words The Falcon pair transfers the next ...

Page 158: ...DRAM in order to complete When the Falcon pair can take advantage of address pipelining back to back single beat writes take 10 clocks to complete DRAM Speeds The Falcon pair can be configured for 3 different speeds of DRAM 50ns 60ns and 70ns When the Falcon pair is configured for 50ns DRAMs it assumes that the devices are Hyper Page parts When the Falcon pair is configured for 70ns DRAMs it assum...

Page 159: ...Timing When Configured for 70ns Page Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 10 1 3 1 15 4 Beat Read after Idle Quad word misaligned 10 4 1 1 16 4 Beat Read after 4 Beat Read Quad word aligned 9 3 1 1 3 1 14 8 4 Beat Read after 4 Beat Read misaligned 7 2 1 4 1 1 13 8 4 Beat Write after Idle 4 1 1 1 7 4...

Page 160: ...cific instances may be longer or shorter ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 9 1 2 1 13 4 Beat Read after Idle Quad word misaligned 9 3 1 1 14 4 Beat Read after 4 Beat Read Quad word aligned 7 3 1 1 2 1 11 7 4 Beat Read after 4 Beat Read misaligned 6 2 1 3 1 1 11 7 4 Beat Write after Idle 4 1 1 1 7 4 Beat ...

Page 161: ...es and specific instances may be longer or shorter ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 8 1 1 1 11 4 Beat Read after Idle Quad word misaligned 8 2 1 1 12 4 Beat Read after 4 Beat Read Quad word aligned 5 2 1 1 1 1 8 5 4 Beat Read after 4 Beat Read misaligned 4 2 1 2 1 1 8 6 4 Beat Write after Idle 4 1 1 1 7...

Page 162: ...ash Access Timing When Configured for 32 64 bit Devices Table 3 5 PowerPC 60x Bus to ROM Flash Access Timing When Configured for 8 bit Devices ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read 20 16 16 16 68 4 Beat Write N A N A N A N A N A 1 Beat Read 20 20 1 Beat Write 19 19 ACCESS TYPE CLOCK PERIODS REQUIRED FOR Total Clocks 1st Beat 2nd Beat 3r...

Page 163: ... associated data transfer the Falcon pair begins a read or write cycle to the accessed entity DRAM ROM Flash Internal Register as soon as the entity is free If the data transfer will be a read the Falcon pair begins providing data to the PowerPC 60x bus as soon as the entity has data ready and the PowerPC 60x data bus is granted If the data transfer will be a write the Falcon pair begins latching ...

Page 164: ...ed through a Falcon which multiplexes it with half of the DRAM data bus Each Falcon connects to 64 DRAM data bits and to 8 DRAM check bits The total DRAM array width is 144 bits 2 64 8 Cycle Types To support ECC the Falcon pair always deals with DRAM using full width 144 bit accesses When the PowerPC 60x bus master requests any size read of DRAM the Falcon pair reads 144 bits at least once When th...

Page 165: ... the write data and write the corrected merged data to DRAM Assert INT_ if so enabled N A 1 This cycle is not seen on the PowerPC 60x bus Write corrected data back to DRAM if so enabled Assert INT_ if so enabled Double Bit Error Terminate the Pow erPC 60x bus cycle normally Provide miss cor rected raw DRAM data to the PowerPC 60x bus master Assert INT_ if so enabled Assert MCP_ if so enabled Termi...

Page 166: ...logging function independently of the other Once a Falcon has logged an error it does not log any more until the elog control status bit has been cleared by software unless the currently logged error is single bit and a new double bit error is encountered The logging of errors that occur during scrub can be enabled disabled in software Refer to the Error Logger Register in this chapter DRAM Tester...

Page 167: ...leared or set at reset depending on external jumper configuration This allows the board designer to use external jumpers to enable disable Block A B ROM Flash as the source of reset vectors The write enable bit is cleared at reset for both blocks 2 The base address for each block is software programmable At reset Block A s base address is FF000000 and Block B s base address is FF400000 As noted ab...

Page 168: ...to either Falcon while half of the data is connected to the upper Falcon and half of the data is connected to the lower Falcon The following rules are enforced a no writes should be attempted aligned 4 byte writes are allowed but produce undefined results all other sizes are ignored and b all reads are allowed multiple accesses to the ROM Flash device are performed for burst reads More information...

Page 169: ...pper XX000009 000005 Upper XX00000A 000006 Upper XX00000B 000007 Upper XX00000C 000004 Lower XX00000D 000005 Lower XX00000E 000006 Lower XX00000F 000007 Lower XXFFFFF8 7FFFFC Upper XXFFFFF9 7FFFFD Upper XXFFFFFA 7FFFFE Upper XXFFFFFB 7FFFFF Upper XXFFFFFC 7FFFFC Lower XXFFFFFD 7FFFFD Lower XXFFFFFE 7FFFFE Lower XXFFFFFF 7FFFFF Lower PowerPC 60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected ...

Page 170: ...000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X0000008 000001 Upper X0000009 000001 Upper X000000A 000001 Upper X000000B 000001 Upper X000000C 000001 Lower X000000D 000001 Lower X000000E 000001 Lower X000000F 000001 Lower X3FFFFF0 7FFFFE Upper X3FFFFF1 7FFFFE Upper X3FFFFF2 7FFFFE Upper X3FFFFF3 7FFFFE Upper X3FFFF...

Page 171: ...ion After each of the 4 cycles the DRAM row address increments by one When it reaches all 1 s it rolls over and starts over at 0 Each time the row address rolls over the block that is scrubbed toggles between A and B Every second time that the row address rolls over which of the 4 cycles that is a scrub changes from 1st to 2nd from 2nd to 3rd from 3rd to 4th or from 4th to 1st Every eighth time th...

Page 172: ...C and B D Every second time the row address rolls over which of the 4 cycles that is a scrub changes from 1st to 2nd from 2nd to 3rd from 3rd to 4th or from 4th to 1st Every eighth time that the row address rolls over the column address increments by one When the column address reaches all 1 s it rolls over and starts over at 0 Each time the column address rolls over the SC1 SC0 bits in the scrub ...

Page 173: ...h attributes In order to set up these parameters correctly software needs some way of knowing about the devices that are being used with the Falcon pair One way of providing this information is by using the power up status registers in the Falcon pair At power up reset each Falcon latches the level on its RD0 RD63 signal pins into its power up status registers Since the RD signal pins are high imp...

Page 174: ... Falcon hardware in the two chips shifts this same value into the lower Falcon before the cycle completion is acknowledged The shifting is done in holding registers such that the actual update of the control register happens on the same CLOCK cycle in both chips Writes to the upper Falcon can be single byte or 4 byte Writes to the lower Falcon are ignored This duplicating of writes from upper to l...

Page 175: ...read on the upper half of the data bus comes from the upper Falcon while CSR data read on the lower half of the data bus comes from the lower Falcon See Figure 3 4 Figure 3 4 Data Path for Reads from the Falcon Internal CSRs For writes internal register or test SRAM data written on the upper half of the data bus goes to the upper Falcon and is automatically copied by hardware to the lower Falcon I...

Page 176: ...e is no automatic copying of upper data to lower data for the external register set CSR read accesses can have a size of 1 2 4 or 8 bytes with any alignment CSR write accesses must have a size of 1 or 4 bytes and they must be aligned Some Tester registers are limited to 4 byte only accesses Figures 3 6 3 7 3 8 and 3 9 show the memory map for the different kinds of access Upper FALCON 1904 9609 Upp...

Page 177: ...Byte Reads to the CSR 1905 9609 Upper Falcon Upper Falcon Upper Falcon Upper Falcon Lower Falcon Lower Falcon Lower Falcon Lower Falcon Upper Falcon Upper Falcon FEF80000 Lower Falcon FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF ...

Page 178: ...rites to the Internal Register Set and Test SRAM 1906 9609 Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons Both Falcons FEF80000 FEF80001 FEF80002 FEF80003 FEF80004 FEF80005 FEF80006 FEF80007 FEF80008 FEF80009 FEF807FF Writes not allowed Here ...

Page 179: ...e 3 9 Memory Map for 4 Byte Writes to the Internal Register Set and Test SRAM 1907 9609 Upper Falcon Lower Falcon Upper Falcon Lower Falcon FEF80000 Lower Falcon FEF80004 FEF80008 FEF8000C FEF807FC 1908 9609 Both Falcons Both Falcons FEF80000 FEF80004 FEF80008 FEF8000C FEF807FC Writes not allowed Here ...

Page 180: ...or accesses to the lower Falcon add 4 to the address shown Since the only way to write to the lower Falcon s internal register set and test SRAM is to duplicate what is written to the upper Falcon only the addresses shown in the table should be used for writes to them Writes to the external register set are not duplicated from upper to lower so writes to them can be via the upper or lower Falcon ...

Page 181: ...EF80020 CLK FREQUENCY por FEF80028 refdis rwcb derc scien tien sien mien mcken FEF80030 elog escb esen embt esbt ERROR_SYNDROME esblk0 esblk1 scof SBE COUNT FEF80038 ERROR_ADDRESS FEF80040 scb0 scb1 swen rtest0 rtest1 rtest2 FEF80048 ROW ADDRESS COL ADDRESS FEF80050 ROM A BASE rom_a_64 ROM A SIZ rom_a_rv rom a en rom a we FEF80058 ROM B BASE rom_b_64 ROM B SIZ rom_b_rv rom b en rom b we FEF80060 t...

Page 182: ... D2 Upper 8 Bits FEF800D0 TEST D2 Middle 32 Bits FEF800D8 TEST D2 Lower 32 Bits FEF800E0 FEF800E8 TEST D3 Upper 8 Bits FEF800F0 TEST D3 Middle 32 Bits FEF800F8 TEST D3 Lower 32 Bits FEF80100 CTR32 FEF80200 FEF803F8 FEF80400 PR_STAT1 FEF80408 FEF804F8 FEF80500 PR_STAT2 FEF80508 FEF807F8 FEF80800 FEF80BF8 TEST SRAM Table 3 9 Register Summary Continued ...

Page 183: ...in the register set are as follows R The bit is a read only status bit R W The bit is readable and writable R C The bit is cleared by writing a one to itself C The bit is readable Writing a zero to the bit will clear it The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset L The bit is affected by local reset X The bit is not af...

Page 184: ...te that the current value 1507 of VENDID is not correct The correct vendor ID should be 1057 This issue will be treated as just an erratum for now DEVID This read only register contains the value 4802 It is the device number for the Falcon ADDRESS FEF80000 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME VENDID DEVID OPERATIO N READ ONLY READ ONLY RESE...

Page 185: ...a_hole When it is set isa_hole disables any of the DRAM or ROM Flash blocks from responding to PowerPC accesses in the range from 000A0000 to 000BFFFF This has the effect of creating a hole in the DRAM memory map for accesses to ISA When isa_hole is cleared there is no hole created in the memory map adis When adis is clear fast page mode operation is used for back to back pipelined accesses to the...

Page 186: ...ed to match the slowest devices that are used Also if any parts do not support EDO then these bits must set for Page Mode The only case in which it is permissible to set ram spd0 ram spd1 for 50ns EDO is when all parts are 50ns and all support EDO chipu chipu indicates which of the two positions within the Falcon pair is occupied by this chip When chipu is low this chip is connected to the lower h...

Page 187: ...n 0 0 0 0 ram a siz0 ram a siz1 ram a siz2 ram b en 0 0 0 0 ram b siz0 ram b siz1 ram b siz2 ram c en 0 0 0 0 ram c siz0 ram c siz1 ram c siz2 ram d en 0 0 0 0 ram d siz0 ram d siz1 ram d siz2 OPERATIO N R W R R R R R W R W R W R W R R R R R W R W R W R W R R R R R W R W R W R W R R R R R W R W R W RESET 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 P 0 P 0 PL X X X X 0 P 0 ...

Page 188: ... and ram_x_siz should never be programmed such that DRAM responds at the same address as the CSR ROM Flash External Register Set or any other slave on the PowerPC bus 100 128MB 18 8Mx8 s 64Mb 101 256MB 144 16Mx1 s 16Mb 36 16Mx4 s 64Mb 4 16Mx36 s 64Mb 16Mb SIMM DIMM 110 1024MB 144 64Mx1 s 64Mb 111 0MB Reserved ADDRESS FEF80018 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ...

Page 189: ...nd all of its associated counters and state machines to be cleared and maintained that way until refdis is removed cleared If a refresh cycle is in process when refdis is updated by a write to this register the update does not take effect until ADDRESS FEF80020 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME CLK FREQUENCY 0 0 0 0 0 0 0 por OPERATIO N ...

Page 190: ...ting of check bits causes the Falcon to perform a read modify write to DRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write check bits operation To avoid this it is recommended that the derc bit also be set while the rwcb bit is set A possible sequence for performing read write check bits is as follows 1 Disabl...

Page 191: ...rrect data bits Check bits are generated for the data being written derc should be cleared during normal system operation scien When scien is set the rolling over of the SBE COUNT register causes the INT_ signal pin to pulse true tien When tien is set the setting of the tpass or the tfail bit causes the INT_ signal pin to pulse true sien When sien is set the logging of a single bit error causes th...

Page 192: ...or occurs it will be logged elog can only be set by the logging of an error and cleared by power up reset or by the writing of a one to it escb escb indicates the entity that was accessing DRAM at the last logging of a single or double bit error If escb is 1 it indicates that the scrubber was accessing DRAM If escb is 0 it indicates that the PowerPC 60x bus master was accessing DRAM Note that the ...

Page 193: ...s non correctable then these bits are meaningless Refer to the section on ECC Codes for a decoding of the syndromes esblk0 esblk1 Together these two read only bits indicate which block of DRAM was being accessed at the last logging of a scrub error esblk0 esblk1 are 0 0 for Block A 0 1 for Block B 1 0 for Block C and 1 1 for Block D scof scof is set by the SBE COUNT register rolling over from FF t...

Page 194: ... Software Considerations It shows how PowerPC addresses correspond to DRAM row and column addresses Scrub Refresh Register scb0 scb1 These bits increment every time the scrubber completes a scrub of the entire DRAM When these bits reach binary 11 they roll over to binary 00 and continue They are cleared by power up reset ADDRESS FEF80038 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ...

Page 195: ... cycle When it reaches all 1s it rolls back over to all 0s and continues counting ROW ADDRESS is readable and writable for test purposes Note that within each block the most significant bits of ROW ADDRESS are used only when their DRAM devices are large enough to require them Table 3 12 rtest encodings rtest0 rtest1 rtest2 Test Mode selected 000 Normal Counter Operation 001 RA counts at 16x 010 RA...

Page 196: ...ss bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM A BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM A BASE is initialized to FF0 at power up or local bus reset Note that in addition to the programmed address the first 1Mbyte of Block A also appears at FFF00000 FFFFFFFF if the rom_a_rv bit is set a...

Page 197: ...en rom_a_64 is set Block A consists of either two 32 bit devices or one 64 bit read only device such as a 64 bit ROM SIMM With two 32 bit devices one device is connected to the upper Falcon and the other device connected to the lower Falcon With one 64 bit device the device is controlled by either Falcon but connects to data signals from both the upper and lower Falcons rom_a_64 matches the value ...

Page 198: ...ed they are disabled Note that if rom_a_64 is cleared only 1 byte writes are allowed If rom_a_64 is set only 4 byte writes are allowed The Falcon ignores other writes If a valid write is attempted and rom a we is cleared the write does not happen but the cycle is terminated normally See Table 3 15 for details of ROM Flash accesses Table 3 15 Read Write to ROM Flash Table 3 14 rom_a_rv and rom_b_rv...

Page 199: ...lash write 1 byte X 1 X No Response write 4 byte Misaligned X X No Response write 4 byte Aligned 0 X No Response write 4 byte Aligned 1 0 Normal termination but no write to ROM Flash write 4 byte Aligned 1 1 Normal termination write occurs to ROM Flash write 2 3 5 6 7 8 32 byte X X X No Response read X X X X Normal Termination ADDRESS FEF80058 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ...

Page 200: ... When rom_b_64 is cleared Block B consists of two 8 bit ROM Flash devices with one device connected to the upper Falcon and the other device connected to the lower Falcon When rom_b_64 is set Block B consists of either two 32 bit devices or one 64 bit read only device such as a 64 bit ROM SIMM With two 32 bit devices one device is connected to the upper Falcon and the other device connected to the...

Page 201: ...FF as shown in Table 3 14 rom_b_rv is initialized at power up reset to match the inverse of the value on the CKD1 pin rom b en When rom b en is set accesses to Block B ROM Flash in the address range selected by ROM B BASE are enabled When rom b en is cleared they are disabled rom b we When rom b we is set writes to Block B ROM Flash are enabled When rom b we is cleared they are disabled Refer back...

Page 202: ...he CLK_FREQUENCY register has been programmed properly Notice that CTR32 is cleared by power up and local reset It does not exist in Revision 1 of Falcon Note When the system clock is a fractional frequency such as 66 67MHz CTR32 will count at a fractional amount faster or slower than 1MHz depending on the programming of the CLK Frequency Register ADDRESS FEF80100 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 ...

Page 203: ...wide and 64 locations deep Software can read and write to TEST SRAM The DRAM Tester can read TEST SRAM as it fetches instructions It cannot write to it ADDRESS FEF80800 FEF80BF8 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME TEST SRAM 64 Locations OPERATIO N READ ZERO READ ZERO READ WRITE RESET X PL X PL X PL ...

Page 204: ...pecially the System Configuration Register and the Memory Configuration Register Power Up Reset Status Register 2 PR_STAT2 PR_STAT2 power up reset status reflects the value that was on the RD32 RD63 signal pins at power up reset This register is read only ADDRESS FEF80400 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 NAME PR_STAT1 OPERATIO N READ RESET V...

Page 205: ...vices are less than 32 bits wide reads to unused data lanes will yield undefined data Note that writes are restricted to one or 4 byte length only 4 byte writes can be used for any size device data should be placed on the correct portion of the data bus so that valid data is written to the device Data duplication is turned off for the EXTERNAL REGISTER SET so writes can be to either the upper Falc...

Page 206: ...e split so that every other 4 byte segment goes in each device Writing to the Control Registers Software should not change control register bits that affect DRAM operation while DRAM is being accessed Because of pipelining software should always make sure that the two accesses before and after the updating of critical bits are not DRAM accesses A possible scenario for trouble would be to execute c...

Page 207: ...Clear the isa_hole bit 2 Make sure that ram_fref and ram_spd0 ram_spd1 are correct 3 Set CLK_FREQUENCY to match the operating frequency 4 Clear the refdis rwcb bits 5 Set the derc bit 6 Clear the scien tien sien and mien bits 7 Clear the mcken bit 8 Clear the swen and rtest0 rtest1 rtest2 bits 9 Make sure that ROM FLASH banks A and B are not enabled to respond in the range from 00000000 to 4000000...

Page 208: ...ammed If any of the addresses do not match exactly then the amount of memory is less than that for which it is currently programmed Sizing needs to continue for this block by programming its control bits to the next smaller size and repeating steps 4 and 5 6 If no match is found for any size then the block is unpopulated and has a size of 0MB Each size that is checked has a specific set of locatio...

Page 209: ...A14 A15 A16 A17 COL A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 64MB ROW A18 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 128MB ROW A6 A5 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 256MB ROW A4 A5 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 COL A4 A6 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 1024MB ROW A3 A5 A7 A8 A9...

Page 210: ...es 3 19 and 3 20 are the same whether the Falcon is configured as upper or as lower Table 3 19 Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rd0 4A rd16 92 rd32 A4 rd48 29 ckd0 01 rd1 4C rd17 13 rd33 C4 rd49 31 ckd1 02 rd2 2C rd18 0B rd34 C2 rd50 B0 ckd2 04 rd3 2A rd19 8A rd35 A2 rd51 A8 ckd3 08 rd4 E9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C...

Page 211: ... rd51 C8 rd47 E8 09 29 rd48 49 rd24 69 89 rd25 A9 C9 E9 rd4 0A 2A rd3 4A rd0 6A 8A rd19 AA CA EA 0B rd18 2B 4B 6B 8B AB CB EB 0C 2C rd2 4C rd1 6C 8C rd15 AC CC EC 0D rd14 2D 4D 6D 8D AD CD ED 0E rd13 2E 4E 6E 8E AE CE EE 0F 2F 4F rd44 6F 8F AF CF EF 10 ckd4 30 50 70 rd53 90 B0 rd50 D0 rd46 F0 11 31 rd49 51 rd43 71 91 rd39 B1 D1 F1 12 32 rd63 52 rd40 72 92 rd16 B2 D2 F2 13 rd17 33 53 73 93 B3 D3 rd...

Page 212: ...Paths Because of the Falcon pair architecture data paths can be confusing Figure 3 10 attempts to show the placement of data that is written by a PowerPC master to DRAM Table 3 21 shows the same information in tabular format ...

Page 213: ...t 3 Figure 3 10 PowerPC Data to DRAM Data Correspondence 1909 9609 Lower Falcon s DRAM Upper Falcon s DRAM ra12 1 PowerPC Data ra12 0 ra12 1 ra12 0 rd63 dl31 rd32 rd31 rd0 rd63 rd32 rd31 rd0 dl0 dh31 dh0 a 27 28 0 a 27 28 1 a 27 28 2 a 27 28 3 ...

Page 214: ... 07 0 rd 32 39 0 1 dh 08 15 0 rd 40 47 0 1 dh 16 23 0 rd 48 55 0 1 dh 24 31 0 rd 56 63 0 1 dl 00 07 0 rd 32 39 0 1 dl 08 15 0 rd 40 47 0 1 dl 16 23 0 rd 48 55 0 1 dl 24 31 0 rd 56 63 1 0 dh 00 07 1 rd 00 07 1 0 dh 08 15 1 rd 08 15 1 0 dh 16 23 1 rd 16 23 1 0 dh 24 31 1 rd 24 31 1 0 dl 00 07 1 rd 00 07 1 0 dl 08 15 1 rd 08 15 1 0 dl 16 23 1 rd 16 23 1 0 dl 24 31 1 rd 24 31 1 1 dh 00 07 1 rd 32 39 1...

Page 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...

Page 216: ...pliant with the VME64 specification and is tuned to the new generation of high speed processors The Universe is ideally suited for CPU boards acting as both master and slave in the VMEbus system and is particularly fitted for PCI local systems The Universe is manufactured in a CMOS process Product Overview Features Fully compliant 64 bit 33 MHz PCI local bus interface Fully compliant high performa...

Page 217: ...verview This section introduces the general architecture of the Universe This description makes reference to the functional block diagram provided in Figure 4 1 that follows Notice that for each of the interfaces VMEbus and PCI bus there are three functionally distinct modules master module slave module and interrupt module These modules are connected to the different functional channels operating...

Page 218: ...e 4 1 Figure 4 1 Architectural Diagram for the Universe VME Slave VME Master VME Interrupts posted writes FIFO coupled read logic DMA bidirectional FIFO Interrupt Handler Interrupter Register Channel VMEbus Slave Channel posted writes FIFO prefetch read FIFO coupled read PCI Bus Slave Channel Interrupt Channel PCI Master PCI Slave PCI Interrupts VMEbus PCI BUS PCI Bus Interface VMEbus Interface DM...

Page 219: ...t the VMEbus is unavailable to other masters while the PCI bus transaction is executed Read transactions may be prefetched or coupled If enabled by the user a prefetched read is initiated when a VMEbus master requests a block read transaction BLT or MBLT and this mode is enabled When the Universe receives the block read request it begins to fill its Read Data FIFO RDFIFO using burst transactions f...

Page 220: ...ceives data acknowledgment from the Universe with zero wait states Meanwhile the Universe obtains the VMEbus and writes the data to the VMEbus resource independent of the initiating PCI master Refer to Posted Writes in the Universe User Manual for a full description of this operation To allow PCI masters to perform RMW and ADOH cycles the Universe provides a Special Cycle Generator The Special Cyc...

Page 221: ...ted to a single INT pin For VMEbus interrupt outputs the Universe interrupter supplies an 8 bit STATUS ID to a VMEbus interrupt handler during the IACK cycle and optionally generates an internal interrupt to signal that the interrupt vector has been provided Refer to VMEbus Interrupt Generation in the Universe User Manual Interrupts mapped to PCI bus outputs are serviced by the PCI interrupt contr...

Page 222: ...fic rules of DMAFIFO operation refer to FIFO Operation and Bus Ownership in the Universe User Manual it then acquires the destination bus and writes data from its DMAFIFO The DMA controller can be programmed to perform multiple blocks of transfers using entries in a linked list The DMA will work through the transfers in the linked list following pointers at the end of each linked list entry Linked...

Page 223: ...o accesses from the PCI bus and to accesses from the VMEbus side using the VMEbus Register Access Image Refer to Registers in the Universe User Manual For register accesses in CR CSR space be sure to add 508 KBytes 0x7F00 to the address offsets provided in the table Caution Register space marked as Reserved should not be overwritten Unimplemented registers return a value of 0 on reads writes compl...

Page 224: ...nimplemented 01C PCI Unimplemented 020 PCI Unimplemented 024 PCI Unimplemented 028 PCI Reserved 02C PCI Reserved 030 PCI Unimplemented 034 PCI Reserved 038 PCI Reserved 03C PCI Configuration Miscellaneous 1 Register PCI_MISC1 040 0FF PCI Unimplemented 100 PCI Slave Image 0 Control LSI0_CTL 104 PCI Slave Image 0 Base Address Register LSI0_BS 108 PCI Slave Image 0 Bound Address Register LSI0_BD 10C ...

Page 225: ...PCI Slave Image 3 Translation Offset LSI3_TO 14C 16C Universe Reserved 170 Special Cycle Control Register SCYC_CTL 174 Special Cycle PCI bus Address Register SCYC_ADDR 178 Special Cycle Swap Compare Enable Register SCYC_EN 17C Special Cycle Compare Data Register SCYC_CMP 180 Special Cycle Swap Data Register SCYC_SWP 184 PCI Miscellaneous Register LMISC 188 Special PCI Slave Image SLSI 18C PCI Comm...

Page 226: ...rupt Status LINT_STAT 308 PCI Interrupt Map 0 LINT_MAP0 30C PCI Interrupt Map 1 LINT_MAP1 310 VMEbus Interrupt Enable VINT_EN 314 VMEbus Interrupt Status VINT_STAT 318 VMEbus Interrupt Map 0 VINT_MAP0 31C VMEbus Interrupt Map 1 VINT_MAP1 320 Interrupt Status ID Out STATID 324 VIRQ1 STATUS ID V1_STATID 328 VIRQ2 STATUS ID V2_STATID 32C VIRQ3 STATUS ID V3_STATID 330 VIRQ4 STATUS ID V4_STATID 334 VIR...

Page 227: ...ge 1 Base Address Register VSI1_BS F1C VMEbus Slave Image 1 Bound Address Register VSI1_BD F20 VMEbus Slave Image 1 Translation Offset VSI1_TO F24 Universe Reserved F28 VMEbus Slave Image 2 Control VSI2_CTL F2C VMEbus Slave Image 2 Base Address Register VSI2_BS F30 VMEbus Slave Image 2 Bound Address Register VSI2_BD F34 VMEbus Slave Image 2 Translation Offset VSI2_TO F38 Universe Reserved F3C VMEb...

Page 228: ...e Reserved F80 VMEbus CSR Control Register VCSR_CTL F84 VMEbus CSR Translation Offset VCSR_TO F88 VMEbus AM Code Error Log V_AMERR F8C VMEbus Address Error Log VAERR F90 FEC Universe Reserved FF0 VME CR CSR Reserved FF4 VMEbus CSR Bit Clear Register VCSR_CLR FF8 VMEbus CSR Bit Set Register VCSR_SET FFC VMEbus CSR Base Address Register VCSR_BS Table 4 1 Universe Register Map Continued Offset Regist...

Page 229: ...ng the Tundra part number printed on the chip Problem Description The Universe chip is being enabled on the PCI bus after a PCI reset The problem does not occur after a board reset or power up The Universe is causing the bye command to hang the system The Universe Master Enable and Memory Enable in the PCI_CSR Configuration Space register are enabled even before the PCI_BS register has been initia...

Page 230: ... valid PCI Base Address enable register space access and disable the LSI0 slave image by clearing the EN bit of the LSI0_CTL register Method 2 The port 92 reset code can be modified to disable the LSI0 image prior to propagating the reset This will cause the LSI0 image to come up disabled We at MCG understand that both of these methods are awkward because the PCI probe reset code should not contai...

Page 231: ...to this problem Customers should not encounter any problems if they leave Motorola s Open Firmware intact Examples Example 1 MVME2600 Series Board Exhibits Problem Use an MVME2600 series board to exhibit the problem Conditions MVME260x running PPCOF2 0 Ir05 all the Universe code which initializes the Universe has been disabled not the PCI code the driver code modified probe list to d c e f 10 env ...

Page 232: ...7 4 This means that the PCI reset changed the image as follows from supervisor address modifier to user from PCI space base address 1012000 to 0 size of 2000 0000 constant from VME address range 4000 0000 thru 5fff ffff to a new VMEbus range of 0 thru 1fff ffff It is still enabled ...

Page 233: ... e f 10 1 After a P U reset before the init code has written the registers the LSI0 register settings are CTL BS BD TO 800000 0 0 0 2 Run the init code and the LSI0 registers become CTL BS BD TO 80821000 3000000 300a000 4d000000 3 After a bye before the init code has run CTL BS BD TO 80820000 0 0 0 Therefore the PCI reset caused the following changes in the LSI0 image from supervisor to user from ...

Page 234: ...init code ran the LSI0 values are 800000 0 0 0 5 Do NOT run the init code but press push button RESET and the values become 830001 f0000000 f0000000 0 6 Run the vme3 init code and the values are set to accommodate env parameters 80821000 3000000 23000000 3d000000 7 Do a bye The values before the init code runs are 80820000 0 20000000 0 This gets the same results with the MVME360x as with the MVME2...

Page 235: ... seen i e that the LSI0_BS LSI0_BD and LSI0_TO values change as well as the LSI0_CTL fields for program super and vct He checked to see if this is in fact what the Universe is supposed to do The following are his results Register Before RST After RST LSI0_CTL 8082_5FFF 8082_0001 LSI0_BS FFFF_FFFF F000_0000 LSI0_BD FFFF_FFFF F000_0000 LSIO_TO FFFF_FFFF 0000_0000 Explanation All the fields in the LS...

Page 236: ...ation assignments on the MVME2600 2700 series are as follows Upon power up the PIB defaults to a round robin arbitration mode The relative priority of each request grant pair can be customized via the PCI Priority Control Register 1 Refer to the W83C553 Data Book for additional details Table 5 1 PCI Arbitration Assignments PCI BUS REQUEST PCI Master s PIB internal PIB CPU Secondary Ethernet Second...

Page 237: ...t architecture of the MVME2600 2700 series SBC is shown in the following figure Figure 5 1 MVME2600 2700 Series Interrupt Architecture 11559 00 9609 PIB 8529 Pair Processor INT_ MCP_ Processor INT_ MCP_ RavenMPIC INT SERR_ PERR_ PCI Interrupts ISA Interrupts ...

Page 238: ...llowing table shows the interrupt assignments for the RavenMPIC on the MVME2600 2700 series Table 5 2 RavenMPIC Interrupt Assignments MPIC IRQ Edge Level Polarity Interrupt Source Notes IRQ0 Level High PIB 8259 1 IRQ1 Edge Low Falcon ECC Error 2 IRQ2 Level Low PCI Ethernet 4 IRQ3 Level Low PCI SCSI 4 IRQ4 Level Low PCI Graphics 4 IRQ5 Level Low PCI VME INT 0 Universe LINT0 3 4 IRQ6 Level Low PCI V...

Page 239: ... IRQ8_ and IRQ13 each of the interrupt lines can be configured for either edge sensitive mode or level sensitive mode by programming the appropriate ELCR registers in the PIB There is also support for four PCI interrupts PIRQ3_ PIRQ0_ The PIB has four PIRQ Route Control Registers to allow each of the PCI interrupt lines to be routed to any of eleven ISA interrupt lines IRQ0 IRQ1 IRQ2 IRQ8_ and IRQ...

Page 240: ... 1897 9609 IRQx PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ Route Control Register PIRQ3_ IRQx PIRQ2_ IRQx PIRQ1_ IRQx PIRQ0_ Controller 2 INT2 IRQ8 IRQ9 IRQ11 IRQ10 IRQ12 IRQ13 IRQ14 IRQ15 0 1 2 3 4 5 6 7 Controller 1 INT1 Timer1 Counter0 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 0 1 2 3 4 5 6 7 INTR ...

Page 241: ...w ABORT Switch Interrupt 4 IRQ9 Level High Z8536 CIO 3 4 Z85230 ESCC 5 IRQ10 PIRQ0_ Level Low PCI Ethernet Interrupt 3 5 6 6 IRQ11 PIRQ1_ Level Low Universe Interrupt LINT0 3 5 6 7 IRQ12 Edge High Mouse 8 IRQ13 Edge High Not Used 6 9 IRQ14 PIRQ2_ Level Low PCI SCSI Interrupt 3 5 6 10 IRQ15 PIRQ3_ Level Low PCI Graphics Interrupt 3 5 6 PMC Interrupt 3 5 6 11 IRQ3 INT1 Edge High COM2 Async Serial Po...

Page 242: ...e The Z8536 CIO has higher priority than the Z85230 ESCC This IRQ MUST be programmed for level sensitive mode 5 These PCI interrupts are routed to the ISA interrupts by programming the PRIQ Route Control Registers in the PIB The PCI to ISA interrupt assignments in this table are suggested Each ISA IRQ to which a PCI interrupt is routed to MUST be programmed for level sensitive mode Use this routin...

Page 243: ...SET Switch 3 Watchdog Timer Reset via the MK48T59 Timekeeper device 4 Port 92 Register via the PIB 5 I O Reset via the Clock Divisor Register in the PIB 6 VMEbus SYSRESET signal 7 Local software reset via the Universe ASIC MISC_CTL Register 8 VME System Reset Via the Universe ASIC MISC_CTL Register 9 VME CSR reset via the Universe ASIC VCSR_SET Register ...

Page 244: ...there can be problems with the Universe chip after a PCI reset Refer to Chapter 4 for the details Table 5 4 Reset Sources and Devices Affected Device Affected Processor s Raven ASIC Falcon Chipset PCI Devices ISA Devices VMEbus System Controller Power On Reset Switch Watchdog MK48T59 VME System Reset SYSRESET Signal VME System Software Reset MISC_CTL Register VME Local Software Reset MISC_CTL Regi...

Page 245: ...he Processor s if so enabled MPC Bus Time Out Store Discard write data and terminate bus cycle normally Load Present undefined data to the MPC master Generate interrupt via RavenMPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 1 s and terminate bus cycle normally Generate ...

Page 246: ... NT and big endian software e g AIX Because the PowerPC processor is inherently big endian PCI is inherently little endian and the VMEbus is big endian things do get rather confusing The following figures shows how the MVME2600 2700 series handle the endian issue in big endian and little endian modes ...

Page 247: ...ing Details 5 Figure 5 3 Big Endian Mode Big Endian PROGRAM 1898 9609 Raven Universe Falcons DRAM Big Endian Little Endian Big Endian Little Endian PCI Local Bus VMEbus N way Byte Swap N way Byte Swap 60X System Bus ...

Page 248: ...le Endian Mode EA Modification XOR 1899 9609 Raven Universe Falcons DRAM Big Endian Little Endian Big Endian Little Endian PCI Local Bus VMEbus N way Byte Swap EA Modification 60X System Bus Big Endian Little Endian Little Endian PROGRAM ...

Page 249: ...ndian mode with the processor and the memory sub system In little endian mode it reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done PCI Domain The PCI bus is inherently little endian and all devices connected directly to PCI will operate in little endian mode regardless of the mode of operation i...

Page 250: ...graphics on the MVME2600 2700 series boards Universe s Involvement Since PCI is little endian and the VMEbus is big endian the Universe performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processor s domain VMEbus Domain The VMEbus is inherently big endian and all devices connected directly to...

Page 251: ...e must direct the Falcon chipset to map the FFF00000 FFFFFFFF address range to Bank B following a hard reset Bank A then can be programmed by code from Bank B Software can determine the mapping of the FFF00000 FFFFFFFF address range by examining the rom_b_rv bit in the Falcon s Rom B Base Size Register Table 5 6 ROM FLASH Bank Default rom_b_rv Default Mapping for FFF00000 FFFFFFFF 0 ROM FLASH Bank...

Page 252: ...A A 1 ARelated Documentation Overview This appendix provides information on how to purchase support contracts from MCG and on obtaining MCG and third party documentation ...

Page 253: ...l assistance that is crucial for mission critical applications around the world 24 X 7 access to the latest technical information on MCG products including known problems and a solutions database Customized training available at the MCG campus or at any of your sites across the world Customized documentation and 24 X 7 Internet access to product documentation Services Central a one stop informatio...

Page 254: ...ough not shown in the above list each Motorola Computer Group manual publication number is suffixed with characters that represent the revision level of the document such as xx2 the second revision of a manual a Table A 1 Motorola Computer Group Documents Document Title Publication Number MVME2600 Series Single Board Computer Installation and Use V2600A IH MVME2700 Series Single Board Computer Ins...

Page 255: ...Related Documentation A 4 A supplement bears the same number as the manual but has a suffix such as xx2A1 the first supplement to the second revision of the manual ...

Page 256: ...e ordered as part number LK PCIKIT2 Table A 2 Manufacturers Documents Document Title and Source Publication Number PowerPC 603TM RISC Microprocessor Technical Summary Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 MPC603 D PowerPC 603TM RISC Microprocessor User s Manual Motorola Literature and Printing Distrib...

Page 257: ...2 FAX 1 800 POWERfax FAX 1 800 769 3732 MPC604UM AD MPR604UMU 01 PowerPCTM Microprocessor Family The Programming Environments Motorola Literature and Printing Distribution Services P O Box 20924 Phoenix Arizona 85036 0924 Telephone 602 994 6561 FAX 602 994 6430 OR IBM Microelectronics Mail Stop A25 862 1 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC ...

Page 258: ...p Information Line Telephone United States and Canada 1 800 332 2717 TTY United States only 1 800 332 2515 Telephone outside North America 1 508 568 6868 EC QN7NC TE PC87308VUL Super I OTM Enhanced Sidewinder Lite Floppy Disk Controller Keyboard Controller Real Time Clock Dual UARTs IEEE 1284 Parallel Port and IDE Interface National Semiconductor Corporation Customer Support Center or nearest Sale...

Page 259: ...X 408 370 8056 UM95SCC0100 Z8536 CIO Counter Timer and Parallel I O Unit Product Specification and User s Manual in Z8000 Family of Products Data Book Zilog Inc 210 East Hacienda Ave mail stop C1 0 Campbell California 95008 6600 Telephone 408 370 8016 FAX 408 370 8056 DC 8319 00 W83C553 Enhanced System I O Controller with PCI Arbiter PIB was SL82C565 Winbond Electronics Corporation Winbond Systems...

Page 260: ...ch Road Kanata ON K2K 2M5 Canada Telephone 1 800 267 7231 Telephone 613 592 1320 OR 695 High Glen Drive San Jose CA 95133 USA Telephone 408 258 3600 FAX 408 258 3659 Universe Part Number 9000000 MD303 01 Table A 2 Manufacturers Documents Continued Document Title and Source Publication Number ...

Page 261: ...Box 19539 Irvine California 92713 9539 Telephone 1 800 854 7179 or 714 979 8135 X3 131 1990 VME64 Specification VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale Arizona 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 NOTE An earlier version of this specification is available as Versatile Backplane Bus VMEbus Institute of Electrical and Electronics Engineers ...

Page 262: ... 21633 Telephone 1 800 678 4333 P1386 1 Draft 2 0 Bidirectional Parallel Port Interface Specification Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 IEEE Standard 1284 Peripheral Component Interconnect PCI Local Bus Specification Revision 2 1 PCI Special Interest Group 2575 NE Kathry...

Page 263: ...800 PowerPC OR Morgan Kaufmann Publishers Inc 340 Pine Street Sixth Floor San Francisco CA 94104 3205 USA Telephone 415 392 2665 FAX 415 982 2665 TB338 D MPRPPCHRP 01 ISBN 1 55860 394 8 PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin TX 78758 3493 Document ...

Page 264: ...d twisted pair UTP of wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet 100Base TX An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet ACIA Asynchronous Communications Interface Adapter ...

Page 265: ...rectangle of data from one area of display memory to another The data specifically need not have any particular alignment BLT BLock Transfer board The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or car...

Page 266: ... without the luminance Y signal The Green signals G Y can be extracted by these two signals Common Hardware Reference Platform CHRP A specification published by the Apple IBM and Motorola which defines the devices interfaces and data formats that make up a CHRP compliant system using a PowerPC processor Composite Video Signal CVS CVBS Signal that carries video picture information for color brightn...

Page 267: ...ransferred between peripherals in 32 bit chunks instead of 16 bit or 8 bit that most systems use With the transfer of larger bits of information the machine is able to perform much faster than the standard ISA bus system EPP Enhanced Parallel Port EPROM Erasable Programmable Read Only Memory A memory storage device that can be written once per erasure cycle and read many times ESCC Enhanced Serial...

Page 268: ...t for graphics drawing algorithms by performing logical functions on data written to display memory HAL Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality hardware A computing system is normally spoken of as having two major components hardware and software Hardware is the term used to describe any of ...

Page 269: ...computers until the introduction of VESA and PCI Used in the reference platform specification IBM ISASIO ISA Super Input Output device ISDN Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks LAN Local Area Network LED Light Emitting Diode LFM Linear Feet per Minute little endian A byte ordering method in memory where...

Page 270: ...ays yielding substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not representative of how long a device or any individual device is likely to last nor is it a warranty but rather of the relative reliability of a family of products multisession The ability to record additional infor...

Page 271: ...Personal Computer Memory Card International Association bus A standard external interconnect bus which allows peripherals adhering to the standard to be plugged in and used without further system modification PCR PCI Configuration Register PHB PCI Host Bridge PDS Processor Direct Slot physical address A binary address that refers to the actual location of information stored in secondary storage PI...

Page 272: ...ates a memory management unit with a 64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under license from IBM PowerPC 604 The third implementation of the PowerPC family of microprocessors PowerPC 604 is used by Motorola Inc under license from IBM PowerPC Reference Platform P...

Page 273: ...quency Interference RGB The three separate color signals Red Green and Blue Used with color displays an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist RISC See Reduced Instruction Set Computer RISC ROM Read Only Memory RTC Real Time Clock SBC Single Board Compute...

Page 274: ...e and software Software is the term used to describe any single program or group of programs languages operating procedures and documentation of a computer system Software is the real interface between the user and the computer SRAM Static Random Access Memory SSBLT Source Synchronous BLock Transfer standard s A set of detailed technical guidelines used as a means of establishing uniformity in an ...

Page 275: ...day It provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels virtual address A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address VL bus See VESA Local bus VL bus VMEchip2 MCG second generation VMEbu...

Page 276: ...veloped by the Microsoft Corporation XGA EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Y Signal Luminance This determines the brightness of each spot pixel on a CRT screen either color or B W systems but not the color ...

Page 277: ...Glossary GL 14 G L O S S A R Y ...

Page 278: ...ittle endian data swap 2 17 big endian 1 3 big endian mode 5 12 binary number 1 2 Bit Descriptions 3 32 block diagram 2 4 block diagram description 2 57 board documentation A 3 Bus Interface 60x 3 12 byte ordering 1 3 byte definition 1 3 C Cache Coherency 3 12 CHRP compliant memory map 2 7 CHRP memory map example 1 10 CLK FREQUENCY 3 38 CLK Frequency Register 3 38 Clock Frequency 3 38 Column Addre...

Page 279: ...Correction Codes 3 59 Error Detection 3 13 error handling 2 18 Error Logger Register 3 41 Error Logging 3 15 error notification and handling 5 10 Error Reporting 3 14 ERROR_ADDRESS 3 43 ERROR_SYNDROME 3 42 esbt 3 42 escb 3 41 esen 3 41 exceptions 5 8 external interrupt service 2 79 External Register Set 3 22 3 54 External Register Set Reads and Writes 3 24 External Source Destination Registers 2 7...

Page 280: ... Base Address Reg ister 1 43 Location Monitor Upper Base Address Reg ister 1 42 M manual terminology 1 2 manufacturers documents A 5 mcken 3 40 Memory Base Register 2 46 Memory Configuration Register MEMCR 1 30 memory maps 1 8 mien 3 40 MK48T59 access registers 1 35 module configuration and status registers 1 35 Motorola Computer Group documents A 1 MPC arbiter 2 5 MPC Arbiter Control Register 2 2...

Page 281: ...PIB PCI ISA interrupt assignments 5 6 Power Up Reset Status Bit 3 38 Power Up Reset Status Register 3 53 PR_STATL 3 53 PR_STATU 3 53 PREP memory map example 1 12 Prescaler Adjust Register 2 29 processor CHRP memory map 1 10 Processor Init Register 2 67 processor memory maps 1 8 processor PREP memory map 1 12 processor memory domain 5 14 processor s current task priority 2 53 product overview featu...

Page 282: ... ROM Flash A Size Encoding 3 46 ROM Flash A Width Control Bit 3 46 ROM Flash B Base Address Control Bits 3 48 ROM Flash B Base Size Register 3 48 ROM Flash B Width Control Bit 3 49 ROM FLASH bank default 5 16 ROM Flash initialization 5 16 ROM Flash Speed 3 11 rom_a_64 3 46 ROM_A_BASE 3 45 rom_a_en 3 47 rom_a_rv 3 47 rom_a_siz 3 46 rom_a_we 3 47 rom_b_64 3 49 ROM_B_BASE 3 48 rom_b_en 3 50 rom_b_rv ...

Page 283: ...emory map 1 16 Universe PCI register values for PREP mem ory map 1 20 Universe PCI register values for VMEbus slave map example 1 25 Universe register map 4 8 Universe s involvement 5 15 Upper Lower Chip Status Bit 3 35 V Vendor ID Device ID Registers 2 43 Vendor ID Device ID Registers 2 24 Vendor Identification Register 2 67 Vendor Device Register 3 33 VME Geographical Address Register VGAR 1 44 ...

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