3
3-1
3
Falcon ECC Memory Controller
Chip Set
Introduction
The Falcon DRAM controller ASIC is designed for the MVME2600/2700
family of boards. It is used in sets of two to provide the interface between
the PowerPC 60x bus and a 144-bit ECC-DRAM memory system. It also
provides an interface to ROM/Flash.
Overview
This chapter provides a functional description and programming model for
the Falcon. Most of the information for using the device in a system,
programming it in a system, and testing it is contained here.
Bit Ordering Convention
All Falcon bused signals are named using big-endian bit ordering (bit 0 is
the most significant bit).
Features
❏
DRAM Interface
– Double-bit error detect/Single-bit error correct on 72-bit basis.
– Up to four blocks.
– Programmable base address for each block.
– Two-way interleave factor.
– Built-in Refresh/Scrub.
– Programmable sequencer for fast DRAM tests.
❏
Error Notification for DRAM
– Software programmable Interrupt on Single/Double-Bit Error.
– Error address and Syndrome Log Registers for Error Logging.
Summary of Contents for MVME2700 Series
Page 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Page 13: ...xiv ...
Page 15: ...xvi ...
Page 67: ...1 50 Board Description and Memory Maps 1 ...
Page 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Page 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Page 277: ...Glossary GL 14 G L O S S A R Y ...