Programming Model
3-35
3
ram fref
Some DRAMs require that they be refreshed at the rate of
7.8
µ
s per row rather than the standard 15.6
µ
s per row. If
any of the DRAM devices require the higher rate, then the
ram fref bit should be left set, otherwise, it can be cleared.
ram spd0,ram spd1
Together ram spd0,ram spd1 control
DRAM timing used by the Falcon pair. They are encoded
as shown:
EDO refers to DRAMs that use an output latch on data.
Sometimes these parts are referred to as Hyper-Page
Mode DRAMs.
To ensure reliable operation, the system should always be
configured so that these two bits are encoded to match the
slowest devices that are used. Also, if any parts do not
support EDO, then these bits must set for Page Mode. The
only case in which it is permissible to set ram spd0,ram
spd1 for “50ns, EDO” is when all parts are 50ns and all
support EDO.
chipu
chipu indicates which of the two positions within the
Falcon pair is occupied by this chip. When chipu is low,
this chip is connected to the lower half of the PowerPC
60x data bus and it does not drive TA_ or AACK_. When
chipu is high, this chip is connected to the upper half of
the PowerPC 60x data bus, and it drives TA_ and
AACK_. chipu reflects the level that was on the ERCS_
pin during power-up reset.
Table 3-10. ram spd1
,ram spd0 and DRAM Type
ram spd0
,
ram spd1
DRAM Speed
DRAM Type
%00
70ns
Page Mode
%01
60ns
Page Mode
%10
-
Reserved
%11
50ns
EDO
Summary of Contents for MVME2700 Series
Page 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Page 13: ...xiv ...
Page 15: ...xvi ...
Page 67: ...1 50 Board Description and Memory Maps 1 ...
Page 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Page 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Page 277: ...Glossary GL 14 G L O S S A R Y ...