Programming Model
3-37
3
DRAM Base Register
RAM A/B/C/D BASE These control bits define the base address for
their block’s DRAM. RAM A/B/C/D BASE bits 0-7/8-
15/16-23/24-31 correspond to PowerPC 60x address bits
0 - 7. For larger DRAM sizes, the lower significant bits of
A/B/C/D BASE are ignored. This means that the block’s
base address will always appear at an even multiple of its
size. Note that bit 0 is MSB.
Also note that the combination of RAM_X_BASE and
ram_x_siz should never be programmed such that
DRAM responds at the same address as the CSR,
ROM/Flash, External Register Set, or any other slave on
the PowerPC bus.
%100
128MB
18
-
8Mx8’s
64Mb
%101
256MB
144
-
16Mx1’s
16Mb
36
-
16Mx4’s
64Mb
4
-
16Mx36’s
64Mb/16Mb
SIMM/DIMM
%110
1024MB
144
-
64Mx1’s
64Mb
%111
0MB
-
-
-
-
Reserved
ADDRESS
$FEF80018
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NAME
RAM A BASE
RAM B BASE
RAM C BASE
RAM D BASE
OPERATIO
N
READ/WRITE
READ/WRITE
READ/WRITE
READ/WRITE
RESET
0 PL
0 PL
0 PL
0 PL
Table 3-11. Block_A/B/C/D Configurations
ram a/b/c/d
siz0-2
Block
SIZE
Devices Used
Technology
Comments
Summary of Contents for MVME2700 Series
Page 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Page 13: ...xiv ...
Page 15: ...xvi ...
Page 67: ...1 50 Board Description and Memory Maps 1 ...
Page 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Page 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Page 277: ...Glossary GL 14 G L O S S A R Y ...