Functional Description
2-13
2
PCI Master
The PCI master, in conjunction with the capabilities of the MPC slave, will
attempt to move data in either single beat or burst transactions. All single
beat transactions will be subdivided into one or two 32-bit transfers,
depending on the alignment and size of the transaction. The PCI master
will attempt to transfer all burst transactions in 64-bit mode. If at any time
during the transaction the PCI target indicates it can not support 64-bit
mode, the PCI master will continue to transfer the remaining data in 32-bit
mode.
The PCI Command Codes generated by the PCI master depend on the
MPC transfer type, TBST*, and the MEM field in the MSATTx registers.
Table 2-3. PCI Command Codes
Generating PCI Memory and I/O Cycles
Each programmable slave may be configured to generate PCI I/O or
memory accesses through the MEM and IOM fields in its Attribute register
as shown below.
MPC Transfer Type
TBST*
MEM
PCI Command
Write w/ Flush
Write w/ Flush Atomic
Write w/ Kill
Graphics Write
x
1
0111
(Memory Write)
x
0
0011
(I/O Write)
Read
Read w/ ITM
Read w/ ITM Atomic
Graphics Read
0
1
1110
(Memory Read Line)
1
1
0110
(Memory Read)
x
0
0010
(I/O Read)
Summary of Contents for MVME2700 Series
Page 1: ...MVME2600 2700 Series Single Board Computer Programmer s Reference Guide V2600A PG2 ...
Page 13: ...xiv ...
Page 15: ...xvi ...
Page 67: ...1 50 Board Description and Memory Maps 1 ...
Page 151: ...2 84 Raven PCI Host Bridge Multi Processor Interrupt Controller Chip 2 ...
Page 215: ...3 64 Falcon ECC Memory Controller Chip Set 3 ...
Page 277: ...Glossary GL 14 G L O S S A R Y ...