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Motorola ColdFire MCF5281, User Manual

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Motorola ColdFire MCF5281 User Manual Download Page 498

23-24

MCF5282 User’s Manual

MOTOROLA

 

Operation  

register and loaded into the top empty receiver holding register position of the FIFO. Thus,
data flowing from the receiver to the CPU is quadruple-buffered.

In addition to the data byte, three status bits, parity error (PE), framing error (FE), and
received break

 

(RB), are appended to each data character in the FIFO; OE (overrun error)

is not appended. By programming the ERR bit in the channel’s mode register (UMR1

n

),

status is provided in character or block modes.

USR

n

[RxRDY] is set when at least one character is available to be read by the CPU. A read

of the receive buffer produces an output of data from the top of the FIFO stack. After the
read cycle, the data at the top of the FIFO stack and its associated status bits are popped and
the receiver shift register can add new data at the bottom of the stack. The FIFO-full status
bit (FFULL) is set if all three stack positions are filled with data. Either the RxRDY or
FFULL bit can be selected to cause an interrupt or DMA request.

The two error modes are selected by UMR1

n

[ERR] as follows:

• In character mode (UMR1

n

[ERR] = 0, status is given in the USR

n

 for the character 

at the top of the FIFO. 

• In block mode, the USR

n

 shows a logical OR of all characters reaching the top of 

the FIFO stack since the last 

RESET

 

ERROR

 

STATUS

 command. Status is updated as 

characters reach the top of the FIFO stack. Block mode offers a data-reception speed 
advantage where the software overhead of error-checking each character cannot be 
tolerated. However, errors are not detected until the check is performed at the end of 
an entire message—the faulting character is not identified.

In either mode, reading the USR

n

 does not affect the FIFO. The FIFO is popped only when

the receive buffer is read. The USR

n

 should be read before reading the receive buffer. If all

three receiver holding registers are full, a new character is held in the receiver shift register
until space is available. However, if a second new character is received, the contents of the
the character in the receiver shift register is lost, the FIFOs are unaffected, and USR

n

[OE]

is set when the receiver detects the start bit of the new overrunning character.

To support flow control, the receiver can be programmed to automatically negate and assert
URTS

n

, in which case the receiver automatically negates URTS

n

 when a valid start bit is

detected and the FIFO stack is full. The receiver asserts URTS

n

 when a FIFO position

becomes available; therefore, overrun errors can be prevented by connecting URTS

n

 to the

UCTS

n

 input of the transmitting device.

NOTE

The receiver can still read characters in the FIFO stack if the
receiver is disabled. If the receiver is reset, the FIFO stack,
URTS

n

 control, all receiver status bits, and interrupts, and

DMA requests are reset. No more characters are received until
the receiver is reenabled.

Summary of Contents for ColdFire MCF5281

Page 1: ...MCF5282UM D Rev 2 1 2004 MCF5282 ColdFire Microcontroller User s Manual Devices Supported MCF5281 ...

Page 2: ...rpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All op...

Page 3: ...tchdog Timer Module Programmable Interrupt Timer PIT Modules General Purpose Timer GPT Modules FlexCAN Module General Purpose I O Module I2C Module 3 4 5 7 8 9 10 11 12 13 15 16 17 18 19 24 6 20 25 26 21 23 22 DMA Timers Queued Serial Peripheral Interface Module QSPI UART Modules 1 2 27 28 29 30 31 32 33 A Chip Configuration Module CCM Queued Analog to Digital Converter QADC Reset Controller Modul...

Page 4: ...et Controller FEC Watchdog Timer Module Programmable Interrupt Timer PIT Modules General Purpose Timer GPT Modules FlexCAN Module General Purpose I O Module I2C Module 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 24 6 20 25 26 21 23 22 DMA Timers Queued Serial Peripheral Interface Module QSPI UART Modules 1 2 27 28 29 30 31 32 33 A Chip Configuration Module CCM Queued Analog to Digital Converter QADC...

Page 5: ...A Timers DTIM0 DTIM3 1 13 1 1 12 General Purpose Timers GPTA GPTB 1 13 1 1 13 Periodic Interrupt Timers PIT0 PIT3 1 13 1 1 14 Software Watchdog Timer 1 14 1 1 15 Phase Locked Loop PLL 1 14 1 1 16 DMA Controller 1 14 1 1 17 Reset 1 14 1 2 MCF5282 Specific Features 1 15 1 2 1 Fast Ethernet Controller FEC 1 15 1 2 2 FlexCAN 1 15 1 2 3 I2 C Bus 1 15 1 2 4 Queued Serial Peripheral Interface QSPI 1 15 1...

Page 6: ...tion 2 16 2 7 13 Fault on Fault Halt 2 16 2 7 14 Reset Exception 2 16 2 8 Instruction Execution Timing 2 21 2 8 1 Timing Assumptions 2 21 2 8 2 MOVE Instruction Execution Times 2 22 2 9 Standard One Operand Instruction Execution Times 2 24 2 10 Standard Two Operand Instruction Execution Times 2 24 2 11 Miscellaneous Instruction Execution Times 2 26 2 12 EMAC Instruction Execution Times 2 27 2 13 B...

Page 7: ...ters 4 7 Chapter 5 Static RAM SRAM 5 1 SRAM Features 5 1 5 2 SRAM Operation 5 1 5 3 SRAM Programming Model 5 1 5 3 1 SRAM Base Address Register RAMBAR 5 2 5 3 2 SRAM Initialization 5 3 5 3 3 SRAM Initialization Code 5 4 5 3 4 Power Management 5 4 Chapter 6 ColdFire Flash Module CFM 6 1 Features 6 1 6 2 Block Diagram 6 2 6 3 Memory Map 6 4 6 3 1 CFM Configuration Field 6 5 6 3 2 Flash Base Address ...

Page 8: ...f Peripheral State During Low Power Modes 7 16 Chapter 8 System Control Module SCM 8 1 Overview 8 1 8 2 Features 8 1 8 3 Memory Map and Register Definition 8 2 8 4 Register Descriptions 8 3 8 4 1 Internal Peripheral System Base Address Register IPSBAR 8 3 8 4 2 Memory Base Address Register RAMBAR 8 4 8 4 3 Core Reset Status Register CRSR 8 6 8 4 4 Core Watchdog Control Register CWCR 8 6 8 4 5 Core...

Page 9: ...et 9 11 9 7 3 System Clock Generation 9 11 9 7 4 PLL Operation 9 12 Chapter 10 Interrupt Controller Modules 10 1 68K ColdFire Interrupt Architecture Overview 10 1 10 1 1 Interrupt Controller Theory of Operation 10 3 10 2 Memory Map 10 5 10 3 Register Descriptions 10 6 10 3 1 Interrupt Pending Registers IPRHn IPRLn 10 6 10 3 2 Interrupt Mask Register IMRHn IMRLn 10 8 10 3 3 Interrupt Force Register...

Page 10: ...3 1 General Chip Select Operation 12 3 12 4 Chip Select Registers 12 5 12 4 1 Chip Select Module Registers 12 6 Chapter 13 External Interface Module EIM 13 1 Features 13 1 13 2 Bus and Control Signals 13 1 13 3 Bus Characteristics 13 2 13 4 Data Transfer Operation 13 2 13 4 1 Bus Cycle Execution 13 3 13 4 2 Data Transfer Cycle States 13 5 13 4 3 Read Cycle 13 6 13 4 4 Write Cycle 13 8 13 4 5 Fast ...

Page 11: ... Converter Signals 14 29 14 2 14 Debug Support Signals 14 30 14 2 15 Test Signals 14 32 14 2 16 Power and Reference Signals 14 33 Chapter 15 Synchronous DRAM Controller Module 15 1 Overview 15 1 15 1 1 Definitions 15 1 15 1 2 Block Diagram and Major Components 15 2 15 2 SDRAM Controller Operation 15 3 15 2 1 DRAM Controller Signals 15 4 15 2 2 Memory Map for SDRAMC Registers 15 4 15 2 3 General Sy...

Page 12: ...roller FEC 17 1 Overview 17 1 17 1 1 Features 17 1 17 2 Modes of Operation 17 2 17 2 1 Full and Half Duplex Operation 17 2 17 2 2 Interface Options 17 2 17 2 3 Address Recognition Options 17 3 17 2 4 Internal Loopback 17 3 17 3 FEC Top Level Functional Diagram 17 4 17 4 Functional Description 17 5 17 4 1 Initialization Sequence 17 6 17 4 2 User Initialization Prior to Asserting ECR ETHER_EN 17 6 1...

Page 13: ...n 18 1 18 2 Low Power Mode Operation 18 1 18 3 Block Diagram 18 2 18 4 Signals 18 2 18 5 Memory Map and Registers 18 2 18 5 1 Memory Map 18 2 18 5 2 Registers 18 3 Chapter 19 Programmable Interrupt Timer Modules PIT0 PIT3 19 1 Overview 19 1 19 2 Block Diagram 19 1 19 3 Low Power Mode Operation 19 2 19 4 Signals 19 2 19 5 Memory Map and Registers 19 3 19 5 1 Memory Map 19 3 19 5 2 Registers 19 3 19...

Page 14: ...gister GPTIE 20 10 20 5 11 GPT System Control Register 2 GPTSCR2 20 11 20 5 12 GPT Flag Register 1 GPTFLG1 20 12 20 5 13 GPT Flag Register 2 GPTFLG2 20 12 20 5 14 GPT Channel Registers GPTCn 20 13 20 5 15 Pulse Accumulator Control Register GPTPACTL 20 13 20 5 16 Pulse Accumulator Flag Register GPTPAFLG 20 14 20 5 17 Pulse Accumulator Counter Register GPTPACNT 20 15 20 5 18 GPT Port Data Register G...

Page 15: ...ters DTCRn 21 7 21 2 11 DMA Timer Counters DTCNn 21 8 21 3 Using the DMA Timer Modules 21 8 21 3 1 Code Example 21 9 21 3 2 Calculating Time Out Values 21 10 Chapter 22 Queued Serial Peripheral Interface QSPI Module 22 1 Overview 22 1 22 2 Features 22 1 22 3 Module Description 22 1 22 3 1 Interface and Signals 22 2 22 3 2 Internal Bus Interface 22 3 22 4 Operation 22 3 22 4 1 QSPI RAM 22 4 22 4 2 ...

Page 16: ...t Change Registers UIPCRn 23 12 23 3 9 UART Auxiliary Control Register UACRn 23 13 23 3 10 UART Interrupt Status Mask Registers UISRn UIMRn 23 13 23 3 11 UART Baud Rate Generator Registers UBG1n UBG2n 23 14 23 3 12 UART Input Port Register UIPn 23 15 23 3 13 UART Output Port Command Registers UOP1n UOP0n 23 15 23 4 UART Module Signal Definitions 23 17 23 5 Operation 23 18 23 5 1 Transmitter Receiv...

Page 17: ...7 Arbitration Lost 24 14 Chapter 25 FlexCAN 25 1 Features 25 1 25 1 1 FlexCAN Memory Map 25 3 25 1 2 External Signals 25 3 25 2 The CAN System 25 4 25 3 Message Buffers 25 4 25 3 1 Message Buffer Structure 25 4 25 3 2 Message Buffer Memory Map 25 7 25 4 Functional Overview 25 8 25 4 1 Transmit Process 25 9 25 4 2 Receive Process 25 9 25 4 3 Message Buffer Handling 25 10 25 4 4 Remote Frames 25 12 ...

Page 18: ...26 1 26 1 1 Overview 26 3 26 1 2 Features 26 3 26 1 3 Modes of Operation 26 3 26 2 External Signal Description 26 4 26 3 Memory Map Register Definition 26 6 26 3 1 Register Overview 26 6 26 3 2 Register Descriptions 26 8 26 4 Functional Description 26 25 26 4 1 Overview 26 25 26 4 2 Port Digital I O Timing 26 25 26 5 Initialization Application Information 26 26 Chapter 27 Queued Analog to Digital ...

Page 19: ...7 7 3 Analog Subsystem 27 34 27 8 Digital Control Subsystem 27 37 27 8 1 Queue Priority Timing Examples 27 38 27 8 2 Boundary Conditions 27 49 27 8 3 Scan Modes 27 50 27 8 4 Disabled Mode 27 50 27 8 5 Reserved Mode 27 50 27 8 6 Single Scan Modes 27 50 27 8 7 Continuous Scan Modes 27 54 27 8 8 QADC Clock QCLK Generation 27 57 27 8 9 Periodic Interval Timer 27 58 27 8 10 Conversion Command Word Tabl...

Page 20: ... 29 4 29 4 Programming Model 29 5 29 4 1 Revision A Shared Debug Resources 29 7 29 4 2 Address Attribute Trigger Register AATR 29 8 29 4 3 Address Breakpoint Registers ABLR ABHR 29 9 29 4 4 Configuration Status Register CSR 29 10 29 4 5 Data Breakpoint Mask Registers DBR DBMR 29 12 29 4 6 Program Counter Breakpoint Mask Registers PBR PBMR 29 13 29 4 7 Trigger Definition Register TDR 29 14 29 5 Bac...

Page 21: ...30 6 1 Reset Configuration 30 8 30 6 2 Chip Mode Selection 30 10 30 6 3 Boot Device Selection 30 11 30 6 4 Output Pad Strength Configuration 30 11 30 6 5 Clock Mode Selection 30 11 30 6 6 Chip Select Configuration 30 12 30 7 Reset 30 12 30 8 Interrupts 30 12 Chapter 31 IEEE 1149 1 Test Access Port JTAG 31 1 Features 31 2 31 2 Modes of Operation 31 3 31 3 External Signal Description 31 3 31 3 1 Det...

Page 22: ... Processor Bus Output Timing Specifications 33 11 33 9 General Purpose I O Timing 33 17 33 10 Reset and Configuration Override Timing 33 18 33 11 I2 C Input Output Timing Specifications 33 19 33 12 Fast Ethernet AC Timing Specifications 33 20 33 12 1 MII Receive Signal Timing ERXD 3 0 ERXDV ERXER and ERXCLK 33 21 33 12 2 MII Transmit Signal Timing ETXD 3 0 ETXEN ETXER ETXCLK 33 21 33 12 3 MII Asyn...

Page 23: ...6 EMAC Register Set 3 6 3 7 MAC Status Register MACSR 3 6 3 8 EMAC Specific OEP Sequence Stall 3 13 3 9 Two s Complement Signed Fractional Equation 3 14 4 1 Cache Block Diagram 4 3 4 2 Cache Control Register CACR 4 8 4 3 Access Control Registers ACR0 ACR1 4 11 5 1 SRAM Base Address Register RAMBAR 5 2 6 1 CFM Block Diagram 6 3 6 2 CFM Array Memory Map 6 4 6 3 Flash Base Address Register FLASHBAR 6...

Page 24: ...er Low IPRLn 10 7 10 3 Interrupt Mask Register High IMRHn 10 8 10 4 Interrupt Mask Register Low IMRLn 10 8 10 5 Interrupt Force Register High INTFRCHn 10 9 10 6 Interrupt Force Register Low INTFRCLn 10 10 10 7 Interrupt RequestLevel Register IRLRn 10 10 10 8 IACK Level and Priority Register IACKLPRn 10 11 10 9 Interrupt Control Register ICRnx 10 12 10 10 Software and Level n IACK Registers SWIACKR...

Page 25: ...sfer 32 Bit Port 13 15 14 1 MCF5282 Block Diagram with Signal Interfaces 14 2 15 1 Synchronous DRAM Controller Block Diagram 15 2 15 2 DRAM Control Register DCR 15 5 15 3 DRAM Address and Control Register DACRn 15 6 15 4 DRAM Controller Mask Registers DMRn 15 8 15 5 Connections for External Memory Port Sizes 15 13 15 6 Burst Read SDRAM Access 15 14 15 7 Burst Write SDRAM Access 15 15 15 8 Auto Ref...

Page 26: ...r Group Lower Address Register GALR 17 40 17 21 FIFO Transmit FIFO Watermark Register TFWR 17 40 17 22 FIFO Receive Bound Register FRBR 17 41 17 23 FIFO Receive Start Register FRSR 17 42 17 24 Receive Descriptor Ring Start Register ERDSR 17 43 17 25 Transmit Buffer Descriptor Ring Start Register ETDSR 17 43 17 26 Receive Buffer Size Register EMRBR 17 44 17 27 Receive Buffer Descriptor RxBD 17 47 1...

Page 27: ...ister GPTDDR 20 16 20 22 Channel 3 Output Compare Pulse Accumulator Logic 20 19 21 1 DMA Timer Block Diagram 21 2 21 2 DTMRn Bit Definitions 21 4 21 3 DTXMRn Bit Definitions 21 5 21 4 DTERn Bit Definitions 21 6 21 5 DTRRn Bit Definitions 21 7 21 6 DTCRn Bit Definitions 21 8 21 7 DTCNn Bit Definitions 21 8 22 1 QSPI Block Diagram 22 2 22 2 QSPI RAM Model 22 5 22 3 QSPI Mode Register QMR 22 10 22 4 ...

Page 28: ... UART Mode Programming Flowchart 23 31 24 1 I2 C Module Block Diagram 24 2 24 2 I2C Standard Communication Protocol 24 3 24 3 Repeated START 24 4 24 4 Synchronized Clock SCL 24 5 24 5 I2C Address Register I2ADR 24 6 24 6 I2C Frequency Divider Register I2FDR 24 7 24 7 I2 C Control Register I2CR 24 8 24 8 I2 CR Status Register I2SR 24 9 24 9 I2C Data I O Register I2DR 24 10 24 10 Flow Chart of Typic...

Page 29: ...Data Registers 6 bit 26 13 26 17 Port Clear Output Data Registers 4 bit 26 13 26 18 Port B C D Pin Assignment Register PBCDPAR 26 14 26 19 Port E Pin Assignment Register PEPAR 26 15 26 20 Port F Pin Assignment Register PFPAR 26 17 26 21 Port J Pin Assignment Register PJPAR 26 18 26 22 Port SD Pin Assignment Register PSDPAR 26 19 26 23 Port AS Pin Assignment Register PASPAR 26 19 26 24 Port EH EL P...

Page 30: ...on 6 27 44 27 29 CCW Priority Situation 7 27 44 27 30 CCW Priority Situation 8 27 45 27 31 CCW Priority Situation 9 27 45 27 32 CCW Priority Situation 10 27 46 27 33 CCW Priority Situation 11 27 46 27 34 CCW Freeze Situation 12 27 47 27 35 CCW Freeze Situation 13 27 47 27 36 CCW Freeze Situation 14 27 47 27 37 CCW Freeze Situation 15 27 47 27 38 CCW Freeze Situation 16 27 48 27 39 CCW Freeze Situa...

Page 31: ...15 29 12 BDM Serial Interface Timing 29 18 29 13 Receive BDM Packet 29 19 29 14 Transmit BDM Packet 29 19 29 15 BDM Command Format 29 21 29 16 Command Sequence Diagram 29 22 29 17 RAREG RDREG Command Format 29 23 29 18 RAREG RDREG Command Sequence 29 23 29 19 WAREG WDREG Command Format 29 24 29 20 WAREG WDREG Command Sequence 29 24 29 21 READ Command Result Formats 29 25 29 22 READ Command Sequenc...

Page 32: ... Requirements 33 11 33 2 Read Write Internally Terminated Timing 33 13 33 3 Read Bus Cycle Terminated by TA 33 14 33 4 Read Bus Cycle Terminated by TEA 33 15 33 5 SDRAM Read Cycle 33 16 33 6 SDRAM Write Cycle 33 17 33 7 GPIO Timing 33 18 33 8 RSTI and Configuration Override Timing 33 19 33 9 I2 C Input Output Timings 33 20 33 10 MII Receive Signal Timing Diagram 33 21 33 11 MII Transmit Signal Tim...

Page 33: ...ellaneous Instruction Execution Times 2 26 2 16 EMAC Instruction Execution Times 2 27 2 17 General Branch Instruction Execution Times 2 28 2 18 BRA Bcc Instruction Execution Times 2 28 3 1 MACSR Field Descriptions 3 7 3 2 Summary of S U F I and R T Control Bits 3 8 3 3 EMAC Instruction Summary 3 12 4 1 Initial Fetch Offset vs CLNF Bits 4 5 4 2 Instruction Cache Operation as Defined by CACR 31 10 4...

Page 34: ...n 8 4 8 3 RAMBAR Field Description 8 5 8 4 CRSR Field Descriptions 8 6 8 5 CWCR Field Description 8 8 8 6 Core Watchdog Timer Delay 8 8 8 7 MPARK Field Description 8 13 8 8 SACU Register Memory Map 8 15 8 9 MPR n Field Descriptions 8 16 8 10 PACR Field Descriptions 8 17 8 11 PACR ACCESSCTRL Bit Encodings 8 17 8 12 Peripheral Access Control Registers PACRs 8 17 8 13 Grouped PeripheralAccess Control...

Page 35: ...ptions 11 5 11 6 EPDR Field Descriptions 11 6 11 7 EPPDR Field Descriptions 11 6 11 8 EPFR Field Descriptions 11 7 12 1 Chip Select Module Signals 12 1 12 2 Byte Enables Byte Write Enable Signal Settings 12 2 12 3 Accesses by Matches in CSARs and DACRs 12 4 12 4 D 19 18 External Boot Chip Select Configuration 12 5 12 5 Chip Select Registers 12 5 12 6 CSARn Field Description 12 7 12 7 CSMRn Field D...

Page 36: ...5 12 15 19 MCF5282 to SDRAM Interface 32 Bit Port 8 Column Address Lines 15 12 15 20 MCF5282 to SDRAM Interface 32 Bit Port 9 Column Address Lines 15 12 15 21 MCF5282 to SDRAM Interface 32 Bit Port 10 Column Address Lines 15 12 15 22 MCF5282 to SDRAM Interface 32 Bit Port 11 Column Address Lines 15 12 15 23 MCF5282 to SDRAM Interface 32 Bit Port 12 Column Address Lines 15 13 15 24 SDRAM Hardware C...

Page 37: ...Field Descriptions 17 41 17 31 FRBR Field Descriptions 17 41 17 32 FRSR Field Descriptions 17 42 17 33 ERDSR Field Descriptions 17 43 17 34 ETDSR Field Descriptions 17 44 17 35 EMRBR Field Descriptions 17 44 17 36 Receive Buffer Descriptor Field Definitions 17 48 17 37 Transmit Buffer Descriptor Field Definitions 17 50 18 1 Watchdog Module Operation in Low power Modes 18 1 18 2 Watchdog Timer Modu...

Page 38: ...Module Memory Map 21 3 21 2 DTMRn Field Descriptions 21 5 21 3 DTXMRn Field Descriptions 21 6 21 4 DTERn Field Descriptions 21 7 22 1 QSPI Input and Output Signals and Functions 22 3 22 2 QSPI_CLK Frequency as Function of System Clock and Baud Rate 22 7 22 3 QSPI Registers 22 9 22 4 QMR Field Descriptions 22 10 22 5 QDLYR Field Descriptions 22 12 22 6 QWR Field Descriptions 22 12 22 7 QIR Field De...

Page 39: ...scriptions 25 26 25 15 Mask examples for Normal Extended Messages 25 26 25 16 RXGMASK RX14MASK and RX15MASK Field Descriptions 25 28 25 17 ESTAT Field Descriptions 25 29 25 18 IMASK Field Descriptions 25 31 25 19 IFLAG Field Descriptions 25 31 25 20 RXECTR Field Descriptions 25 32 25 21 TXECTR Field Descriptions 25 32 26 1 MCF5282 Ports External Signals 26 4 26 2 MCF5282 Ports Module Memory Map 26...

Page 40: ...nts and Signal Designations 27 28 27 17 Multiplexed Channel Assignments and Signal Designations 27 29 27 18 RJURR Field Descriptions 27 30 27 19 LJSRR Field Descriptions 27 30 27 20 LJURR Field Descriptions 27 31 27 21 Analog Input Channels 27 34 27 22 Trigger Events 27 40 27 23 Status Bits 27 40 27 24 External Circuit Settling Time to 1 2 LSB 27 74 27 25 Error Resulting from Input Leakage IOff 27...

Page 41: ...ion Module Memory Map 30 4 30 4 CCR Field Descriptions 30 5 30 5 RCON Field Descriptions 30 6 30 6 RCSC Chip Select Configuration 30 7 30 7 BOOTPS Port Size Configuration 30 7 30 8 CIR Field Description 30 8 30 9 Reset Configuration Pin States During Reset 30 9 30 10 Configuration During Reset 30 9 30 11 Chip Configuration Mode Selection 30 11 30 12 Output Pad Driver Strength Selection 30 11 30 13...

Page 42: ...3 15 I2C Input Timing Specifications between SCL and SDA 33 19 33 16 I2C Output Timing Specifications between SCL and SDA 33 20 33 17 MII Receive Signal Timing 33 21 33 18 MII Transmit Signal Timing 33 22 33 19 MII Async Inputs Signal Timing 33 22 33 20 MII Serial Management Channel Timing 33 23 33 21 Timer Module AC Timing Specifications 33 24 33 22 QSPI Modules AC Timing Specifications 33 24 33 ...

Page 43: ...to develop products with the MCF5282 It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and basic details of the ColdFire architecture Organization Following is a summary and brief description of the major sections of this manual Chapter 1 Overview includes general descriptions of the modules and features incorporated ...

Page 44: ... registers in the interrupt controller memory map and the interrupt priority scheme Chapter 11 Edge Port Module EPORT describes EPORT module functionality including operation in low power mode Chapter 12 Chip Select Module describes the MCF5282 chip select implementation including the operation and programming model which includes the chip select address mask and control registers Chapter 13 Exter...

Page 45: ...overview and a description of operation including details of the QSPI s internal storage organization The chapter concludes with the programming model and a timing diagram Chapter 23 UART Modules describes the use of the universal asynchronous receiver transmitters UARTs implemented on the MCF5282 and includes programming examples Chapter 24 I2C Interface describes the MCF5282 I2C module including...

Page 46: ...ory Maps provides the entire address map for MCF5282 memory mapped registers Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture General Information The following documentation provides useful information about the ColdFire architecture and computer architecture in general...

Page 47: ...les instruction mnemonics are shown in lowercase italics Italics indicate variable command parameters Book titles in text are set in italics 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG FIELD Abbreviations for registers are shown in uppercase Specific bits fields or ranges appear in brackets For example RAMBAR BA identifies the base address field in the RAM base a...

Page 48: ...ss FIFO First in first out GPIO General purpose I O I2 C Inter integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last in first out LRU Least recently used LSB Least significant byte lsb Least significant bit MAC Multiply accumulate u...

Page 49: ...ational Conventions Instruction Operand Syntax Opcode Wildcard cc Logical condition example NE for not equal Register Specifications An Any address register n example A3 is address register 3 Ay Ax Source and destination address registers respectively Dn Any data register n example D5 is data register 5 Dy Dx Source and destination data registers respectively Rc Any control register example VBR is...

Page 50: ...ters for MOVEM instruction example D3 D0 shift Shift operation shift left shift right size Operand data size byte B word W longword L bc Both instruction and data caches dc Data cache ic Instruction cache vector Identifies the 4 bit vector number for trap instructions identifies an indirect data address referencing memory xxx identifies an absolute address referencing memory dn Signal displacement...

Page 51: ...nd the optional else clause is present the operations after else are performed If the condition is false and else is omitted the instruction performs no operation Refer to the Bcc instruction description as an example Subfields and Qualifiers Optional operation Identifies an indirect address dn Displacement value n bits wide example d16 is a 16 bit displacement Address Calculated effective address...

Page 52: ...dded Table 14 3 Table 14 3 14 11 Added Unlike the MCF5272 the MCF5282 does not have an independent SDRAM clock signal For the MCF5282 the timing of the SDRAM controller is controlled by the CLKOUT signal 15 2 15 3 Added Section 15 2 3 2 SDRAM Byte Strobe Connections 15 2 3 2 15 13 Added Note Because the MCF5282 has 24 external address lines the maximum SDRAM address size is 128 Mbits 15 2 3 1 15 9...

Page 53: ...r to be parked on the highest priority master 8 5 2 1 8 11 Changed MFD 2 9 to MFD 4 18 Figure 9 2 9 4 Changed equation in Normal PLL Clock Mode row to the following fsys fref 2 MFD 2 2RFD Table 9 7 9 11 Eliminated Section 12 4 1 4 Code Example Chapter 12 In Reset CSCR0 row changed D7 D6 D5 to D19 D18 Figure 12 4 12 8 Replaced SCKE with SCKE Table 14 1 14 3 Changed text to read The transmit FIFO us...

Page 54: ...Q2 PNQ0 with PNQ1 PQS0 with PQS1 PQS1 with PQS0 PJ6 with PJ7 RAS0 with SDRAM_CS0 RAS1 with SDRAM_CS1 and SCKE with SCKE Table 32 1 32 3 Changed value for ESD Target for Human Body Model to 2000 and ESD Target for Machine Model to 200 Table 33 1 33 1 Changed value in Maximum number of guaranteed program erase cycles before failure row to 10 000 Table 33 9 33 10 Changed the max value in specs B6a B6...

Page 55: ...bit in the second RAMBAR register must also be set to allow dual port access to the SRAM For more information see Section 8 4 2 Memory Base Address Register RAMBAR Table 5 1 5 2 Replaced Figure 6 2 CFM 512K Array Memory Map and renamed it CFM Array Memory Map Figure 6 2 6 4 Change value for page erase verify command to 0x06 Table 6 12 6 16 Change value for page erase verify command to 0x06 Table 6...

Page 56: ...erved bits Figure 23 11 23 13 Change I2CR 0xA to I2CR 0xA0 24 6 1 24 10 Changed When interfacing to 16 bit ports the port C and D pins and PJ 5 4 BS 1 0 can be configured as general purpose input output I O 30 2 1 30 2 Added additional device number order information to Table 32 2 for MCF5280 and MCF5281 at 66 and 80 MHz and MCF5282 at 80 MHz Table 32 2 32 7 Delete references to TA TL to TH Chapte...

Page 57: ...y Accumulate EMAC unit with four 48 bit accumulators to support 32 bit signal processing algorithms Illegal instruction decode that allows for 68K emulation support System debug support Real time trace for determining dynamic execution path Background debug mode BDM for in circuit debugging Real time debug support with one user visible hardware breakpoint register PC and address with optional data...

Page 58: ...he Motorola TOUCAN module Full implementation of the CAN protocol specification version 2 0B Standard data and remote frames up to 109 bits long Extended data and remote frames up to 127 bits long 0 8 bytes data length Programmable bit rate up to 1 Mbit sec Up to 16 message buffers MBs Configurable as receive Rx or transmit Tx Support standard and extended messages Unused message buffer MB space c...

Page 59: ...rd I2C bus Master or slave modes support multiple masters Automatic interrupt generation with programmable level Queued serial peripheral interface QSPI Full duplex three wire synchronous transfers Up to four chip selects available Master mode operation only Programmable master bit rates Up to 16 pre programmed transfers Queued analog to digital converter QADC 8 direct or up to 18 multiplexed anal...

Page 60: ...e prescaler Input capture capability with programmable trigger edge on input pin Output compare with programmable mode for the output pin Free run and restart modes Maskable interrupts on input capture or reference compare DMA trigger capability on input capture or reference compare Two 4 channel general purpose timers Four 16 bit input capture output compare channels per timer 16 bit architecture...

Page 61: ...K cycles Combinatorial path to provide wake up from low power modes DMA controller Four fully programmable channels Dual address transfer support with 8 16 and 32 bit data capability along with support for 16 byte 4 x 32 bit burst transfers Source destination address pointers that can increment or remain constant 24 bit byte transfer counter per channel Auto alignment transfers supported for effic...

Page 62: ...detection LVD Status flag indication of source of last reset Chip integration module CIM System configuration during reset Support for single chip master and test modes Selects one of four clock modes Sets boot device and its data port width Configures output pad drive strength Unique part identification number and part revision number General purpose I O interface Up to 142 bits of general purpos...

Page 63: ...ules DRAM Controller 2 Kbyte D Cache I Cache Debug Module DIV Clock Module Chip Configuration Reset Controller Power PLL Edgeport Interrupt Controller 0 Interrupt Controller 1 FEC UART0 Serial I O DMA Controller Watchdog Timer General Purpose Timer A General Purpose Timer B QSPI FlexCAN QADC PIT Timers PIT0 DTIM0 DTIM3 Management Module Ports Module PIT3 Internal Bus Arbiter System Control Module ...

Page 64: ...nd a complete set of instructions to process these data types The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost 1 1 1 1 Cache The 2 Kbyte cache can be configured into one of three possible organizations a 2 Kbyte instruction cache a 2 Kbyte data cache or a split 1 Kbyte instruction 1 Kbyte data cache The configurati...

Page 65: ...gnificantly if Ethernet packets are moved from the FEC into the SRAM rather than external memory prior to any processing 1 1 1 3 Flash This product incorporates SuperFlash technology licensed from SST The ColdFire Flash Module CFM is a non volatile memory NVM module for integration with the processor core The CFM is constructed with eight banks of 32K x 16 bit Flash arrays to generate 512 Kbytes o...

Page 66: ...he dynamic execution path of the processor at the CPU s clock rate 1 1 2 System Control Module This section details the functionality of the System Control Module SCM which provides the programming model for the System Access Control Unit SACU the system bus arbiter a 32 bit Core Watchdog Timer CWT and the system control registers and logic Specifically the system control includes the internal per...

Page 67: ... Their primary function is to provide an external memory interface to access off chip resources When not used for this function all of the pins may be used as general purpose digital I O pins In some cases the pin function is set by the operating mode and the alternate pin functions are not supported The digital I O pins on the MCF5282 are grouped into 8 bit ports Some ports do not use all eight b...

Page 68: ...82 for a given circuit board test by effectively reducing the boundary scan register to a single bit Disable the output drive to pins during circuit board testing Drive output pins to stable levels 1 1 10 UART Modules The MCF5282 contains three full duplex UARTs that function independently The three UARTs can be clocked by the system clock eliminating the need for an external crystal Each UART has...

Page 69: ...a DMA transfer 1 1 12 General Purpose Timers GPTA GPTB The two general purpose timers GPTA and GPTB are 4 channel timer modules Each timer consists of a 16 bit programmable counter driven by a 7 stage programmable prescaler Each of the four channels for each timer can be configured for input capture or output compare Additionally one of the channels channel 3 can be configured as a pulse accumulat...

Page 70: ...ow byte word longword or 16 byte burst line transfers These transfers are triggered by software explicitly setting a DCRn START bit or the occurrence of a hardware event from one of the on chip peripheral devices such as a capture event or an output reference event in a DMA timer DTIMn for each channel The DMA controller supports dual address mode to on chip devices 1 1 17 Reset The reset controll...

Page 71: ... between devices This bus is suitable for applications requiring occasional communications over a short distance between many devices 1 2 4 Queued Serial Peripheral Interface QSPI The queued serial peripheral interface module provides a synchronous serial peripheral interface with queued transfer capability It allows up to 16 transfers to be queued at once eliminating CPU intervention between tran...

Page 72: ...1 16 MCF5282 User s Manual MOTOROLA MCF5282 Specific Features status registers the 64 entry conversion command word CCW table and the 64 entry result table ...

Page 73: ...dFire Family Programmer s Reference Manual 2 1 Processor Pipelines Figure 2 1 is a block diagram showing the processor pipelines of a V2 ColdFire core Figure 2 1 ColdFire Processor Core Pipelines Instruction Instruction FIFO Decode Select Address read_data 31 0 IAG IC IB DSOC AGEX Address 31 0 Instruction Buffer Address Generation Fetch Cycle Generation Execute Operand Fetch Operand Execution Pipe...

Page 74: ... the Operand Execution Pipeline If the buffer is not empty the IFP stores the contents of the fetch cycle in the FIFO queue until it is required by the OEP In the Version 2 implementation the instruction buffer contains three 32 bit longwords of storage The Operand Execution Pipeline is implemented in a two stage pipeline featuring a traditional RISC datapath with a dual read ported register file ...

Page 75: ... USP This support provides the required isolation between operating modes of the processor The SSP is described in Section 2 2 3 2 Supervisor User Stack Pointers A7 and OTHER_A7 A subroutine call saves the PC on the stack and the return restores it from the stack Both the PC and the SR are saved on the supervisor stack during the processing of exceptions and interrupts The return from exception RT...

Page 76: ...3 N Negative condition code bit Set if the most significant bit of the result is set otherwise cleared 2 Z Zero condition code bit Set if the result equals zero otherwise cleared 1 V Overflow condition code bit Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size otherwise cleared 0 C Carry condition code bit Set if a carry out of the operand msb ...

Page 77: ...CCext23 One 16 bit mask register MASK One 32 bit status register MACSR including four indicator bits signaling product or accumulation overflow one for each accumulator PAV0 PAV3 These registers are shown in Figure 2 4 Figure 2 4 EMAC Register Set 2 2 3 Supervisor Programming Model Only system control software is intended to use the supervisor programming model to implement restricted operating sy...

Page 78: ...rocessor trace mode T bit supervisor or user mode S bit and master or interrupt state M bit All defined bits in the SR have read write access when in supervisor mode System Byte Condition Code Register CCR 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 T 0 S M 0 I 0 0 0 X N Z V C Figure 2 6 Status Register Table 2 2 SR Field Descriptions Bits Name Description 15 T Trace enable When set the processor performs...

Page 79: ...SP and USP This functionality is enabled by setting the enable user stack pointer bit CACR EUSP If this bit is cleared only the stack pointer A7 defined for previous ColdFire versions is available EUSP is zero at reset If EUSP is set the appropriate stack pointer register SSP or USP is accessed as a function of the processor s operating mode To support dual stack pointers the following two privile...

Page 80: ...he mode write protect and buffer write enables The ACRs are described in Section 4 4 2 2 Access Control Registers ACR0 ACR1 2 2 3 6 Memory Base Address Registers RAMBAR FLASHBAR Memory base address registers are used to specify the base address of the internal SRAM and Flash modules and indicate the types of references mapped to each Each base address register includes a base address write protect...

Page 81: ...nts of assembly language code Table 2 4 summarizes the new instructions added to Revision A ISA For more details see Section 2 14 ColdFire Instruction Set Architecture Enhancements D0 D7 0x 0 1 80 0x 0 1 87 No Data registers 0 7 0 load 1 store A0 A7 0x 0 1 88 0x 0 1 8F No Address registers 0 7 0 load 1 store A7 is user stack pointer Processor Miscellaneous Registers OTHER_A7 0x800 No Other stack p...

Page 82: ...n also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request Second the processor determines the exception vector number For all faults except interrupts the processor performs this calculation based on the exception type For interrupts the processor performs an interrupt acknowledge IACK bus cycle to obtain the vector number from th...

Page 83: ...etched the contents of the vector determine the address of the first instruction of the desired handler After the instruction fetch for the first opcode of the handler has been initiated exception processing terminates and normal instruction processing continues in the handler All ColdFire processors support a 1024 byte vector table aligned on any 1 Mbyte address boundary see Table 2 5 The table c...

Page 84: ... stack frame contains the 16 bit format vector word F V and the 16 bit status register and the second longword contains the 32 bit program counter address Figure 2 7 Exception Stack Frame Form The 16 bit format vector word contains 3 unique fields A 4 bit format field at the top of the system stack is always written with a value of 4 5 6 or 7 by the processor indicating a two longword frame format...

Page 85: ... do not generate an exception When the processor attempts to execute an instruction with a faulted opword and or extension words the access error is signaled and the instruction aborted For this type of exception the programming model has not been altered by the instruction generating the access error If the access error occurs on an operand read the processor immediately aborts the current instru...

Page 86: ... of 8 on an indexed effective addressing mode generates an address error as does an attempted execution of a full format indexed addressing mode 2 7 3 Illegal Instruction Exception Any attempted execution of an illegal 16 bit opcode except for line A and line F opcodes generates an illegal instruction exception vector 4 Additionally any attempted execution of any non MAC line A and most line F opc...

Page 87: ... to check for trace mode after processing other exception types As an example consider the execution of a TRAP instruction while in trace mode The processor will initiate the TRAP exception and then pass control to the corresponding handler If the system requires that a trace exception be processed it is the responsibility of the TRAP exception handler to check for this condition SR 15 in the exce...

Page 88: ... the auto incremented address after the fetch of the first longword and then 4 transfers control to the instruction address defined by the second longword operand within the stack frame 2 7 11 TRAP Instruction Exception The TRAP n instruction always forces an exception as part of its execution and is useful for implementing system calls 2 7 12 Interrupt Exception Interrupt exception processing inc...

Page 89: ...is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter After the initial instruction is fetched from memory program execution begins at the address in the PC If an access error or address error occurs before the first instruction is executed the processor enters the fault on fault halted state ColdFire processors load hardware configuration informa...

Page 90: ...is present in core This is the value used for MCF5282 13 EMAC EMAC execute engine status Indicates if optional enhanced MAC unit is present 0 EMAC execute engine not present in core 1 EMAC execute engine is present in core This is the value used for MCF5282 12 FPU FPU execute engine status Indicates if optional FPU unit is present 0 FPU execute engine not present in core This is the value used for...

Page 91: ...ion Bits Name Description 31 30 CL Cache line size This field is fixed to a hex value of 0x0 indicating a 16 byte cache line size 29 28 ICA Instruction cache associativity 00 Four way 01 Direct mapped This is the value used for MCF5282 27 24 ICSIZ Instruction cache size 0000 No instruction cache 0001 512B instruction cache 0010 1KB instruction cache 0011 2KB instruction cache This is the value use...

Page 92: ...512KB Flash This is the value used for MCF5282 0xC 0xF Reserved 19 16 ROM0SIZ ROM bank 0 size 0x0 0x3 No ROM This is the value used for MCF5282 0100 4KB ROM 0101 8KB ROM 0110 16KB ROM 0111 32KB ROM 1000 64KB ROM 1001 128KB ROM 0xA 0xF Reserved 15 14 BUSW Encoded bus data width 00 32 bit data bus only configuration currently in use 13 12 DCA Data cache associativity 00 Four way 01 Direct mapped Thi...

Page 93: ...cludes the assumptions concerning the timing values and the execution time details 2 8 1 Timing Assumptions For the timing data presented in this section the following assumptions apply 1 The operand execution pipeline OEP is loaded with the opword and all required extension words at the beginning of each instruction execution This implies that the OEP does not wait for the instruction fetch pipel...

Page 94: ...tion assume that an infinite zero wait state memory is attached to the processor core 4 All operand data accesses are aligned on the same byte boundary as the operand size that is 16 bit operands aligned on 0 modulo 2 addresses and 32 bit operands aligned on 0 modulo 4 addresses If the operand alignment fails these guidelines it is misaligned The processor core decomposes the misaligned operand re...

Page 95: ... 1 1 3 1 1 xxx l 3 1 0 3 1 1 3 1 1 3 1 1 d16 PC 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 PC Xi 4 1 0 4 1 1 4 1 1 4 1 1 xxx 1 0 0 3 0 1 3 0 1 3 0 1 Table 2 12 Move Long Execution Times Source Destination Rx Ax Ax Ax d16 Ax d8 Ax Xi xxx wl Dn 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 An 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 2 0 1 1 0 1 An 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 An 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 ...

Page 96: ... 1 0 1 2 0 1 1 0 1 ext w Dx 1 0 0 ext l Dx 1 0 0 extb l Dx 1 0 0 ff1 Dx 1 0 0 neg l Dx 1 0 0 negx l Dx 1 0 0 not l Dx 1 0 0 scc Dx 1 0 0 stldsr imm 5 0 1 swap Dx 1 0 0 tst b ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst w ea 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 tst l ea 1 0 0 2 1 0 2 1 0 2 1 0 2 1 0 3 1 0 2 1 0 1 0 0 Table 2 14 Two Operand Instruction Execution Times Opcode EA ...

Page 97: ...0 23 1 0 23 1 0 23 1 0 23 1 0 24 1 0 23 1 0 20 0 0 divs l1 ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 divu l1 ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 eor l Dy ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 eori l imm Dx 1 0 0 lea ea Ax 1 0 0 1 0 0 2 0 0 1 0 0 lsl l ea Dx 1 0 0 1 0 0 lsr l ea Dx 1 0 0 1 0 0 moveq imm Dx 1 0 0 muls w ea y Dx 4 0 0 6 1 0 6 1 0 6 1 0 6 1 0 7 1 0 6 1 0 4 1 0 mulu w ea y D...

Page 98: ...7 0 0 2 movec Ry Rc 9 0 1 movem l ea list 1 n n 0 1 n n 0 movem l list ea 1 n 0 n 1 n 0 n nop 3 0 0 pea ea 2 0 1 2 0 1 4 3 0 1 5 2 0 1 pulse 1 0 0 stop imm 3 0 0 3 trap imm 15 1 2 trapf 1 0 0 trapf w 1 0 0 trapf l 1 0 0 unlk Ax 2 1 0 wddata ea 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 3 1 0 wdebug ea 5 2 0 5 2 0 1n is the number of registers moved by the MOVEM opcode 2If a MOVE W imm SR instruction is e...

Page 99: ...ac l Ry Rx Raccx 1 0 0 mac w Ry Rx ea Rw Raccx 2 1 0 2 1 0 2 1 0 2 1 0 1 1 Effective address of d16 PC not supported mac l Ry Rx ea Rw Raccx 2 1 0 2 1 0 2 1 0 2 1 0 1 msac w Ry Rx ea Rw 2 1 0 2 1 0 2 1 0 2 1 0 1 msac l Ry Rx ea Rw Raccx 2 1 0 2 1 0 2 1 0 2 1 0 1 mov l ea y Raccx 1 0 0 1 0 0 mov l Raccy Raccx 1 0 0 mov l ea y MACSR 5 0 0 5 0 0 mov l ea y Rmask 4 0 0 4 0 0 mov l ea y Raccext01 1 0 0...

Page 100: ...tion the depth of the EMAC pipeline is exposed and the execution time is four cycles 2 13 Branch Instruction Execution Times 2 14 ColdFire Instruction Set Architecture Enhancements This section describes the new opcodes implemented as part of the Revision A enhancements to the basic ColdFire ISA Table 2 17 General Branch Instruction Execution Times Opcode EA Effective Address Rn An An An d16 An d1...

Page 101: ...es Size longword The contents of the destination data register are bit reversed that is new Dx 31 old Dx 0 new Dx 30 old Dx 1 new Dx 0 old Dx 31 Condition Codes Not affected Instruction Field Register field Specifies the destination data register Dx Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Register Dx BITREV V2 V3 Core ISA_A V4 Core ISA_B V2 Core ISA_A Opc...

Page 102: ...tents of the destination data register are byte reversed as defined below Condition Codes Not affected Instruction Field Register field Specifies the destination data register Dx Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 Register Dx new Dx 31 24 old Dx 7 0 new Dx 23 16 old Dx 15 8 new Dx 15 8 old Dx 23 16 new Dx 7 0 old Dx 31 24 BYTEREV V2 V3 Core ISA_A V4 ...

Page 103: ...irst set bit appears as shown below If the source data is zero then an offset of 32 is returned Instruction Field Destination Register field Specifies the destination data register Dx Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 1 1 0 0 0 Destination Register Dx Old Dx 31 0 New Dx 31 0 0b1 0x0000 0000 0b01 0x0000 0001 0b001 0x0000 0002 0b00000 0010 0x0000 001E 0b00000 0...

Page 104: ...equest to be stored in memory using the SR IML field and then masks interrupts by loading the SR IML field with 0x7 if desired If execution is attempted with bit 13 of the immediate data cleared attempting to place the processor in user mode a privilege violation exception is generated The opcode for STRLDSR is 0x40E7 46FC Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 1 ...

Page 105: ...erent performance levels and capabilities The original MAC uses a three stage execution pipeline optimized for 16 bit operands and featuring a 16x16 multiply array with a single 32 bit accumulator The EMAC features a four stage pipeline optimized for 32 bit operands with a fully pipelined 32x32 multiply array and four 48 bit accumulators The first ColdFire MAC supported signed and unsigned integer...

Page 106: ... example small digital filters can tolerate some variance in an algorithm s execution time but larger more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond the scope of any processor architecture and may require full DSP implementation To strike a balance between speed size and functionality the ColdFire MAC is optimized for a small set of oper...

Page 107: ...mination that the OEP normally uses if no MAC hardware is present The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers followed by the addition or subtraction of the product to or from the value in an accumulator Optionally the product may be shifted left or right by 1 bit before addition or subtraction Hardware support for saturation arithmetic can be enabl...

Page 108: ...w relative alignment of input operands the full 64 bit product the resulting 40 bit product used for accumulation and 48 bit accumulator formats Figure 3 4 Fractional Alignment Figure 3 5 Signed and Unsigned Integer Alignment X OperandY OperandX Product Extended Product Accumulator 32 8 Extension Byte Upper 7 0 0 32 40 23 40 8 40 8 Accumulator 31 0 Extension Byte Lower 7 0 X OperandY OperandX Prod...

Page 109: ...h the input data and another is loaded with the coefficient Two 16 bit multiply accumulates can be performed without fetching additional operands between instructions by alternating the word choice during the calculations The EMAC has four accumulator registers versus the MAC s single accumulator The additional registers improve the performance of some algorithms by minimizing pipeline stalls need...

Page 110: ...ne 32 bit MAC status register MACSR including four indicator bits signaling product or accumulation overflow one for each accumulator PAV0 PAV3 These registers are shown in Figure 3 6 Figure 3 6 EMAC Register Set 3 4 1 MAC Status Register MACSR MACSR functionality is organized as follows MACSR 11 8 contains one product accumulation overflow flag per accumulator MACSR 7 4 defines the operating conf...

Page 111: ...16 bit value Accumulator is moved to a general purpose register as a 32 bit value 1 The accumulator is rounded to a 16 bit value using the round to nearest even method when it is moved to a general purpose register See Section 3 4 1 1 1 Rounding The resulting 16 bit value is stored in the lower word of the destination register The upper word is zero filled The accumulator value is not affected by ...

Page 112: ...MAC V is set only if a product overflow occurs or the accumulation overflows the 48 bit structure V is evaluated on each MAC or MSAC operation and uses the appropriate PAVx flag in the next state V evaluation 0 EV Extension overflow Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode or the 40 lsbs in fractional mode of the destination accumulator However the resul...

Page 113: ...f R0 U so the result is always even lsb 0 If the lsb of R0 U 1 and R0 L 0x8000 the number is rounded up If the lsb of R0 U 0 and R0 L 0x8000 the number is rounded down This method minimizes rounding bias and creates as statistically correct an answer as possible The rounding algorithm is summarized in the following pseudocode if R0 L 0x8000 then Result R0 U else if R0 L 0x8000 then Result R0 U 1 e...

Page 114: ...move l 0 macsr disable rounding in the macsr move l d0 acc0 restore the accumulators move l d1 acc1 move l d2 acc2 move l d3 acc3 move l d4 accext01 restore the accumulator extensions move l d5 accext23 move l d6 mask restore the address mask move l d7 macsr restore the macsr By executing this type of sequence the exact state of the EMAC programming model can be correctly saved and restored 3 4 1 ...

Page 115: ...a array as a circular queue For MAC MOVE operations the MASK contents can optionally be included in all memory effective address calculations The syntax is as follows MAC sz Ry RxSF ea y Rw The operator enables the use of MASK and causes bit 5 of the extension word to be set The exact algorithm for the use of MASK is as follows if extension word bit 5 1 the MASK bit then if ea An oa An 0xFFFF MASK...

Page 116: ...rands and adds subtracts the product to from an accumulator Multiply Accumulate with Load MAC Ry Rx ea y Rw ACCx MSAC Ry Rx ea y Rw ACCx Multiplies two operands and combines the product to an accumulator while loading a register with the memory operand Load Accumulator MOV L Ry imm ACCx Loads an accumulator with a 32 bit operand Store Accumulator MOV L ACCx Rx Writes the contents of an accumulator...

Page 117: ...er can reduce or eliminate sequence related store MAC instruction stalls In fact a major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between the accumulator s and the general purpose registers 3 5 2 Data Representation MACSR S U F I selects one of the following three modes where each mode defines a unique operand type Two s complement signed int...

Page 118: ...AC design includes an additional product accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction See Section 3 4 1 MAC Status Register MACSR For the MAC design the assembler syntax of the MAC multiply and add to accumulator and MSAC multiply and subtract from accumulator instructions does not include a...

Page 119: ...ghout this example a comma separated list in curly brackets indicates a concatenation operation switch MACSR 6 5 MACSR S U F I case 0 signed integers if MACSR OMC 0 MACSR PAVx 0 then MACSR PAVx 0 select the input operands if sz word then if U Ly 1 then operandY 31 0 sign extended Ry 31 Ry 31 16 else operandY 31 0 sign extended Ry 15 Ry 15 0 if U Lx 1 then operandX 31 0 sign extended Rx 31 Rx 31 16...

Page 120: ...t MSAC then result 47 0 ACCx 47 0 product 47 0 else result 47 0 ACCx 47 0 product 47 0 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVx 1 MACSR V 1 if MACSR OMC 1 then accumulation overflow saturationMode enabled if result 47 1 then result 47 0 0x0000_7fff_ffff else result 47 0 0xffff_8000_0000 transfer the result to the accumulator ACCx 47 0 result 47 0 MACSR V MACSR PAVx...

Page 121: ...bits and combine with accumulator check for the 1 1 overflow case if operandY 31 0 0x8000_0000 operandX 31 0 0x8000_0000 then product 71 64 0x00 zero fill else product 71 64 8 product 63 sign extend if inst MSAC then result 47 0 ACCx 47 0 product 71 24 else result 47 0 ACCx 47 0 product 71 24 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVx 1 MACSR V 1 if MACSR OMC 1 then ...

Page 122: ...n product overflow MACSR PAVx 1 MACSR V 1 if inst MSAC MACSR OMC 1 then result 47 0 0x0000_0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 47 0 0xffff_ffff_ffff zero fill to 48 bits before performing any scaling product 47 40 0 zero fill upper byte scale product before combining with accumulator switch SF 2 bit scale factor case 0 no scaling specified break case 1 S...

Page 123: ...SR V 1 if inst MSAC MACSR OMC 1 then result 47 0 0x0000_0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMode enabled result 47 0 0xffff_ffff_ffff transfer the result to the accumulator ACCx 47 0 result 47 0 MACSR V MACSR PAVx MACSR N ACCx 47 if ACCx 47 0 0x0000_0000_0000 then MACSR Z 1 else MACSR Z 0 if ACCx 47 32 0x0000 then MACSR EV 0 else MACSR EV 1 break ...

Page 124: ...3 20 MCF5282 User s Manual MOTOROLA EMAC Instruction Set Summary ...

Page 125: ...onfiguration is controlled by bits in the cache control register CACR that is detailed later in this chapter For the instruction or data only configurations only the associated instruction or data line fill buffer is used For the split cache configuration one half of the tag and storage arrays is used for an instruction cache and one half is used for a data cache The split cache configuration uses...

Page 126: ...in response to a cache miss With each fetch the contents of the associated line fill buffer are examined Thus each fetch address examines both the tag memory array and the associated line fill buffer to see if the desired address is mapped into either hardware resource A cache hit in either the memory array or the associated line fill buffer is serviced in a single cycle Because the line fill buff...

Page 127: ...action with Other Modules Because both the cache and high speed SRAM module are connected to the ColdFire core s local data bus certain user defined configurations can result in simultaneous fetch processing If the referenced address is mapped into the SRAM module that module will service the request in a single cycle In this case data accessed from the cache is simply discarded and no external me...

Page 128: ... references for accesses to cached instructions Therefore software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code segments if instructions are cached The cache invalidation can be performed in several ways For the instruction or data only configurations setting CACR CINV forces the entire cache to be marked as invalid The invalidation o...

Page 129: ...rmined by the value contained in the 2 bit CLNF field of the CACR and the miss address Table 4 1 shows the relationship between the CLNF bits the miss address and the size of the external fetch Depending on the runtime characteristics of the application and the memory response speed overall performance may be increased by programming the CLNF bits to values 00 01 For all cases of a line sized fetc...

Page 130: ... instruction fetches If the processor branches to an odd word address a word sized instruction fetch is generated For instruction fetches the fill buffer can also be used as temporary storage for line sized bursts of non cacheable references under control of CACR CEIB With this bit set a noncacheable instruction fetch is processed as defined by Table 4 2 For this condition the line fill buffer is ...

Page 131: ...andom values after reset The access column indicates if the corresponding register allows both read write functionality R W read only functionality R or write only functionality W If a read access to a write only register is attempted zeros will be returned If a write access to a read only register is attempted the access will be ignored and no write will occur 4 4 2 Cache Registers 4 4 2 1 Cache ...

Page 132: ...tion is invalid the contents of the line fill buffer can be written into the memory array while CFRZ is asserted 0 Normal Operation 1 Freeze valid cache lines 26 25 Reserved should be cleared 24 CINV Cache invalidate The cache invalidate operation is not a function of the CENB state that is this operation is independent of the cache being enabled or disabled Setting this bit forces the cache to in...

Page 133: ...cesses are never written into the memory array 0 Disable burst fetches on noncacheable accesses 1 Enable burst fetches on noncacheable accesses 9 DCM Default cache mode This bit defines the default cache mode 0 is cacheable 1 is noncacheable For more information on the selection of the effective memory attributes see Section 4 3 2 Memory Reference Attributes 0 Caching enabled 1 Caching disabled 8 ...

Page 134: ...e uses lower half of tag and storage arrays and 1 KByte direct mapped write through data cache uses upper half of tag and storage arrays 1 0 1 Instruction Cache 2 KByte direct mapped instruction cache uses all of tag and storage arrays 1 1 0 Data Cache 2 KByte direct mapped write through data cache uses all of tag and storage arrays Table 4 6 Cache Invalidate All as Defined by CACR 23 22 21 20 CAC...

Page 135: ...s Address and CLNF CLNF 1 0 Longword Address Bits 00 01 10 11 00 Line Line Line Longword 01 Line Line Longword Longword 10 Line Line Line Line 11 Line Line Line Line 31 24 23 16 Field AB AM Reset 0000_0000_0000_0000 R W W 15 14 13 12 7 6 5 4 3 2 1 0 Field EN SM CM BUFW WP Reset 0000_0000_0000_0000 R W W Figure 4 3 Access Control Registers ACR0 ACR1 Table 4 8 ACR Field Descriptions Bits Name Descri...

Page 136: ... the local bus is terminated immediately and the operation is then buffered in the bus controller In this mode operand write cycles are effectively decoupled between the processor s local bus and the external bus Generally the enabling of buffered writes provides higher system performance but recovery from access errors may be more difficult For the V2 ColdFire CPU the reporting of access errors o...

Page 137: ...ected to the processor s high speed local bus it can service processor initiated access or memory referencing commands from the debug module Depending on configuration information instruction fetches may be sent to both the cache and the SRAM block simultaneously If the reference is mapped into the region defined by the SRAM the SRAM provides the data back to the processor and the cache data disca...

Page 138: ... BA21 BA20 BA19 BA18 BA17 BA16 Reset Undefined R W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field PRI1 PRI2 SPV WP C I SC SD UC UD V Reset Undefined 0 R W W Address CPU 0xC05 Figure 5 1 SRAM Base Address Register RAMBAR Table 5 1 SRAM Base Address Register Bits Name Description 31 16 BA Base address Defines the 0 modulo 64K base address of the SRAM module By programming this field the SRAM may be l...

Page 139: ...information see Section 8 4 2 Memory Base Address Register RAMBAR 8 WP Write protect Allows only read accesses to the SRAM When this bit is set any attempted write access will generate an access error exception to the ColdFire processor core 0 Allows read and write accesses to the SRAM module 1 Allows only read accesses to the SRAM module 7 6 Reserved should be cleared 5 1 C I SC SD UC UD Address ...

Page 140: ...o D0 SRAM_INIT_LOOP clr l A0 clear 4 bytes of SRAM subq l 1 D0 decrement loop counter bne b SRAM_INIT_LOOP if done then exit else continue looping 5 3 4 Power Management As noted previously depending on the configuration defined by the RAMBAR instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously If the access is mapped to the SRAM module it sources the read d...

Page 141: ...MOTOROLA Chapter 5 Static RAM SRAM 5 5 SRAM Programming Model ...

Page 142: ...5 6 MCF5282 User s Manual MOTOROLA SRAM Programming Model ...

Page 143: ...me however it is not possible to read from a Flash physical block while the same block is being programmed or erased The array used in the MCF5282 makes it possible to program or erase one pair of Flash physical blocks under the control of software routines executing out of another pair NOTE The MCF5281 implements only 256 Kbytes of Flash half that of the MCF5282 6 1 Features Features of the CFM i...

Page 144: ...ime through two way longword interleaving and speculative reads Flash physical blocks are interleaved on longword 4 byte boundaries Therefore all Flash program erase and verify commands operate on adjacent Flash physical blocks and are initiated with a single aligned 32 bit write to the appropriate array location Any other write operation will cause a cycle termination transfer error Page erase op...

Page 145: ...6 1 CFM Block Diagram Flash Interface SATO SATO SATO SATO BIST Engine Internal Bus Memory Array Backdoor Access Flash Control Registers Block 0H 32K x 16 Memory Array Block 0L 32K x 16 Memory Array Block 3H 32K x 16 Memory Array Block 3L 32K x 16 Flash Physical Block 0 Flash Physical Block 3 Note Mass Erase Block 0 256 Kbytes Flash Physical Block 0 and Flash Physical Block 1 Mass Erase Block 1 256...

Page 146: ...ory NOTE The CFM on the MCF5281 is constructed with four banks of 32K x 16 bit Flash arrays to generate 256 Kbytes of 32 bit Flash memory Figure 6 2 CFM Array Memory Map 0x0007 FFFF 0x0004 000C 0x0000 0000 0x0000 0004 0x0000 0008 0x0000 000C 0x0003 FFFF 0x0004 0000 0x0004 0004 0x0004 0008 3H 1 3L 1 2H 1 2L 1 3H 0 3L 0 2H 0 2L 0 1H 1 1L 1 0H 1 0L 1 1H 1 1L 1 0H 0 0L 0 Logical Block 1 256 Kbytes Mem...

Page 147: ...SHBAR controls the operation of the Flash module The FLASHBAR holds the base address of the Flash The MOVEC instruction provides write only access to this register The FLASHBAR can be read or written from the debug module in a similar manner All undefined bits in the register are reserved These bits are ignored during writes to the FLASHBAR and return zeroes when read from the debug module The bac...

Page 148: ...r example for a DMA transfer from the first location of Flash when IPSBAR is still at its default location of 0x4000_0000 the source register would be loaded with 0x4400_0000 Backdoor access to Flash for reads can be made by the bus master but it takes 2 cycles longer than a direct read of the Flash if using its FLASHBAR address NOTE The Flash is marked as valid on reset based on the RCON reset co...

Page 149: ...te access will generate an access error exception to the ColdFire processor core 0 Allows read and write accesses to the Flash module 1 Allows only read accesses to the Flash module 7 6 Reserved should be cleared 5 1 C I SC SD UC UD Address space masks ASn These five bit fields allow certain types of accesses to be masked or inhibited from accessing the Flash module The address space mask bits are...

Page 150: ...Bits 23 16 Bits 15 8 Bits 7 0 Access 1 1 S Supervisor access only User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error 0x1D_0000 CFMMCR CFMCLKD Reserved 2 2 Addresses not assigned to a register and undefined register bits are reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect S ...

Page 151: ...bles an interrupt in case the access error flag ACCERR is set 1 An interrupt will be requested whenever the ACCERR flag is set 0 ACCERR interrupts disabled 7 CBEIE Command buffer empty interrupt enable The CBEIE bit is readable and writable CBEIE enables an interrupt request when the command buffer for the Flash physical blocks is empty 1 Request an interrupt whenever the CBEIF flag is set 0 Comma...

Page 152: ...reset 0 CFMCLKD has not been written 6 PRDIV8 Enable prescaler divide by 8 1 Enables a prescaler that divides the CFM clock by 8 before it enters the CFMCLKD divider 0 The CFM clock is fed directly into the CFMCLKD divider 5 0 DIV Clock divider field The combination of PRDIV8 and DIV 5 0 effectively divides the CFM input clock down to a frequency between 150 kHz and 200 kHz The frequency range of ...

Page 153: ...security status 1 Flash security is enabled 0 Flash security is disabled 29 16 Reserved Should be cleared 15 0 SEC 15 0 Security field The SEC bits define the security state of the device see below SEC 15 0 Description 0x4AC8 Flash secured 1 1 The 0x4AC8 value was chosen because it represents the ColdFire Halt instruction making it unlikely that compiled code accidentally programmed at the securit...

Page 154: ...ion longword at offset 0x1D_0400 must be written with the desired value The CFMPROT controls the protection of thirty two 16 Kbyte Flash logical sectors in the 512 Kbyte Flash array Figure 6 8 shows the association between each bit in the CFMPROT and its corresponding logical sector 31 16 Field PROT Reset See Note R W R W 15 0 Field PROT Reset See Note R W R W Address IPSBAR 0x1D_0010 Note The CFM...

Page 155: ...t See Note R W R W Address IPSBAR 0x1D_0014 Note The CFMPROT register is loaded at reset from the Flash Supervisor user Space Restrictions longword stored at the array base address 0x0000_040C Figure 6 9 CFM Supervisor Access Register CFMSACC ARRAY_BASE 0x0000_0000 16Kbyte Sector ARRAY_BASE 0x0007_FFFF SECTOR 0 SECTOR 1 SECTOR 2 SECTOR 31 ARRAY_BASE 0x0000_4000 ARRAY_BASE 0x0000_8000 PROTECT 31 PR...

Page 156: ...sector is mapped in unrestricted address space 31 16 Field DATA Reset See Note R W R W 15 0 Field DATA Reset See Note R W R W Address IPSBAR 0x1D_0018 Note The CFMPROT register is loaded at reset from the Flash Program Data Space Restrictions longword stored at the array base address 0x0000_0410 Figure 6 10 CFM Data Access Register CFMDACC Table 6 9 CFMDACC Field Descriptions Bits Name Description...

Page 157: ... 6 CCIF Command complete interrupt flag The CCIF flag indicates that no commands are pending for the Flash physical blocks CCIF is set and cleared automatically upon start and completion of a command Writing to CCIF has no effect The CCIF bit can trigger an interrupt request if the CCIE bit is set in CFMCR 1 All commands are completed 0 Command in progress 5 PVIOL Protection violation flag The PVI...

Page 158: ...rify command has been requested and the CCIF flag is set then the selected Flash physical blocks are not blank 1 0 Reserved should be cleared 7 6 0 Field CMD Reset 0000_0000 R W R W Address IPSBAR 0x1D_0024 Figure 6 12 CFM Command Register CFMCMD Table 6 11 CFMCMD Field Descriptions Bits Name Description 7 Reserved should be cleared 6 0 CMD 6 0 Command Valid Flash user mode commands are shown in T...

Page 159: ... whenever a transfer request is initiated by the ColdFire core the address is equal to an address within the valid range of the CFM memory space and the read write control indicates a write cycle The action taken on a valid CFM array write depends on the subsequent user command issued as part of a valid command sequence Only aligned 32 bit write operations are allowed to the CFM array Byte and wor...

Page 160: ...than 12 8 MHz PRDIV8 1 otherwise PRDIV8 0 2 Determine DIV 5 0 by using the following equation Keep only the integer portion of the result and discard any fraction Do not round the result 3 Thus the Flash state machine clock will be Consider the following example for fSYS 66 MHz So for fSYS 66 MHz writing 0x54 to CFMCLKD will set fCLK to 196 43 kHz which is a valid frequency for the timing of progr...

Page 161: ...he command write sequence can be started This three step command write sequence must be strictly followed No intermediate writes to the CFM module are permitted between these three steps The command write sequence is 1 Write the 32 bit longword to be programmed to its location in the CFM array The address and data will be stored in internal buffers All address bits are valid for program commands T...

Page 162: ... for the erase and verify algorithms with the exceptions noted in step 1 above 6 4 3 3 Flash Valid Commands Table 6 13 summarizes the valid Flash user commands Table 6 13 Flash User Commands CFMCMD Meaning Description 0x05 Erase verify Verify that all 256 Kbytes of Flash from two interleaving physical blocks are erased If both blocks are erased the BLANK bit will be set in the CFMUSTAT register up...

Page 163: ...STAT ACCERR BIT WRITE 0x10 TO CLEAR NO YES NO PROTECTION VIOLATION CHECK ACCESS ERROR CHECK READ CFMUSTAT NO NO ADDRESS DATA COMMAND BUFFER EMPTY CHECK NEXT WRITE YES NO TO ARRAY ADDRESS CFMUSTAT PVIOL BIT WRITE 0x20 TO CLEAR YES BIT POLLING FOR COMMAND COMPLETION CHECK READ CFMUSTAT YES NOTE COMMAND SEQUENCE ABORTED BY WRITING 0x00 TO CFMUSTAT NOTE COMMAND SEQUENCE ABORTED BY WRITING 0x00 TO CFMU...

Page 164: ...am or erase command is in progress 10 Aborting a command sequence by writing a 0 to CBEIF after the longword write to the CFM array or after writing a command to CFMCMD and before launching it The PVIOL flag will be set during a command write sequence after the longword write to the CFM array if any of the illegal operations below are performed Such operations will cause the command sequence to im...

Page 165: ...boot device to provide the reset vector and terminate the bus cycle 6 5 Flash Security Operation The CFM array provides security information to the integration module and the rest of the MCU A longword in the Flash configuration field stores this information This longword is read automatically after each reset and is stored in the CFMSEC register NOTE Enabling Flash security will disable BDM commu...

Page 166: ...ains in effect unless changed by program or erase operations The back door method of unsecuring the device has no effect on the program and erase protections defined by the CFM protection register CFMPROT 6 5 2 Erase Verify Check Security can be disabled by verifying that the CFM array is blank If required the mass erase command can be executed for each pair of Flash physical blocks that comprise ...

Page 167: ...pleted or when the address data and command buffers are empty Table 6 14 shows the CFM interrupt mechanism Table 6 14 CFM Interrupt Sources Interrupt Source Interrupt Flag Local Enable Command data and address buffers empty CBEIF CFMUSTAT CBEIE CFMCR All commands are completed CCIF CFMUSTAT CCIE CFMCR Access error ACCERR CFMUSTAT AEIE CFMCR ...

Page 168: ...6 26 MCF5282 User s Manual MOTOROLA Interrupts ...

Page 169: ...t Doze Stop Ability to shut down most peripherals independently Ability to shut down the external CLKOUT pin 7 2 Memory Map and Registers This subsection provides a description of the memory map and registers 7 2 1 Programming Model The PMM programming model consists of one register The low power control register LPCR specifies the low power mode entered when the STOP instruction is issued and con...

Page 170: ...desired low power mode and loading the appropriate interrupt priority level 2 At the appropriate time the processor executes the privileged STOP instruction Once the processor has stopped execution it asserts a specific Processor Status PST encoding Issuing the STOP instruction when the LPICR ENBSTOP bit is set causes the SCM to enter stop mode Table 7 1 Chip Configuration Module Memory Map IPSBAR...

Page 171: ...icular low power mode 5 Once an appropriately high interrupt request level arrives the interrupt controller signals its presence and the SIM responds by asserting the request to exit low power mode 6 The low power mode control logic senses the request signal and re enables the appropriate clocks 7 With the processor clocks enabled the core processes the pending interrupt request 7 6 4 3 0 Field EN...

Page 172: ...R Table 7 4 LPCR Field Descriptions Bits Name Description 7 6 LPMD Low power mode select Used to select the low power mode the chip enters once the ColdFire CPU executes the STOP instruction These bits must be written prior to instruction execution for them to take effect The LPMD 1 0 bits are readable and writable in all modes Table 7 5 illustrates the four different power modes that can be confi...

Page 173: ...s idles the CPU with no cycles active powers down the system and stops all internal clocks appropriately During stop mode the system clock is stopped low For entry into stop mode the LPICR ENBSTOP bit must be set before a STOP instruction is issued A wakeup event is required to exit a low power mode and return to run mode Wakeup events consist of any of these conditions Any type of reset Any valid...

Page 174: ...wakeup event is detected In this mode peripherals may be programmed to continue operating and can generate interrupts which cause the CPU to exit from wait mode 7 3 1 3 Doze Mode Doze mode affects the CPU in the same manner as wait mode except that each peripheral defines individual operational characteristics in doze mode Peripherals which continue to run and have the capability of producing inte...

Page 175: ...ing any low power mode 7 3 2 2 Static Random Access Memory SRAM SRAM is disabled during any low power mode No recovery time is required when exiting any low power mode 7 3 2 3 Flash The Flash module is in a low power state if not being accessed No recovery time is required after exit from any low power mode 7 3 2 4 System Control Module SCM The SCM s core Watchdog timer can bring the device out of...

Page 176: ...ct Module In wait and doze modes the chip select module continues operation but does not generate interrupts therefore it cannot bring a device out of a low power mode This module is stopped in stop mode 7 3 2 7 DMA Controller DMAC0 DMA3 In wait and doze modes the DMA controller is capable of bringing the device out of a low power mode by generating an interrupt either upon completion of a transfe...

Page 177: ... was exited by reset 7 3 2 10 Queued Serial Peripheral Interface QSPI In wait and doze modes the queued serial peripheral interface QSPI may generate an interrupt to exit the low power modes Clearing the QSPI enable bit SPE disables the QSPI function The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode In stop mode the QSPI stops immediately and freezes operation reg...

Page 178: ...nerate an interrupt to exit the low power modes Clearing the ECNTRL ETHER_EN bit disables the FEC function The FEC is unaffected by wait mode and may generate an interrupt to exit this mode In stop mode the FEC stops immediately and freezes operation register values state machines and external pins During this mode the FEC clocks are shut down Coming out of stop mode returns the FEC to operation f...

Page 179: ...ecovery time and stop mode power The PLL may be disabled during stop mode A wakeup time of up to 200 µs is required for the PLL to re lock The OSC may also be disabled during stop mode The time required for the OSC to restart is dependent upon the startup time of the crystal used Power consumption can be reduced in stop mode by disabling either or both of these functions via the SYNCR STMPD bits T...

Page 180: ... low power modes 7 3 2 20 Programmable Interrupt Timers PIT0 PIT1 PIT2 and PIT3 In stop mode or in doze mode if so programmed the programmable interrupt timer PIT ceases operation and freezes at the current value When exiting these modes the PIT resumes operation from the stopped value It is the responsibility of software to avoid erroneous operation When not stopped the PIT may generate an interr...

Page 181: ...35 interrupt sources 32 sources due to message buffers and 3 sources due to Bus off Error and Wake up When in stop mode a recessive to dominant transition on the CAN bus causes the WAKE INT bit in the error status register to be set This event can cause a CPU interrupt if the WAKE MASK bit in module configuration register MCR is set When setting stop mode in the FlexCAN by setting the MCR STOP bit...

Page 182: ...bit to be set The correct flow to negate STOP with SELF WAKE negate SELF WAKE at the same time as STOP wait for STOP_ACK negation SELF WAKE should be set only when the MCR STOP bit is negated and the FlexCAN is ready that is the NOT_RDY bit in the MCR is negated If STOP and SELF_WAKE are set and if a recessive to dominant edge immediately follows on the CAN bus the STOP_ACK bit in the MCR may neve...

Page 183: ...e FlexCAN module The FlexCAN is neither in halt mode MCR bit 8 in stop mode MCT bit 15 nor in BUSOFF 7 3 2 24 ColdFire Flash Module The ColdFire Flash Control Module is capable of generating interrupts by the setting of the CBEIF or CCIF bits in the CFMUSTAT These interrupt sources however should not occur when the device is in a low power mode as long as no Flash operation was in progress when th...

Page 184: ...dividual peripherals may be disabled by programming its dedicated control bits The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode Table 7 7 CPU and Peripherals in Low Power Modes Module Peripheral Status 1 Wakeup Capability Wait Mode Doze Mode Stop Mode CPU Stopped No Stopped No Stopped No SRAM Stopped No Stopped No Stopped ...

Page 185: ...M Enabled Yes 4 Enabled Yes4 Enabled Yes4 JTAG Enabled No Enabled No Enabled No 1 Program Indicates that the peripheral function during the low power mode is dependent on programmable bits in the peripheral register map 2 These modules can generate a interrupt which will exit a low power mode The CPU will begin to service the interrupt exception after wakeup 3 These modules can generate a reset wh...

Page 186: ...7 18 MCF5282 User s Manual MOTOROLA Functional Description ...

Page 187: ...and the ColdFire core memory spaces RAMBAR The MCF5282 CPU core supports two memory banks one for the internal SRAM and the other for the internal Flash The SACU provides the mechanism needed to implement secure bus transactions to the system address space The programming model for the system bus arbitration resides in the SCM The SCM sources the necessary control signals to the arbiter for bus ma...

Page 188: ...0 GPACR1 8 3 Memory Map and Register Definition The memory map for the SCM registers is shown in Table 8 1 All the registers in the SCM are memory mapped as offsets within the 1 Gbyte IPS address space and accesses are controlled to these registers by the control definitions programmed into the SACU Table 8 1 SCM Register Map IPSBAR Offset 31 24 23 16 15 8 7 0 0x00_0000 IPSBAR 0x00_0004 0x00_0008 ...

Page 189: ... by loading a different value into the IPSBAR at a later time NOTE Accessing reserved IPSBAR memory space could result in an unterminated bus cycle that causes the core to hang Only a hard reset will allow the core to recover from this state Therefore all bus accesses to IPSBAR space should fall within a module s memory map space If an address hits in overlapping memory regions the following prior...

Page 190: ...eats with the processor and the DMA ping ponging between alternate regions of the dual ported SRAM The MCF5282 design implements the dual ported SRAM in the memory space defined by the RAMBAR register There are two physical copies of the RAMBAR register one located in the processor core and accessible only via the privileged MOVEC instruction at CPU space address 0xC05 and another located in the S...

Page 191: ...ss the on chip SRAM see Chapter 5 Static RAM SRAM for more information 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 Reset 0000_0000_0000_0000 R W R W 15 10 9 8 0 Field BDE Reset 0000_0000_0000_0000 R W R W Address IPSBAR 0x008 Figure 8 2 Memory Base Address Register RAMBAR Table 8 3 RAMBAR Field Description Bi...

Page 192: ... Register CWCR The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit The core watchdog timer can be enabled or disabled through CWCR CWE By default it is disabled If enabled the watchdog timer requires the 7 6 5 4 0 Field EXT CWDR Reset See Note R W R W Address IPSBAR 0x010 Note The reset value of EXT and CWDR depend on the last reset sour...

Page 193: ...ernal reset is asserted and CRSR CWDR is set To prevent the core watchdog timer from interrupting or resetting the CWSR must be serviced by performing the following sequence 1 Write 0x55 to CWSR 2 Write 0xAA to the CWSR Both writes must occur in order before the time out but any number of instructions can be executed between the two writes This order allows interrupts and exceptions to occur if ne...

Page 194: ... period but the watchdog is disabled CWCR CWE 0 2 CWTA Core watchdog transfer acknowledge enable 0 CWTA Transfer acknowledge disabled 1 CWTA Transfer Acknowledge enabled After one CWT time out period of the unacknowledged assertion of the CWT interrupt the transfer acknowledge asserts which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to occur 1 CWTAVAL Core watchdog tra...

Page 195: ... to the CWSR can be executed between the two writes If the CWT has already timed out writing to this register has no effect in negating the CWT interrupt Figure 8 5 illustrates the CWSR At system reset the contents of CWSR are uninitialized 8 5 Internal Bus Arbitration The internal bus arbitration is performed by the on chip bus arbiter which containing the arbitration logic that controls which of...

Page 196: ...282 User s Manual MOTOROLA Internal Bus Arbitration Figure 8 6 Arbiter Module Functions SRAM1 MPARK RAMBAR CPU M0 DMA M2 Internal M1 Bus Master FEC M3 EIM Internal MARB Modules SDRAMC back door to SRAM and Flash ...

Page 197: ...e arbitration pointer to the highest priority requester calculated by adding a requester s fixed priority to the current bus master s fixed priority and then taking this sum modulo the number of possible bus masters The default priority is FEC M3 DMA M2 internal master M1 CPU M0 where M3 is the highest and M0 the lowest priority There are two actions for an idle arbitration cycle either leave the ...

Page 198: ... set by MPARK LCKOUT_TIME the arbitration algorithm will be changed to round robin arbitration mode until all locks are cleared The arbitration will then return to fixed mode and the highest priority master will be granted the bus As in round robin mode if no masters are requesting the arbitration pointer will park on the highest priority master if MPARK PRK_LAST is set or will park on the master ...

Page 199: ...rity 21 20 M2_PRTY Master priority level for master 2 DMA Controller 00 fourth lowest priority 01 third priority 10 second priority 11 first highest priority 19 18 M0_PRTY Master priority level for master 0 ColdFire Core 00 fourth lowest priority 01 third priority 10 second priority 11 first highest priority 17 16 M1_PRTY Master priority level for master 1 Not used in user mode 00 fourth lowest pr...

Page 200: ...ister defines the privilege level associated with each bus master and another set of control registers define the access levels associated with the peripheral modules and the memory space The SACU s programming model is physically implemented as part of the System Control Module SCM with the actual access control logic included as part of the arbitration controller Each bus transaction targeted fo...

Page 201: ... support the concept of a trusted bus master and also controls the ability of a bus master to modify the register state of any of the SACU control registers that is only trusted masters can modify the control registers Peripheral access control registers PACRs Nine 8 bit registers control access to 17 of the on chip peripheral modules Provides read write access rights supervisor user privilege lev...

Page 202: ...0 and is always treated as a trusted bus master Accordingly MPR 0 is forced to 1 at reset 8 6 3 2 Peripheral Access Control Registers PACR 0 PACR8 Access to several on chip peripherals is controlled by shared peripheral access control registers A single PACR defines the access level for each of the two modules These 0x028 PACR4 PACR5 PACR6 0x02c PACR7 PACR8 0x030 GPACR0 GPACR1 0x034 0x038 0x03C 7 ...

Page 203: ...it field defines the access control for the given platform peripheral The encodings for this field are shown in Table 8 11 3 LOCK0 This bit when set prevents subsequent writes to ACCESSCTRL0 Any attempted write to the PACR generates an error termination and the contents of the register are not affected Only a system reset clears this flag 2 0 ACCESS_CTRL0 This 3 bit field defines the access contro...

Page 204: ...ts 29 26 of the address select the specific GPACRn to be used for a given reference within the IPS address space These access control registers are 8 bits in width so that read write and execute attributes may be assigned to the given IPS region NOTE The access control for modules with memory space protected by PACR0 PACR8 are determined by the PACR0 PACR8 settings The access control is not affect...

Page 205: ... termination and the contents of the register are not affected Only a system reset clears this flag 6 4 Reserved should be cleared 3 0 ACCESS_CTRL This 4 bit field defines the access control for the given memory region The encodings for this field are shown in Table 8 14 Table 8 14 GPACR ACCESS_CTRL Bit Encodings Bits Supervisor Mode User Mode 0000 Read Write No Access 0001 Read No Access 0010 Rea...

Page 206: ...ster Space Protected IPSBAR Offset Modules Protected GPACR0 0x0000_0000 0x03FF_FFFF Ports CCM PMM Reset controller Clock EPORT WDOG PIT0 PIT3 QADC GPTA GPTB FlexCAN CFM Control GPACR1 0x0400_0000 0x07FF_FFFF CFM Flash module s backdoor access for programming or access by a bus master other than the core ...

Page 207: ...r OSC Phase locked loop PLL Reduced frequency divider RFD Status and control registers Control logic 9 1 Features Features of the clock module include 2 to 10 MHz reference crystal oscillator Support for low power modes Separate clock out signal 9 2 Modes of Operation The clock module can be operated in normal PLL mode default 1 1 PLL mode or external clock mode 9 2 1 Normal PLL Mode In normal PLL...

Page 208: ...emory In wait and doze modes the system clocks to the peripherals are enabled and the clocks to the CPU Flash and SRAM are stopped Each module can disable its clock locally at the module level In stop mode all system clocks are disabled There are several options for enabling or disabling the PLL or crystal oscillator in stop mode compromising between stop mode current and wakeup recovery time The ...

Page 209: ...s one before entering stop mode In external clock mode there are no wakeup periods for oscillator startup or PLL lock 9 4 Block Diagram Figure shows a block diagram of the entire clock module The PLL block in this diagram is expanded in detail in Figure 9 2 Figure 9 1 Clock Module Block Diagram CLKOUT XTAL EXTERNAL CLOCK OSC PLLREF REFERENCE CLOCK PLL MFD PLLMODE LOCEN CLKMOD 1 0 RSTOUT CLKOUT LOC...

Page 210: ...s a connection to the external crystal when using the internal oscillator Table 9 2 Signal Properties Name Function EXTAL Oscillator or clock input XTAL Oscillator output CLKOUT System clock output CLKMOD 1 0 Clock mode select inputs RSTOUT Reset signal from reset controller STPMD CLKMOD 1 0 RSTOUT MFD 4 18 LOCKS LOCK LOCS TO RESET MODULE CLKOUT PLLSEL DISCLK MDF 2 0 PHASE AND FREQUENCY DETECT LOS...

Page 211: ... system reset signal FRCRSTOUT bit in the reset control status register RCR see Section 28 4 1 Reset Control Register RCR 9 6 Memory Map and Registers The clock module programming model consists of these registers Synthesizer control register SYNCR which defines clock operation Synthesizer status register SYNSR which reflects clock status 9 6 1 Module Memory Map Table 9 3 Clock Module Memory Map I...

Page 212: ...AR 0x0012_0000 Figure 9 3 Synthesizer Control Register SYNCR Table 9 4 SYNCR Field Descriptions Bit s Name Description 15 LOLRE Loss of lock reset enable Determines how the system handles a loss of lock indication When operating in normal mode or 1 1 PLL mode the PLL must be locked before setting the LOLRE bit Otherwise reset is immediately asserted To prevent an immediate reset the LOLRE bit must...

Page 213: ...2 0 does not affect the PLL or cause a relock delay Changes in clock frequency are synchronized to the next falling edge of the current system clock To avoid surpassing the allowable system operating frequency write to RFD 2 0 only when the LOCK bit is set 7 LOCEN Enables the loss of clock function LOCEN does not affect the loss of lock function 1 Loss of clock function enabled 0 Loss of clock fun...

Page 214: ...n the clock that was lost In external clock mode the FWKUP bit has no effect on the wakeup sequence 4 Reserved should be cleared 3 2 STPMD Control PLL and CLKOUT operation in stop mode The following table illustrates STPMD operation in stop mode 1 0 Reserved should be cleared 7 6 5 4 3 2 1 0 Field PLLMODE PLLSEL PLLREF LOCKS LOCK LOCS Reset See note 1 See note 2 000 R W R Address IPSBAR 0x0012_000...

Page 215: ...k LOCKS is cleared When the PLL relocks LOCKS remains cleared until one of the two listed events occurs In stop mode if the PLL is intentionally disabled then the LOCKS bit reflects the value prior to entering stop mode However if FWKUP is set then LOCKS is cleared until the PLL regains lock Once lock is regained the LOCKS bit reflects the value prior to entering stop mode Furthermore reading the ...

Page 216: ...cks have failed due to a reference failure or PLL failure After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled STPMD 1 0 11 the PLL exits stop mode in the SCM while the oscillator starts up During this time LOCS is temporarily set regardless of LOCEN It is cleared once the oscillator comes up and the PLL is attempting to lock If a read of the LOCS flag and a lo...

Page 217: ... is asserted the system cannot enter reset unless the PLL is capable of operating in SCM 9 7 3 System Clock Generation In normal PLL clock mode the default system frequency is two times the reference frequency after reset The RFD 2 0 and MFD 2 0 bits in the SYNCR select the frequency multiplier When programming the PLL do not exceed the maximum system clock frequency listed in the electrical speci...

Page 218: ...frequencies of 4 MHz to 18 MHz In addition the RFD can reduce the system frequency by dividing the output of the PLL The RFD is not in the feedback loop of the PLL so changing the RFD divisor does not affect PLL operation Figure 9 5 shows the external support circuitry for the crystal oscillator with example component values Actual component values depend on crystal specifications The following su...

Page 219: ...e the charge pump uses a fixed current In normal mode the current magnitude of the charge pump varies with the MFD as shown in Table 9 8 The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge respectively from the loop filter The filter is integrated on the chip 9 7 4 3 Voltage Control Output VCO The voltage across the loop filter controls the frequency of t...

Page 220: ...the feedback counter If the feedback counter has also counted N cycles the process is repeated for N K counts Then if the two counters still match the lock criteria is relaxed by 1 2 and the system is notified that the PLL has achieved frequency lock After lock is detected the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process If ...

Page 221: ...p mode then after exit from stop mode the LOCKS flag reflects the value prior to entering stop mode once lock is regained 9 7 4 7 PLL Loss of Lock Reset If the LOLRE bit in the SYNCR is set a loss of lock condition asserts reset Reset reinitializes the LOCK and LOCKS flags Therefore software must read the LOL bit in the reset status register RSR to determine if a loss of lock caused the reset See ...

Page 222: ... initializes the clock module registers to a known startup state as described in Section 9 6 Memory Map and Registers 9 7 4 10 Alternate Clock Selection Depending on which clock source fails the loss of clock circuit switches the system clocks source to the remaining operational clock The alternate clock source generates the system clocks until reset is asserted As Table 9 9 shows if the reference...

Page 223: ...clock in Stop Mode when the device is being clocked by the various clocking methods Table 9 10 Stop Mode Operation Sheet 1 of 5 MODE In LOCEN LOCRE LOLRE PLL OSC FWKUP Expected PLL Action at Stop PLL Action During Stop MODE Out LOCKSS LOCK LOCS Comments EXT X X X X X X EXT 0 0 0 Lose reference clock Stuck NRM 0 0 0 Off Off 0 Lose lock f b clock reference clock Regain NRM LK 1 LC No regain Stuck NR...

Page 224: ...LOCEN 0 NRM 0 0 0 On On 0 NRM LK 1 LC Lose lock or clock Stuck Lose lock regain NRM 0 1 LC Lose clock and lock regain NRM 0 1 LC LOCS not set because LOCEN 0 NRM 0 0 0 On On 1 NRM LK 1 LC Lose lock Unstable NRM 0 0 1 LC Lose lock regain NRM 0 1 LC Lose clock Stuck Lose clock regain without lock Unstable NRM 0 0 1 LC Lose clock regain with lock NRM 0 1 LC NRM X X 1 Off X X Lose lock f b clock refer...

Page 225: ...0 1 LC REF mode not entered during stop No f b clock regain Stuck Lose reference clock SCM 0 0 1 Wakeup without lock NRM 1 0 0 On On 0 NRM LK 1 LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f b clock REF 0 X 1 Wakeup without lock Lose lock Stuck Lose lock regain NRM 0 1 LC NRM 1 0 0 On On 1 NRM LK 1 LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f b clock REF 0 X 1 Wakeup ...

Page 226: ...e NRM 0 0 1 LC Lose lock regain NRM 0 1 LC NRM 1 1 1 On On X NRM LK 1 LC Lose clock or lock RESET Reset immediately REF 1 0 0 X X X REF 0 X 1 Lose reference clock Stuck SCM 1 0 0 Off X 0 PLL disabled Regain SCM SCM 0 0 1 Wakeup without lock SCM 1 0 0 Off X 1 PLL disabled Regain SCM SCM 0 0 1 SCM 1 0 0 On On 0 SCM 0 0 1 Wakeup without lock Lose reference clock SCM Table 9 10 Stop Mode Operation She...

Page 227: ...lock or lock from NRM mode SCM PLL self clocked mode due to losing reference clock from NRM mode RESET immediate reset LOCKS LK expecting previous value of LOCKS before entering stop 0 LK current value is 0 until lock is regained which then will be the previous value before entering stop 0 current value is 0 until lock is regained but lock is never expected to regain LOCS LC expecting previous val...

Page 228: ...9 22 MCF5282 User s Manual MOTOROLA Functional Description ...

Page 229: ...are mapped to the interrupt controller logic and how interrupts are serviced 10 1 68K ColdFire Interrupt Architecture Overview Before continuing with the specifics of the MCF5282 interrupt controllers a brief review of the interrupt architecture of the 68K ColdFire family is appropriate The interrupt architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded i...

Page 230: ... format After the exception stack frame is stored in memory the processor accesses the 32 bit pointer from the exception vector table using the vector number as the offset and then jumps to that address to begin execution of the service routine After the status register is stored in the exception stack frame the SR I mask field is set to the level of the interrupt being acknowledged effectively ma...

Page 231: ...vel and represents the mid point of the priority within the level For the fully programmable interrupt sources the 3 bit level and the 3 bit priority within the level are defined in the 8 bit interrupt control register ICRnx The operation of the interrupt controller can be broadly partitioned into three activities Recognition Prioritization Vector Determination during IACK 10 1 1 1 Interrupt Recog...

Page 232: ...bers 0 63 are reserved for the ColdFire processor and its internal exceptions Thus the following mapping of bit positions to vector numbers applies for the INTC0 if interrupt source 1 is active and acknowledged then vector_number 65 if interrupt source 2 is active and acknowledged then vector_number 66 if interrupt source 8 is active and acknowledged then vector_number 72 if interrupt source 9 is ...

Page 233: ...resses Interrupt Controller Number Base Address INTC0 IPSBAR 0xC00 INTC1 IPSBAR 0xD00 Global IACK Registers Space 1 1 This address space only contains the SWIACK and L1ACK L7IACK registers See Section 10 3 7 Software and Level n IACK Registers SWIACKR L1IACK L7IACK for more information IPSBAR 0xF00 Table 10 3 Interrupt Controller Memory Map Module Offset Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 0x...

Page 234: ...he IPRn is a read only register so any attempted write to this register is ignored Bit 0 is not implemented and reads as a zero 0x60 ICR32 ICR33 ICR34 ICR35 0x64 ICR36 ICR37 ICR38 ICR39 0x68 ICR40 ICR41 ICR42 ICR43 0x6C ICR44 ICR45 ICR46 ICR47 0x70 ICR48 ICR49 ICR50 ICR51 0x74 ICR52 ICR53 ICR54 ICR55 0x78 ICR56 ICR57 ICR58 ICR59 0x7C ICR60 ICR61 ICR62 ICR63 0x80 0xDC Reserved 0xE0 SWIACK Reserved ...

Page 235: ...responding interrupt source does not have an interrupt pending 1 The corresponding interrupt source has an interrupt pending 31 16 Field INT 31 16 Reset 0000_0000_0000_0000 R W R 15 1 0 Field INT 16 1 Reset 0000_0000_0000_0000 R W R IPSBAR 0xC04 0xD04 Figure 10 2 Interrupt Pending Register Low IPRLn Table 10 5 IPRLn Field Descriptions Bits Name Description 31 1 INT Interrupt Pending Each bit corre...

Page 236: ..._1111 R W R W 15 0 Field INT_MASK 47 32 Reset 1111_1111_1111_1111 R W R W IPSBAR 0xC08 0xD08 Figure 10 3 Interrupt Mask Register High IMRHn Table 10 6 IMRHn Field Descriptions Bits Name Description 31 0 INT_MASK Interrupt mask Each bit corresponds to an interrupt source The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt The corresponding IPRHn bit refle...

Page 237: ...errupt source The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked 0 MASKALL Mask all interrupts Setting this bit will force the other 63 bits of...

Page 238: ...PSBAR 0xC14 0xD14 Figure 10 6 Interrupt Force Register Low INTFRCLn Table 10 9 INTFRCLn Field Descriptions Bits Name Description 31 1 INTFRC Interrupt force Allows software generation of interrupts for each possible source for functional or debug purposes 0 No interrupt forced on corresponding interrupt source 1 Force an interrupt on the corresponding source 0 Reserved should be cleared 7 2 1 0 Fi...

Page 239: ...the priority within the level 0 7 All ICRnx registers can be read but only ICRn8 to ICRn63 can be written It is software s responsibility to program the ICRnx registers with unique and non overlapping level and priority definitions Failure to program the ICRnx registers in this manner can result in undefined behavior If a specific interrupt request is completely unused the ICRnx value can remain i...

Page 240: ...rrupt sources the priority is fixed at the midpoint for the level and the IP field will always read as 000b Table 10 13 Interrupt Source Assignment for INTC0 Source Module Flag Source Description Flag Clearing Mechanism 1 EPORT EPF1 Edge port flag 1 Write EPF1 1 2 EPF2 Edge port flag 2 Write EPF2 1 3 EPF3 Edge port flag 3 Write EPF3 1 4 EPF4 Edge port flag 4 Write EPF4 1 5 EPF5 Edge port flag 5 Wr...

Page 241: ...Graceful stop complete Write GRA 1 33 EBERR Ethernet bus error Write EBERR 1 34 BABT Babbling transmit error Write BABT 1 35 BABR Babbling receive error Write BABR 1 36 PMM LVDF LVD Write LVDF 1 37 QADC CF1 Queue 1 conversion complete Write CF1 0 after reading CF1 1 38 CF2 Queue 2 conversion complete Write CF2 0 after reading CF2 1 39 PF1 Queue 1 conversion pause Write PF1 0 after reading PF1 1 40...

Page 242: ...ss IC OC if TFFCA 1 54 C3F Timer channel 3 Write C3F 1 or access IC OC if TFFCA 1 55 PIT0 PIF PIT interrupt flag Write PIF 1 of write PMR 56 PIT1 PIF PIT interrupt flag Write PIF 1 of write PMR 57 PIT2 PIF PIT interrupt flag Write PIF 1 of write PMR 58 PIT3 PIF PIT interrupt flag Write PIF 1 of write PMR 59 CFM CBEIF SGFM buffer empty Write CBEIF 1 60 CFM CCIF SGFM command complete Cleared automat...

Page 243: ...ge buffer 0 interrupt Write BUF0I 1 after reading BUF0I 1 9 BUF1I Message buffer 1 interrupt Write BUF1I 1 after reading BUF1I 1 10 BUF2I Message buffer 2 interrupt Write BUF2I 1 after reading BUF2I 1 11 BUF3I Message buffer 3 interrupt Write BUF3I 1 after reading BUF3I 1 12 BUF4I Message buffer 4 interrupt Write BUF4I 1 after reading BUF4I 1 13 BUF5I Message buffer 5 interrupt Write BUF5I 1 after...

Page 244: ...sters within each interrupt controller there are global software IACK registers A read from the global SWIACK will return the vector number for the highest level and priority unmasked interrupt source from all interrupt controllers A read from one of the LnIACK registers will return the vector for the highest priority unmasked interrupt within a level for all interrupt controllers 10 4 Prioritizat...

Page 245: ... NOTE The wakeup mask level taken from LPICR 6 4 is adjusted by hardware to allow a level 7 IRQ to generate a wakeup That is the wakeup mask value used by the interrupt controller must be in the range of 0 6 Second the processor executes a STOP instruction which places it in stop mode Once the processor is stopped each interrupt controller enables a special logic path which evaluates the incoming ...

Page 246: ...10 18 MCF5282 User s Manual MOTOROLA Low Power Wakeup Operation ...

Page 247: ...input output I O pin See Figure 11 1 Figure 11 1 EPORT Block Diagram 11 2 Low Power Mode Operation This section describes the operation of the EPORT module in low power modes For more information on low power modes see Chapter 7 Power Management Table 11 1 shows EPORT module operation in low power modes and describes how this module may exit from each mode IPBUS Synchronizer EPDR n EPFR n EPPAR 2n...

Page 248: ...r is bypassed for the level detect logic since no clocks are available 11 3 Interrupt General Purpose I O Pin Descriptions All pins default to general purpose input pins at reset The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register EPPDR The values used in the edge level detect logic are also synchronized to the rising edge of CLKOUT These pins use ...

Page 249: ...for each pin individually The EPORT data register EPDR holds the data to be driven to the pins The EPORT pin data register EPPDR reflects the current state of the pins The EPORT flag register EPFR individually latches EPORT edge events Table 11 2 Edge Port Module Memory Map IPSBAR Offset Bits 15 8 Bits 7 0 Access 1 1 S CPU supervisor mode access only S U CPU supervisor or user mode access User mod...

Page 250: ...sensitive interrupt request is acknowledged the interrupt source must keep the signal asserted until acknowledged by software Level sensitivity must be selected to bring the device out of stop mode with an IRQx interrupt Pins configured as edge triggered are latched and need not remain asserted for interrupt generation A pin configured for edge detection can trigger an interrupt regardless of its ...

Page 251: ... Reserved should be cleared 7 6 5 4 3 2 1 0 Field EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 Reset 0000_0000 R W R W R Address IPSBAR 0x0013_0003 Figure 11 4 EPORT Port Interrupt Enable Register EPIER Table 11 5 EPIER Field Descriptions Bit s Name Description 7 1 EPIEx Edge port interrupt enable bits enable EPORT interrupt requests If a bit in EPIER is set EPORT generates an interrupt request when ...

Page 252: ...7 EPD1 0 Reserved should be cleared 7 6 5 4 3 2 1 0 Field EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1 Reset Current pin state 0 R W R Address IPSBAR 0x0013_0005 Figure 11 6 EPORT Port Pin Data Register EPPDR Table 11 7 EPPDR Field Descriptions Bit s Name Description 7 1 EPPDx Edge port pin data bits The read only EPPDR reflects the current state of the EPORT pins IRQ7 IRQ1 Writing to EPPDR has no ef...

Page 253: ...cates that the selected edge has been detected Reset clears EPF7 EPF1 Bits in this register are set when the selected edge is detected on the corresponding pin A bit remains set until cleared by writing a 1 to it Writing 0 has no effect If a pin is configured as level sensitive EPPARx 00 pin transitions do not affect this register 1 Selected edge for IRQx pin has been detected 0 Selected edge for ...

Page 254: ...11 8 MCF5282 User s Manual MOTOROLA Memory Map and Registers ...

Page 255: ...ach CSn can be independently programmed for an address location as well as for masking port size read write burst capability wait state generation and internal external termination Only CS0 is initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external address space Port size for CS0 is configured by the logic levels of D 19 18 when RSTO negates and RCON...

Page 256: ...0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 1 32 bit 0 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 Word 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 0 1 1 1 0 0 0 1 1 32 bit 0 0 0 0 1 1 1 0 1 1 0 0 Longword 8 bit 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 16 bit 0 0 0 0 1 1 1 0 0 0 1 1 32 bit 0 0 0 0 0 0 Line 8 b...

Page 257: ...ess and mask configurations programmed for chip selects 0 6 configured in CSCR0 CSCR6 and DRAM blocks 0 and 1 configured in DACR0 and DACR1 If the driven address matches a programmed chip select or DRAM block the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register Otherwise the following occurs If the addres...

Page 258: ...ts operation differs from other external chip select outputs after system reset After system reset CS0 is asserted for every external access No other chip select can be used until the valid bit CSMR0 V is set at which point CS0 functions as configured and Table 12 3 Accesses by Matches in CSARs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSAR ...

Page 259: ...ernal Boot Chip Select Configuration D 19 18 Boot Device Data Port Size 00 Internal 32 bit 01 External 16 bit 10 External 8 bit 11 External 32 bit Table 12 5 Chip Select Registers IPSBAR Offset 31 24 23 16 15 8 7 0 0x00_0080 Chip select address register bank 0 CSAR0 p 12 6 Reserved 1 0x00_0084 Chip select mask register bank 0 CSMR0 p 12 7 0x00_0088 Reserved1 Chip select control register bank 0 CSC...

Page 260: ...ter bank 4 CSCR4 p 12 8 0x00_00BC Chip select address register bank 5 CSAR5 p 12 6 Reserved1 0x00_00C0 Chip select mask register bank 5 CSMR5 p 12 7 0x00_00C4 Reserved1 Chip select control register bank 5 CSCR5 p 12 8 0x00_00C8 Chip select address register bank 6 CSAR6 p 12 6 Reserved1 0x00_00CC Chip select mask register bank 6 CSMR6 p 12 7 0x00_00D0 Reserved1 Chip select control register bank 6 C...

Page 261: ...etting a BAM bit causes the corresponding CSAR bit to be ignored in the decode 0 Corresponding address bit is used in chip select decode 1 Corresponding address bit is a don t care in chip select decode The block size for CS 6 0 is 2n where n number of bits set in respective CSMR BAM 16 So if CSAR0 0x0000 and CSMR0 BAM 0x0008 CS0 addresses a 128 Kbyte 217 byte range from 0x0000 0x1_FFFF Likewise f...

Page 262: ...r code address space mask UD User data address space mask 0 The address space assigned to this chip select is available to the specified access type 1 The address space assigned to this chip select is not available masked to the specified access type If this address space is accessed chip select is not activated and a regular external bus cycle occurs Note that if AM 0 SC SD UC and UD are ignored ...

Page 263: ...32 bit port size Valid data sampled and driven on D 31 0 01 8 bit port size Valid data sampled and driven on D 31 24 1x 16 bit port size Valid data sampled and driven on D 31 16 5 BEM Byte enable mode Specifies the byte enable operation Certain SRAMs have byte enables that must be asserted during reads as well as writes BEM can be set in the relevant CSCR to provide the appropriate mode of byte en...

Page 264: ...12 10 MCF5282 User s Manual MOTOROLA Chip Select Registers ...

Page 265: ...its of address and 32 bits of data Access 8 16 and 32 bit data port sizes Generates byte word longword and line size transfers Burst and burst inhibited transfer support Optional internal termination for external bus cycles 13 2 Bus and Control Signals Table 13 1 summarizes MCF5282 bus signals described in Chapter 14 Signal Descriptions Table 13 1 ColdFire Bus Signal Summary Signal Name Descriptio...

Page 266: ...nd other devices involve the following signals Address bus A 23 0 Data bus D 31 0 Control signals TS and TA CSn OE BS Attribute signals R W SIZ and TIP TA Transfer acknowledge I Rising TIP Transfer in progress O Rising TS Transfer start O Rising 1 These signals change after the falling edge In the Electrical Specifications these signals are specified off of the rising edge because CLKIN is squared...

Page 267: ... connected to D 31 24 BS3 A longword transfer takes four transfers on D 31 24 starting with the MSB and going to the LSB Figure 13 2 Connections for External Memory Port Sizes The timing relationship of chip selects CS 7 0 byte selects BS 3 0 and output enable OE with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT However due to differences in on chip sig...

Page 268: ...ess as a function of match in the CSCRs and DACRs Basic operation of the MCF5282 bus is a three clock bus cycle 1 During the first clock the address attributes and TS are driven 2 Data and TA are sampled during the second clock of a bus read cycle During a read the external device provides data and is sampled at the rising edge at the end of the second bus clock This data is concurrent with TA whi...

Page 269: ...es as they appear in subsequent timing diagrams Table 13 3 Bus Cycle States State Cycle CLKOUT Description S0 All High The read or write cycle is initiated in S0 On the rising edge of CLKOUT the MCF5282 places a valid address on the address bus and drives R W high for a read and low for a write if it is not already in the appropriate state The MCF5282 asserts TIP SIZ 1 0 and TS on the rising edge ...

Page 270: ... the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted S4 All High The external device should negate TA Read including fast terminat ion The external device can stop driving data after the rising edge of CLKOUT However data could be driven through the end of S5 S5 S5 Low CS BS and OE are negated on the CLKOUT falling edge of S5 The MCF5282 stops driving address li...

Page 271: ...Read Bus Cycle Note the following characteristics of a basic read In S3 data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted System 1 Set R W to read 2 Place address on A 31 0 3 Assert TIP and SIZ 1 0 4 Assert TS 5 Negate TS 1 Decode address and select the appropriate slave device 2 Drive data on D 31 0 3 Assert TA...

Page 272: ...ral device The write cycle flowchart is shown in Figure 13 7 Figure 13 7 Write Cycle Flowchart The write cycle timing diagram is shown in Figure 13 8 Figure 13 8 Basic Write Bus Cycle Table 13 3 describes the six states of a basic write cycle System 1 Set R W to write 2 Place address on A 31 0 3 Assert TIP and SIZ 1 0 4 Assert TS 5 Place data on D 31 0 6 Negate TS 1 Decode address 2 Store data on ...

Page 273: ... Fast termination cycles occur when the external device or memory asserts TA less than one clock after TS is asserted This means that the MCF5282 samples TA on the rising edge of the second cycle of the bus transfer Figure 13 9 shows a read cycle with fast termination Note that fast termination cannot be used with internal termination Figure 13 9 Read Cycle with Fast Termination Figure 13 10 shows...

Page 274: ... cycles if its transfer size exceeds the size of the port it is transferring to For example a word transfer to an 8 bit port would take a 2 byte burst cycle A line transfer to a 32 bit port would take a 4 longword burst cycle The MCF5282 bus can support 2 1 1 1 burst cycles to maximize cache performance and optimize DMA transfers A user can add wait states by delaying termination of the cycle The ...

Page 275: ...cess read with zero wait states The access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of S4 but the next pipelined burst data is sampled a cycle later on the rising edge of S6 Each subsequent pipelined data burst is single cycle until the last one which can be held for up to two CLKOUT cycles after TA is asserted Note that CSn are asserted throughout...

Page 276: ... the exception of an added wait state Figure 13 14 Line Read Burst 3 2 2 2 External Termination Figure 13 15 shows a burst inhibited line read access with fast termination The external device executes a basic read cycle while determining that a line is being transferred The external device uses fast termination for subsequent transfers R W TIP TS CSn BSn OE D 31 0 TA Read Read S0 S1 S2 S3 S4 S5 S1...

Page 277: ...line read example in Figure 13 12 CSn remain asserted throughout the burst transfer This example shows the behavior of the address lines for both internal and external termination Note that when external termination is used the address lines change with SIZ 1 0 Figure 13 16 Line Write Burst 2 1 1 1 Internal External Termination A 31 0 R W TIP SIZ 1 0 TS D 31 0 TA Line Longword Basic Fast Fast Fast...

Page 278: ...ch subsequent transfer Figure 13 18 Line Write Burst Inhibited 13 5 Misaligned Operands Because operands can reside at any byte boundary unlike opcodes they are allowed to be misaligned A byte operand is properly aligned at any address a word operand is A 31 0 R W TIP TS CSn OE BSn D 31 0 TA Write Write Write Write S0 S1 S2 S3 S4 S5 S10 S9 S8 S7 S6 S11 WS WS WS WS CLKOUT SIZ 1 0 A 31 0 R W TIP SIZ...

Page 279: ... a byte transfer and a byte offset of 0x1 The slave device supplies the byte and acknowledges the data transfer When the MCF5282 starts the second cycle SIZ 1 0 specify a word transfer with a byte offset of 0x2 The next two bytes are transferred in this cycle In the third cycle byte 3 is transferred The byte offset is now 0x0 the port supplies the final byte and the operation is complete Figure 13...

Page 280: ...13 16 MCF5282 User s Manual MOTOROLA Misaligned Operands ...

Page 281: ...pter 13 External Interface Module EIM describes how these signals interact NOTE The terms assertion and negation are used to avoid confusion when dealing with a mixture of active low and active high signals The term asserted indicates that a signal is active independent of the voltage level The term negated indicates that a signal is inactive Active low signals such as SRAS and TA are indicated wi...

Page 282: ...ebug Module DIV Clock Module Chip Configuration Reset Controller Power RCON CLKMOD0 CLKMOD1 RSTI RSTO PLL Edgeport Interrupt Controller 0 Interrupt Controller 1 IRQ 7 1 FEC UART0 Serial I O DMA Controller Watchdog Timer General Purpose Timer A General Purpose Timer B QSPI FlexCAN QADC PIT Timers PIT0 JTAG_EN CLKOUT XTAL ETXCLK ETXEN ETXDO ECOL ERXCLK ERXDV ERXD0 ECRS ETXD 3 1 ETXER ERXD 3 1 ERXER ...

Page 283: ...tes that the external data transfer is complete and should be asserted for one clock I 14 19 Transfer error acknowledge TEA Indicates that an error condition exists for the bus transfer I 14 19 Read Write R W Indicates the direction of the data transfer on the bus I O 14 19 Transfer size SIZ 1 0 Specify the data access size of the current external bus reference O 14 19 Transfer start TS Asserted d...

Page 284: ...ock O 14 22 Chip Configuration Module Clock mode CLKMOD 1 0 Clock mode select I 14 22 Reset configuration RCON Reset configuration select I 14 22 External Interrupt Signals External interrupts IRQ 7 1 External interrupt sources I 14 23 Ethernet Module Signals Management data EMDIO Transfers control information between the external PHY and the media access controller I O 14 23 Management data clock...

Page 285: ...rted with ERXDV that the PHY has detected an error in the current frame I 14 25 Queued Serial Peripheral Interface QSPI Signals QSPI synchronous serial data output QSPI_DOUT Provides serial data from the QSPI O 14 25 QSPI synchronous serial data input QSPI_DIN Provides serial data to the QSPI I 14 25 QSPI serial clock QSPI_CLK Provides the serial clock from the QSPI O 14 25 QSPI chip selects QSPI_...

Page 286: ...DC analog input AN 52 53 MA 0 1 Direct analog input ANn or multiplexed output MAn MAn selects the output of the external multiplexer I O 14 29 QADC analog input AN 55 56 TRIG 1 2 Direct analog input ANn or input TRIGn TRIGn causes one of the two queues to execute I 14 30 Debug Support Signals JTAG_EN JTAG_EN Selects between multiplexed debug module and JTAG signals at reset I 14 30 Development ser...

Page 287: ...High VRH and low VRL reference potentials for the analog converter Ground 14 33 QADC analog supply VDDA VSSA Isolate the QADC analog circuitry from digital power supply noise I 14 33 PLL analog supply VDDPLL VSSPLL Isolate the PLL analog circuitry from digital power supply noise I 14 33 QADC positive supply VDDH Supplies positive power to the ESD structures in the QADC pads I 14 33 Flash erase pro...

Page 288: ...ility indication wait state generation and internal external termination O D 31 0 Data bus Provide the general purpose data path between the MCU and all other devices I O DDATA 3 0 Display captured processor addresses data and breakpoint status O DSO TDO Provides single bit communication for debug module responses DSO Provides serial data port for outputting JTAG logic data TDO O DSI TDI Developme...

Page 289: ... O ETXER Asserted for one or more E_TXCLKs while ETXEN is also asserted to cause the PHY to send one or more illegal symbols O EXTAL Driven by an external clock except when used as a connection to the external crystal I VDDF VSSF Supply power and ground to Flash array I VPP Used for Flash stress testing I GPTA 3 0 Provide the external interface to the timer A functions I O GPTB 3 0 Provide the ext...

Page 290: ...e SDRAMs within a memory block O SIZ 1 0 Specify the data access size of the current external bus reference O SRAS SDRAM synchronous row address strobe O VSTBY Provides standby voltage to RAM array if VDD is lost I SYNCA SYNCB Clear the timer s clock providing a means of synchronization to externally clocked or timed events I TA Indicates that the external data transfer is complete and should be a...

Page 291: ...lect I Yes T14 CLKMOD1 Clock mode select I Yes T11 RCON Reset configuration enable I Yes H1 D26 PA2 Chip mode I O K2 D17 PB1 Chip mode I O K3 D16 PB0 Chip mode I O J4 D19 PB3 Boot device data port size I O K1 D18 PB2 Boot device data port size I O J2 D21 PB5 Output pad drive strength I O External Memory Interface and Ports C6 B6 A5 A 23 21 PF 7 5 CS 6 4 Address bus O Yes C4 B4 A4 B3 A3 A 20 16 PF ...

Page 292: ...es C6 B6 A5 A 23 21 PF 7 5 CS 6 4 Chip selects 6 4 O Yes SDRAM Controller H15 SRAS PSD5 SDRAM row address strobe I O H16 SCAS PSD4 SDRAM column address strobe I O G15 DRAMW PSD3 SDRAM write enable I O H13 G16 SDRAM_CS 1 0 PSD 2 1 SDRAM chip selects I O H14 SCKE PSD0 SDRAM clock enable I O External Interrupts Port B15 B16 C14 C15 C16 D14 D15 IRQ 7 1 PNQ 7 1 External interrupt request I O Ethernet C...

Page 293: ... B8 ERXER PEL0 MAC Receive error I O FlexCAN D16 CANRX PAS3 URXD2 FlexCAN Receive data I O E13 CANTX PAS2 UTXD2 FlexCAN Transmit data I O I2 C E14 SDA PAS1 URXD2 I2 C Serial data I O Yes5 E15 SCL PAS0 UTXD2 I2 C Serial clock I O Yes6 QSPI F13 QSPI_DOUT PQS0 QSPI data out I O E16 QSPI_DIN PQS1 QSPI data in I O F14 QSPI_CLK PQS2 QSPI clock I O G14 G13 F16 F15 QSPI_CS 3 0 PQS 6 3 QSPI chip select I O...

Page 294: ...I O K13 DTOUT2 PTC0 UCTS1 UCTS0 U1 U0 Clear to Send I O J16 DTIN1 PTD3 URTS1 URTS0 U1 U0 Request to Send I O J15 DTOUT1 PTD2 URTS1 URTS0 U1 U0 Request to Send I O J14 DTIN0 PTD1 UCTS1 UCTS0 U1 U0 Clear to Send I O J13 DTOUT0 PTD0 UCTS1 UCTS0 U1 U0 Clear to Send I O General Purpose Timers T13 R13 P13 N13 GPTA 3 0 PTA 3 0 Timer A IC OC PAI I O Yes T12 R12 P12 N12 GPTB 3 0 PTB 3 0 Timer B IC OC PAI I...

Page 295: ...nalog channel 1 I O T2 AN2 PQB2 ANY Analog channel 2 I O R1 AN3 PQB3 ANZ Analog channel 3 I O R4 AN52 PQA0 MA0 Analog channel 52 I O T4 AN53 PQA1 MA1 Analog channel 53 I O P3 AN55 PQA3 ETRIG1 Analog channel 55 I O R3 AN56 PQA4 ETRIG2 Analog channel 56 I O P4 VRH High analog reference I T5 VRL Low analog reference I Debug and JTAG Test Port Control R9 JTAG_EN JTAG Enable I P9 DSCLK TRST Debug clock...

Page 296: ...tandby power I E6 E11 F5 F7 F10 F12 G5 G6 G11 G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 L5 L7 L10 L12 M6 M11 VDD Positive supply I A1 A16 E5 E12 F6 F11 G7 G10 H7 H10 J7 J10 K7 K10 L6 L11 M5 M12 T16 VSS Ground I 1 Pull ups are not active when GPIO functions are selected for the pins 2 The primary functionality of a pin is not necessarily its default functionality Pins that have GPIO functionali...

Page 297: ... 14 4 will operate as described above All other signals will default to GPIO inputs Table 14 4 Pin Reset States at Reset Single Chip Mode Signal Reset I O Clock and Reset Signals RSTI I RSTO Low O EXTAL I XTAL XTAL O CLKOUT CLKOUT O Debug Support Signals JTAG_EN I DSCLK TRST I BKPT TMS I DSI TDI I DSO TDO High O TCLK I DDATA 3 0 DDATA 3 0 O PST 3 0 PST 3 0 O Table 14 5 Default Signal Functions Aft...

Page 298: ...y the MCF5282 on the rising CLKOUT edge The data bus port width and wait states are initially defined for the external boot chip select CS0 by D 19 18 during chip configuration at reset The port width for each chip select and SDRAM bank is programmable The data bus uses a default configuration if none of the chip selects or SDRAM bank match the address decode The default configuration is a 32 bit ...

Page 299: ...izes TA it latches the data and then terminates the bus cycle During a write cycle when the processor recognizes TA the bus cycle is terminated If all bus cycles support fast termination TA can be tied low This pin can also be configured as GPIO PE6 14 2 1 6 Transfer Error Acknowledge TEA This signal indicates an error condition exists for the bus transfer The bus cycle is terminated and the CPU b...

Page 300: ...st access and the size of the current port transfer on subsequent transfers For example for a longword write to an 8 bit port SIZ 1 0 00 for the first byte transfer and 01 for the next three These pins can also be configured as GPIO PE 3 2 or SYNCA SYNCB 14 2 1 9 Transfer Start TS The MCF5282 asserts TS during the first CLKOUT cycle of a transfer when address and attributes TIP R W and SIZ 1 0 are...

Page 301: ...for SDRAM accesses 14 2 2 1 SDRAM Row Address Strobe SRAS This output is the SDRAM synchronous row address strobe This pin is configured as GPIO PSD5 in single chip mode 14 2 2 2 SDRAM Column Address Strobe SCAS This output is the SDRAM synchronous column address strobe This pin is configured as GPIO PSD4 in single chip mode 14 2 2 3 SDRAM Write Enable DRAMW The DRAM write signal DRAMW is asserted...

Page 302: ...his input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator 14 2 3 4 XTAL This output is an internal oscillator connection to the external crystal 14 2 3 5 Clock Output CLKOUT The internal PLL generates CLKOUT This output reflects the internal system clock 14 2 4 Chip Configuration Signals 14 2 4 1 RCON If the external RCON s...

Page 303: ...d be connected to VSS This pin can also be configured as GPIO PAS5 or URXD2 14 2 6 2 Management Data Clock EMDC EMDC is an output clock which provides a timing reference to the PHY for data transfers on the EMDIO signal and applies to MII mode operation This pin can also be configured as GPIO PAS4 or UTXD2 14 2 6 3 Transmit Clock ETXCLK This is an input clock which provides a timing reference for ...

Page 304: ... pin can also be configured as GPIO PEH2 14 2 6 9 Receive Data 0 ERXD0 ERXD0 is the Ethernet input data transferred from the PHY to the media access controller when ErXDV is asserted This signal is used for 10 Mbps Ethernet data This signal is also used for MII mode Ethernet data in conjunction with ERXD 3 1 This pin can also be configured as GPIO PEH1 14 2 6 10 Carrier Receive Sense ECRS ECRS is ...

Page 305: ...QSPI and can be programmed to be driven on the rising or falling edge of QSPICLK Each byte is sent msb first This pin can also be configured as GPIO PQS0 14 2 7 2 QSPI Synchronous Serial Data Input QSPI_DIN The QSPI_DIN input provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPICLK Each byte is written to RAM lsb first This pin can also be c...

Page 306: ...the master mode or it becomes the clock input when the I2 C is in the slave mode This pin can also be configured as GPIO PAS0 or UTXD2 14 2 9 2 Serial Data SDA This bidirectional open drain signal is the data input output for the I2 C interface This pin can also be configured as GPIO PAS1 or URXD2 14 2 10 UART Module Signals The signals in the following sections are used to transfer serial data be...

Page 307: ...ered as secondary functions on four pins DTIN2 DTOUT2 DTIN0 and DTOUT0 14 2 10 4 Request to Send URTS 1 0 The URTS 1 0 signals are automatic request to send outputs from the UART modules URTS 1 0 can also be configured to be asserted and negated as a function of the Rx FIFO level The URTS 1 0 outputs are each offered as secondary functions on four pins DTIN3 DTOUT3 DTIN1 and DTOUT1 14 2 11 General...

Page 308: ...se events to occur in DMA timer 1 This can either clock the event counter or provide a trigger to the timer value capture logic This pin can also be configured as GPIO PTD3 secondary function URTS1 or secondary function URTS0 14 2 12 4 DMA Timer 1 Output DTOUT1 The programmable DMA timer output DTOUT1 pulse or toggle on various timer events This pin can also be configured as GPIO PTD2 secondary fu...

Page 309: ... QADC Analog Input AN0 ANW This PQB signal is the direct analog input AN0 When using external multiplexing this pin can also be configured as multiplexed input ANW This pin can also be configured as GPIO PQB0 14 2 13 2 QADC Analog Input AN1 ANX This PQB signal is the direct analog input AN1 When using external multiplexing this pin can also be configured as multiplexed input ANX This pin can also ...

Page 310: ...gnal TRIG2 to trigger the execution of one of the two queues This pin can also be configured as GPIO PQA4 14 2 14 Debug Support Signals These signals are used as the interface to the on chip JTAG controller and also to interface to the BDM logic 14 2 14 1 JTAG_EN This input signal is used to select between multiplexed debug module and JTAG signals at reset If JTAG_EN is low the part is in normal a...

Page 311: ...TDI Debug mode operation If JTAG_EN is low DSI is selected DSI provides the single bit communication for debug module commands JTAG mode operation TDI is selected TDI provides the serial data port for loading the various JTAG boundary scan bypass and instruction registers Shifting in data depends on the state of the JTAG controller state machine and the instruction in the instruction register Shif...

Page 312: ...15 1 Test TEST This input signal is reserved for factory testing only and should be connected to VSS to prevent unintentional activation of test functions Table 14 7 Processor Status Encoding PST 3 0 Definition 0000 Continue execution 0001 Begin execution of an instruction 0010 Reserved 0011 Entry into user mode 0100 Begin execution of PULSE and WDDATA instruction 0101 Begin execution of taken bra...

Page 313: ...he digital power supply 14 2 16 3 PLL Analog Supply VDDPLL VSSPLL These are dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply 14 2 16 4 QADC Positive Supply VDDH This pin supplies positive power to the ESD structures in the QADC pads 14 2 16 5 Power for Flash Erase Program VPP This pin is used for Flash ...

Page 314: ...14 34 MCF5282 User s Manual MOTOROLA MCF5282 External Signals ...

Page 315: ...h the ColdFire product The key features of the DRAM controller include the following Support for two independent blocks of SDRAM Interface to standard SDRAM components Programmable SRAS SCAS and refresh timing Support for 8 16 and 32 bit wide SDRAM blocks 15 1 1 Definitions The following terminology is used in this chapter SDRAM block Any group of DRAM memories selected by one of the MCF5282 SRAS ...

Page 316: ...s from the refresh counter DRAM control register DCR Contains data to control refresh operation of the DRAM controller Both memory blocks are refreshed concurrently as controlled by DCR RC Refresh counter Determines when refresh should occur controlled by the value of DCR RC It generates a refresh request to the control block Hit logic Compares address and attribute signals of a current SDRAM bus ...

Page 317: ... refresh and various combinations of these functions Table 15 1 lists common SDRAM commands SDRAMs operate differently than asynchronous DRAMs particularly in the use of data pipelines and commands to initiate special actions Commands are issued to memory using specific encodings on address and control pins Soon after system reset a command must be sent to the SDRAM mode register to configure SDRA...

Page 318: ...memory block of SDRAMs connected to the MCF5282 One SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals SCKE Synchronous DRAM clock enable Connected directly to the CKE clock enable signal of SDRAMs Enables and disables the clock internal to SDRAM When CKE is low memory can enter a power down mode in which operations are suspended or capable of entering self refres...

Page 319: ...e for putting the command information on the proper address bit 11 IS Initiate self refresh command 0 Take no action or issue a SELFX command to exit self refresh 1 If DCR COC 0 the SDRAM controller sends a SELF command to both SDRAM blocks to put them in low power self refresh state where they remain until IS is cleared When IS is cleared the controller sends a SELFX command for the SDRAMs to exi...

Page 320: ...pared with the corresponding address of the current bus cycle If all unmasked bits match the address hits in the associated DRAM block BA functions the same as in asynchronous operation 17 16 Reserved should be cleared 15 RE Refresh enable Determines when the DRAM controller generates a refresh cycle to the DRAM block 0 Do not refresh associated DRAM block 1 Refresh associated DRAM block 14 Reserv...

Page 321: ...ns Because the SDRAM does not register this information it doesn t matter if the IMRS access is a read or a write or what if any data is put onto the data bus The DRAM controller clears IMRS after the MRS command finishes 0 Take no action 1 Initiate MRS command 5 4 PS Port size Indicates the port size of the associated block of SDRAM which allows for dynamic sizing of associated SDRAM accesses PS ...

Page 322: ...d 0 Allow write accesses 1 Ignore write accesses The DRAM controller ignores write accesses to the memory block and an address exception occurs Write accesses to a write protected DRAM region are compared in the chip select module for a hit If no hit occurs an external bus cycle is generated If this external bus cycle is not acknowledged an access exception occurs 7 Reserved should be cleared 6 1 ...

Page 323: ...tions for interfacing the MCF5282 to the SDRAM To use the tables find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5282 which is not necessarily the SDRAM port size For example if two 1M x 16 bit SDRAMs together form a 1M x 32 bit memory the port size is 32 bits Most SDRAMs likely have fewer address lines than are shown in the t...

Page 324: ... A9 A10 A11 A12 A13 Table 15 10 MCF5282 to SDRAM Interface 8 Bit Port 11 Column Address Lines MCF5282 Pins A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 Row 17 16 15 14 13 12 11 10 9 19 21 22 23 Column 0 1 2 3 4 5 6 7 8 18 20 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Table 15 11 MCF5282 to SDRAM Interface 8 Bit Port 12 Column Address Lines MCF5282 Pins A17 A16 A15 A14 A13 A12 A11 A...

Page 325: ... A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Table 15 15 MCF5282 to SDRAM Interface 16 Bit Port 10 Column Address Lines MCF5282 Pins A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 Row 16 15 14 13 12 11 10 9 18 20 21 22 23 Column 1 2 3 4 5 6 7 8 17 19 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Table 15 16 MCF5282 to SDRAM Interface 16 Bit Port 11 Column Address Lines MCF5282 Pins A16 A15 A14...

Page 326: ...1 A12 A13 Table 15 20 MCF5282 to SDRAM Interface 32 Bit Port 9 Column Address Lines MCF5282 Pins A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 Row 15 14 13 12 11 10 9 17 19 20 21 22 23 Column 2 3 4 5 6 7 8 16 18 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Table 15 21 MCF5282 to SDRAM Interface 32 Bit Port 10 Column Address Lines MCF5282 Pins A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22...

Page 327: ...LKOUT for as long as accesses occur in that page In burst page mode there are multiple read or write operations for every ACTV command in the SDRAM if the requested transfer size exceeds Table 15 23 MCF5282 to SDRAM Interface 32 Bit Port 12 Column Address Lines MCF5282 Pins A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0...

Page 328: ...a burst read operation In this example DACR CASL 01 for an SRAS to SCAS delay tRCD of 2 system clock cycles Because tRCD is equal to the read CAS latency SCAS assertion to data out this value is also 2 system clock cycles Notice that NOPs are executed until the last data is read A PALL command is executed one cycle after the last data transfer Figure 15 6 Burst Read SDRAM Access Figure 15 7 shows ...

Page 329: ...ted to assure precharge to ACTV delay 15 2 3 5 Auto Refresh Operation The DRAM controller is equipped with a refresh counter and control This logic is responsible for providing timing and control to refresh the SDRAM without user interaction Once the refresh counter is set and refresh is enabled the counter counts to zero At this time an internal refresh request flag is set and the counter begins ...

Page 330: ...is inserted before the next ACTV command is generated In this example the next bus cycle is initiated but does not generate an SDRAM access until TRC is finished Because both chip selects are active during the REF command it is passed to both blocks of external SDRAM Figure 15 8 Auto Refresh Operation 15 2 3 6 Self Refresh Operation Self refresh is a method of allowing the SDRAM to enter into a lo...

Page 331: ...DACR IP and accessing a SDRAM location Wait the time determined by tRP before any other execution 4 Enable refresh set DACR RE and wait for at least 8 refreshes to occur 5 Before issuing the MRS command determine if the DMR mask bits need to be modified to allow the MRS to execute properly 6 Issue the MRS command by setting DACR IMRS and accessing a location in the SDRAM Note that mode register se...

Page 332: ...the MCF5282 The SDRAM mode register is written by setting the associated block s DACR IMRS First the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set Note that improperly set DMR mask bits may prevent access to the mode register address Thus the user should determine the mapping of the mode register address to the MCF5282 address bit...

Page 333: ... SDRAM Example Specifications Parameter Specification Speed grade 8E 40 MHz 25 ns period 10 rows 8 columns Two bank select lines to access four internal banks ACTV to read write delay tRCD 20 ns min Period between auto refresh and ACTV command tRC 70 ns ACTV command to precharge command tRAS 48 ns min Precharge command to ACTV command tRP 20 ns min Last data input to PALL command tRWL 1 bus clock ...

Page 334: ...e 15 26 SDRAM Hardware Connections MCF5282 Pins A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CMD BA0 BA1 15 14 13 12 11 10 9 8 0 Field NAM COC IS RTIM RC Setting 0000_0000_0010_0110 hex 0026 Figure 15 11 Initialization Values for DCR Table 15 27 DCR Initialization Values Bits Name Setting Description 15 0 Reserved 14 0 Reserved 13 NAM 0 Indicating...

Page 335: ...r Configuration Table 15 28 DACR Initialization Values Bits Name Setting Description 31 18 BA 1111_1111_ 1000_10 Base address So DACR0 31 16 0xFF88 placing the starting address of the SDRAM accessible memory at 0xFF88_0000 17 16 Reserved Don t care 15 RE 0 Keeps auto refresh disabled because registers are being set up at this time 14 Reserved Don t care 13 12 CASL 00 Indicates a delay of data 1 cy...

Page 336: ...0_x111_0101 hex 0075 Figure 15 14 DMR0 Register Table 15 29 DMR0 Initialization Values Bits Name Setting Description 31 18 BAM With bits 17 and 16 as don t cares BAM 0x0074 which leaves bank select bits and upper 512K select bits unmasked Note that bits 22 and 21 are set because they are used as bank selects bit 20 is set because it controls the 1 Mbyte boundary address 17 16 Reserved Don t care 1...

Page 337: ...value Although A 31 20 corresponds to the address programmed in DACR0 according to how DACR0 and DMR0 are initialized bit 19 must be set to hit in the SDRAM Thus before the mode register bit is set DMR0 19 must be set to enable masking Table 15 30 Mode Register Initialization MCF5282 Pins SDRAM Pins Mode Register Initialization A20 A10 Reserved X A19 A9 WB 0 A18 A8 Opmode 0 A17 A7 Opmode 0 A9 A6 C...

Page 338: ...recharge Sequence move l 0xFF880308 d0 Set DACR0 IP move l d0 DACR0 move l 0xBEADDEED d0 Write and value to memory location to init precharge move l d0 0xFF880000 Refresh Sequence move l 0xFF888300 d0 Enable refresh bit in DACR0 move l d0 DACR0 Mode Register Initialization Sequence move l 0x00600075 d0 Mask bit 19 of address move l d0 DMR0 move l 0xFF888340 d0 Enable DACR0 IMRS DACR0 RE remains se...

Page 339: ...MOTOROLA Chapter 15 Synchronous DRAM Controller Module 15 25 SDRAM Example ...

Page 340: ...15 26 MCF5282 User s Manual MOTOROLA SDRAM Example ...

Page 341: ...on to refer to registers or signals associated with one of the four identical DMA channels DMA0 DMA1 DMA2 or DMA3 16 1 Overview The DMA controller module provides an efficient way to move blocks of data with minimal processor interaction The DMA module shown in Figure 16 1 provides four channels that allow byte word longword or 16 byte burst data transfers Each channel has a dedicated source addre...

Page 342: ...ses Dual address transfers Channel arbitration on transfer boundaries Data transfers in 8 16 32 or 128 bit blocks using a 16 byte buffer Continuous mode or cycle steal transfers Independent transfer widths for source and destination Independent source and destination address registers MUX Arbitration Bus Interface Data Path Control Internal External Channel Channel MUX Registered Data Path SAR0 DA...

Page 343: ...000_0000_0000 R W R W IPSBAR 0x014 Figure 16 2 DMA Request Control Register DMAREQC Table 16 1 DMAREQC Field Description Bits Name Description 31 16 Reserved Should be cleared 15 0 DMACn DMA Channel n Each four bit field defines the logical connection between the DMA requestors and that DMA channel There are seven possible requesters 4 DMA Timers and 3 UARTs Any request can be routed to any of the...

Page 344: ...Requests Cycle Steal and Continuous Modes The DMA controller supports dual address transfers The DMA channels support up to 32 data bits Dual address transfers A dual address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by asserting DREQ Two types of transfer can occur a read from a source device or a write to a destination device S...

Page 345: ...ation of the DMA and the interpretation of the BCR is controlled by the MPARK BCR24BIT See Section 8 5 3 Bus Master Park Register MPARK for more details Reserved 0x10C Reserved Byte count register 0 BCR24BIT 1 1 BCR0 p 16 7 0x110 DMA status register 0 DSR0 p 16 10 Reserved 1 0x140 Source address register 1 SAR1 p 16 6 0x144 Destination address register 1 DAR1 p 16 6 0x148 DMA control register 1 DC...

Page 346: ...of IPSBAR plus an offset of 0x0400_0000 For example for a DMA transfer from the first Flash location when IPSBAR is still at its default location of 0x4000_0000 the source register would be loaded with 0x4400_0000 Backdoor Flash read accesses can be made with the bus master but it takes two cycles longer than a direct read of the Flash when using the FLASHBAR address 16 4 2 Destination Address Reg...

Page 347: ...BCRn shown in Figure 16 6 and Figure 16 7 hold the number of bytes yet to be transferred for a given block The offset within the memory map is based on the value of MPARK BCR24BIT BCRn decrements on the successful completion of the address transfer of a write transfer BCRn decrements by 1 2 4 or 16 for byte word longword or line accesses respectively Figure 16 6 shows BCRn for BCR24BIT 1 Figure 16...

Page 348: ...nsfer Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition 0 No interrupt is generated 1 Internal interrupt signal is enabled 30 EEXT Enable external request Care should be taken because a collision can occur between the START bit and DREQ when EEXT 1 0 External request is ignored 1 Enables external request to initiate transfer The intern...

Page 349: ...Source size Determines the data size of the source bus cycle for the DMA control module 00 Longword 01 Byte 10 Word 11 Line 16 byte burst 19 DINC Destination increment Controls whether a destination address increments after each successful transfer 0 No change to the DAR after a successful transfer 1 The DAR increments by 1 2 4 or 16 depending upon the size of the transfer 18 17 DSIZE Destination ...

Page 350: ...00_0000 R W R W Address IPSBAR 0x110 0x150 0x190 0x1D0 Figure 16 9 DMA Status Registers DSRn Table 16 4 DSRn Field Descriptions Bits Name Description 7 Reserved should be cleared 6 CE Configuration error Occurs when BCR SAR or DAR does not match the requested transfer size or if BCR 0 when the DMA receives a start condition CE is cleared at hardware reset or by writing a 1 to DSR DONE 0 No configu...

Page 351: ...a single address access DCRn SAA 0 or when SAA 1 16 5 1 Transfer Requests Cycle Steal and Continuous Modes The DMA channel supports internal and external requests A request is issued by setting DCRn START or by asserting DREQn Setting DCRn EEXT enables recognition of external DMA requests Selecting between cycle steal and continuous modes minimizes bus usage for either internal or external request...

Page 352: ...xt section 16 5 2 1 Dual Address Transfers Dual address transfers consist of a source data read and a destination data write The DMA controller module begins a dual address transfer sequence during a DMA request If no error condition exists DSRn REQ is set Dual address read The DMA controller drives the SARn value onto the internal address bus If DCRn SINC is set the SARn increments by the appropr...

Page 353: ...gramming the DMA No mechanism exists within the DMA module itself to prevent writes to control registers during DMA accesses If the DCRn BWC value of sequential channels are equal the channels are prioritized in ascending order The SARn is loaded with the source read address If the transfer is from a peripheral device to memory the source address is the location of the peripheral data register If ...

Page 354: ...ource is auto aligned if DCRn SSIZE indicates a transfer size larger than DCRn DSIZE Source alignment takes precedence over the destination when the source and destination sizes are equal Otherwise the destination is auto aligned The address register chosen for alignment increments regardless of the increment value Configuration error checking is performed on registers not chosen for alignment If ...

Page 355: ...ns asserted until BCRn reaches zero DMA has priority over the core Note that in this scheme the arbiter can always force the DMA to relinquish the bus See Section 8 5 3 Bus Master Park Register MPARK 16 5 5 Termination An unsuccessful transfer can terminate for one of the following reasons Error conditions When the MCF5282 encounters a read or write cycle that terminates with an error condition DS...

Page 356: ...16 16 MCF5282 User s Manual MOTOROLA DMA Controller Module Functional Description ...

Page 357: ...edia The FEC supports three different standard MAC PHY physical interfaces for connection to an external Ethernet transceiver The FEC supports the 10 100 Mbps MII and the 10 Mbps only 7 wire interface which uses a subset of the MII pins 17 1 1 Features The FEC incorporates the following features Support for three different Ethernet physical interfaces 100 Mbps IEEE 802 3 MII 10 Mbps IEEE 802 3 MII...

Page 358: ...configured for full duplex mode flow control may be enabled Refer to the TCR RFC_PAUSE and TCR TFC_PAUSE bits the RCR FCE bit and Section 17 4 10 Full Duplex Flow Control for more details 17 2 2 Interface Options The following interface options are supported A detailed discussion of the interface configurations is provided in Section 17 4 5 Network Interface Options 17 2 2 1 10 Mbps and 100 Mbps M...

Page 359: ...MII mode is disabled and the 10 Mbps 7 wire mode is enabled 17 2 3 Address Recognition Options The address options supported are promiscuous broadcast reject individual address hash or exact match and multicast hash match Address recognition options are discussed in detail in Section 17 4 8 Ethernet Address Recognition 17 2 4 Internal Loopback Internal loopback mode is selected via RCR LOOP Loopba...

Page 360: ...ller that provides the following functions in the FEC Initialization those internal registers not initialized by the user or hardware High level control of the DMA channels initiating DMA transfers Interpreting buffer descriptors Address recognition for receive frames Random number generation for transmit collision backoff timer SIF CSR FIFO DMA Descriptor Controller MII Receive Transmit Bus Contr...

Page 361: ... a serial channel for control status communication with the external physical layer device transceiver This serial channel consists of the EMDC Management Data Clock and EMDIO Management Data Input Output lines of the MII interface The DMA block provides multiple channels allowing transmit data transmit descriptor receive data and receive descriptor accesses to run independently The Transmit and R...

Page 362: ...e TCR and RCR will not be reset but the entire data path will be reset 17 4 2 User Initialization Prior to Asserting ECR ETHER_EN The user needs to initialize portions the FEC prior to setting the ECR ETHER_EN bit The exact values will depend on the particular application The sequence is not important Ethernet MAC registers requiring initialization are defined in Table 17 2 Table 17 1 ECR ETHER_EN...

Page 363: ...t up the buffer frame descriptors and write to the TDAR and RDAR Refer to Section 17 6 Buffer Descriptors for more details MSCR optional Clear MIB_RAM locations IPSBAR 0x1200 0x12FC Table 17 3 FEC User Initialization Before ECR ETHER_EN Description Initialize FRSR optional Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize Empty Transmit Descriptor ring Initialize Empty Receive Descript...

Page 364: ...operates in what is generally referred to as the AMD mode 7 wire mode connections to the external transceiver are shown in Table 17 6 Table 17 5 MII Mode Signal Description EMAC pin Transmit Clock ETXCLK Transmit Enable ETXEN Transmit Data ETXD 3 0 Transmit Error ETXER Collision ECOL Carrier Sense ECRS Receive Clock ERXCLK Receive Data Valid ERXDV Receive Data ERXD 3 0 Receive Error ERXER Manageme...

Page 365: ...of a collision This improves bus utilization and latency in case immediate retransmission is necessary When all the frame data has been transmitted the FCS Frame Check Sequence or 32 bit Cyclic Redundancy Check CRC bytes are appended if the TC bit is set in the transmit frame control word If the ABC bit is set in the transmit frame control word a bad CRC will be appended to the frame data regardle...

Page 366: ... 64 bytes of data has been received and if address recognition has not rejected the frame the receive FIFO is signalled that the frame is accepted and may be passed on to the DMA If the frame is a runt due to collision or is rejected by address recognition the receive FIFO is notified to reject the frame Thus no collision fragments are presented to the user except late collisions which indicate se...

Page 367: ...f flow control is enabled the microcontroller will do an exact address match check between the DA and the designated PAUSE DA 01 80 C2 00 00 01 If the receive block determines that the received frame is a valid PAUSE frame then the frame will be rejected Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast physical address If the DA is ...

Page 368: ...e BC_REJ 1 Frame Hash Match Exact Match Pause Frame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Frame PROM field in RCR register PROMiscous mode Pause Frame valid PAUSE frame received Set BC bit in RCV BD Set MC bit in RCV BD if multicast Set M Miss bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if br...

Page 369: ...t within the selected register If the CRC generator selects a bit that is set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group addresses are received the hash table prevents roughly 56 64 or 87 5 of the group address frames from reaching memory Those that do reach memory must be further filtered by t...

Page 370: ...65 ff ff ff ff ff 0x0 0 55 ff ff ff ff ff 0x1 1 15 ff ff ff ff ff 0x2 2 35 ff ff ff ff ff 0x3 3 b5 ff ff ff ff ff 0x4 4 95 ff ff ff ff ff 0x5 5 d5 ff ff ff ff ff 0x6 6 f5 ff ff ff ff ff 0x7 7 db ff ff ff ff ff 0x8 8 fb ff ff ff ff ff 0x9 9 bb ff ff ff ff ff 0xa 10 8b ff ff ff ff ff 0xb 11 0b ff ff ff ff ff 0xc 12 3b ff ff ff ff ff 0xd 13 7b ff ff ff ff ff 0xe 14 5b ff ff ff ff ff 0xf 15 27 ff ff f...

Page 371: ... ff ff ff ff ff 0x25 37 71 ff ff ff ff ff 0x26 38 51 ff ff ff ff ff 0x27 39 7f ff ff ff ff ff 0x28 40 4f ff ff ff ff ff 0x29 41 1f ff ff ff ff ff 0x2a 42 3f ff ff ff ff ff 0x2b 43 bf ff ff ff ff ff 0x2c 44 9f ff ff ff ff ff 0x2d 45 df ff ff ff ff ff 0x2e 46 ef ff ff ff ff ff 0x2f 47 93 ff ff ff ff ff 0x30 48 b3 ff ff ff ff ff 0x31 49 f3 ff ff ff ff ff 0x32 50 d3 ff ff ff ff ff 0x33 51 53 ff ff ff ...

Page 372: ...e frame TCR GTS is asserted by the FEC internally When transmission has paused the EIR GRA interrupt is asserted and the pause timer begins to increment Note that the pause timer makes use of the transmit backoff timer hardware which is used for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DUR slot times have ex...

Page 373: ... be negated before starting its 96 bit time IPG counter Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times If carrier sense asserts during the last 36 bit times it will be ignored and a collision will occur The receiver receives back to back frames with a minimum spacing of at least 28 bit times If an inter packet gap between rece...

Page 374: ...ssion error conditions using the FEC RxBDs the EIR register and the MIB block counters 17 4 14 1 Transmission Errors 17 4 14 1 1 Transmitter Underrun If this error occurs the FEC sends 32 bits that ensure a CRC error and stops transmitting All remaining buffers for that frame are then flushed and closed The UN bit is set in the EIR The FEC will then continue to the next transmit buffer descriptor ...

Page 375: ...ve FIFO is full the FEC sets the OV bit in the RxBD All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available At this point the receive frame status word is written into the FIFO with the OV bit set This frame must be discarded by the driver 17 4 14 2 2 Non Octet Error Dribbling Bits The ...

Page 376: ...vided into 2 sections of 512 bytes each The first is used for control status registers The second contains event statistic counters held in the MIB block Table 17 9 defines the top level memory map 17 5 2 Detailed Memory Map Control Status Registers Table 17 10 shows the FEC register memory map with each register address name and a brief description Table 17 9 Module Memory Map Address Function IP...

Page 377: ...802 3 1998 edition The IEEE Basic Package objects are supported by the FEC but do not require counters in the MIB block In addition some of the recommended package objects which are supported do not require MIB counters Counters for transmit and receive full duplex flow control frames are included as well 0x1084 RCR 32 Receive Control Register 0x10C4 TCR 32 Transmit Control Register 0x10E4 PALR 32...

Page 378: ... 0x1238 RMON_T_P512TO1023 RMON Tx 512 to 1023 byte packets 0x123C RMON_T_P1024TO2047 RMON Tx 1024 to 2047 byte packets 0x1240 RMON_T_P_GTE2048 RMON Tx packets w 2048 bytes 0x1244 RMON_T_OCTETS RMON Tx Octets 0x1248 IEEE_T_DROP Count of frames not counted correctly 0x124C IEEE_T_FRAME_OK Frames Transmitted OK 0x1250 IEEE_T_1COL Frames Transmitted with Single Collision 0x1254 IEEE_T_MCOL Frames Tran...

Page 379: ...rc 0x1298 RMON_R_OVERSIZE RMON Rx Packets MAX_FL bytes good crc 0x129C RMON_R_FRAG RMON Rx Packets 64 bytes bad crc 0x12A0 RMON_R_JAB RMON Rx Packets MAX_FL bytes bad crc 0x12A4 RMON_R_RESVD_0 0x12A8 RMON_R_P64 RMON Rx 64 byte packets 0x12AC RMON_R_P65TO127 RMON Rx 65 to 127 byte packets 0x12B0 RMON_R_P128TO255 RMON Rx 128 to 255 byte packets 0x12B4 RMON_R_P256TO511 RMON Rx 256 to 511 byte packets...

Page 380: ... 16 Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR LC RL UN Reset 0000_0000_0000_0000 R W R W 15 0 Field Reset 0000_0000_0000_0000 R W R W Address IPSBAR 0x1004 Figure 17 4 Ethernet Interrupt Event Register EIR Table 17 12 EIR Field Descriptions Bits Name Description 31 HBERR Heartbeat error This interrupt indicates that HBC is set in the TCR register and that the COL input was not asserted w...

Page 381: ... interrupt This bit indicates that a receive buffer descriptor has been updated that was not the last in the frame 23 MII MII interrupt This bit indicates that the MII has completed the data transfer requested 22 EBERR Ethernet bus error This bit indicates that a system bus error occurred when a DMA transaction was underway When the EBERR bit is set ECR ETHER_EN will be cleared halting frame proce...

Page 382: ...provided ECR ETHER_EN is also set Once the FEC polls a receive descriptor whose empty bit is not set then the FEC will clear the RDAR bit and cease receive descriptor ring polling until the user sets the bit again signifying that additional descriptors have been placed into the receive descriptor ring 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR ...

Page 383: ...ls a transmit descriptor whose ready bit is not set then the FEC will clear the TDAR bit and cease transmit descriptor ring polling until the user sets the bit again signifying additional descriptors have been placed into the transmit descriptor ring The TDAR register is cleared at reset when ECR ETHER_EN is cleared or when ECR RESET is set 31 25 24 23 16 Field R_DES_ACTIVE Reset 0000_0000_0000_00...

Page 384: ...4 Figure 17 7 Transmit Descriptor Active Register TDAR Table 17 15 TDAR Field Descriptions Bits Name Description 31 25 Reserved should be cleared 24 X_DES_ACTIVE Set to one when this register is written regardless of the value written Cleared by the FEC device whenever no additional ready descriptors remain in the transmit ring Also cleared when ECR ETHER_EN is cleared 23 0 Reserved should be clea...

Page 385: ...ission is stopped after a bad CRC is appended to any currently transmitted frame The buffer descriptor s for an aborted transmit frame are not updated after clearing this bit When ETHER_EN is deasserted the DMA buffer descriptor and FIFO control logic are reset including the buffer descriptor and FIFO pointers The ETHER_EN bit is altered by hardware under the following conditions ECR RESET is set ...

Page 386: ...tent of the DATA field is a don t care Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine During this time the contents of the MMFR register will be altered as the contents are serially shifted and will be unpredictable if read by the user Once the read management frame operation has completed the...

Page 387: ...gement frame is complete the MSCR register may optionally be set to zero to turn off the EMDC The EMDC generated will have a 50 duty cycle except when MII_SPEED is changed during operation change will take effect following either a rising or falling edge of EMDC 31 16 Field Reset 0000_0000_0000_0000 R W R W 15 8 7 6 1 0 Field DIS_PREAMBLE MII_SPEED Reset 0000_0000_0000_0000 R W R W Address IPSBAR ...

Page 388: ...B block then clear all the MIB RAM locations then enable the MIB block The MIB_DISABLE bit is reset to 1 See Table 17 11 for the locations of the MIB counters Table 17 19 Programming Examples for MSCR System Clock Frequency MII_SPEED field in reg EMDC frequency 25 MHz 0x5 2 5 MHz 33 MHz 0x7 2 36 MHz 40 MHz 0x8 2 5 MHz 50 MHz 0xA 2 5 MHz 66 MHz 0xD 2 5 MHz 31 30 16 Field MIB_DISABLE MIB_IDLE Reset ...

Page 389: ...he BABR interrupt to occur and will set the LG bit in the end of frame receive buffer descriptor The recommended default value to be programmed by the user is 1518 or 1522 if VLAN Tags are supported 15 6 Reserved should be cleared 5 FCE Flow control enable If asserted the receiver will detect PAUSE frames Upon PAUSE frame detection the transmitter will stop transmitting data frames for a given dur...

Page 390: ...duplex mode 1 Disable reception of frames while transmitting normally used for half duplex mode 0 LOOP Internal loopback If set transmitted frames are looped back internal to the device and the transmit output signals are not asserted The system clock is substituted for the ETXCLK when LOOP is asserted DRT must be set to zero when asserting LOOP 31 16 Field Reset 0000_0000_0000_0000 R W R W 15 5 4...

Page 391: ...l PAUSE frame Next the MAC will clear the TFC_PAUSE bit and resume transmitting data frames Note that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE frame the MAC may still transmit a MAC Control PAUSE frame 2 FDEN Full duplex enable If set frames are transmitted independent of carrier sense and collision inputs This bit should only be modified when ETHER_EN is d...

Page 392: ... type field 0x8808 used for transmission of PAUSE frames This register is not reset and bits 31 16 must be initialized by the user 31 16 Field PADDR1 Reset Uninitialized R W R W 15 0 Field PADDR1 Reset Uninitialized R W R W Address IPSBAR 0x10E4 Figure 17 14 Physical Address Low Register PALR Table 17 23 PALR Field Descriptions Bits Name Description 31 0 PADDR1 Bytes 0 bits 31 24 1 bits 23 16 2 bi...

Page 393: ...ress hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA This register is not reset and must be initialized by the user Table 17 24 PAUR Field Descriptions BIts Name Description 31 16 PADDR2 Bytes 4 bits 31 24 and 5 bits 23 16 of the 6 byte individual address to be used for exact match and the Source Address field...

Page 394: ...eld IADDR1 Reset Uninitialized R W R W 15 0 Field IADDR1 Reset Uninitialized R W R W Address IPSBAR 0x1118 Figure 17 17 Descriptor Individual Upper Address Register IAUR Table 17 26 IAUR Field Descriptions Bits Name Descriptions 31 0 IADDR1 The upper 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a unicast address Bit 31 of IADDR1 contains hash ind...

Page 395: ... must be initialized by the user Table 17 27 IALR Field Descriptions Bits Name Description 31 0 IADDR2 The lower 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a unicast address Bit 31 of IADDR2 contains hash index bit 31 Bit 0 of IADDR2 contains hash index bit 0 31 16 Field GADDR1 Reset Uninitialized R W R W 15 0 Field GADDR1 Reset Uninitialized R...

Page 396: ...may need to be modified to match a given system requirement worst case bus access latency by the transmit data DMA channel 31 16 Field GADDR2 Reset Uninitialized R W R W 15 0 Field GADDR2 Reset Uninitialized R W R W Address IPSBAR 0x1124 Figure 17 20 Descriptor Group Lower Address Register GALR Table 17 29 GALR Field Descriptions Bits Name Description 31 0 GADDR2 The GADDR2 register contains the l...

Page 397: ... Bits Name Descriptions 31 2 Reserved should be cleared 1 0 X_WMRK Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written 31 16 Field Reset 0000_0000_0000_0000 R W Read Only 15 10 9 2 1 0 Field R_BOUND Reset 0000_0110_0000_0000 R W Read Only Address IPSBAR 0x114C Figure 17 22 FIFO Receive Bound Register FRBR Tabl...

Page 398: ...Receive Descriptor Ring Start ERDSR The ERDSR is written by the user It provides a pointer to the start of the circular receive buffer descriptor queue in external memory This pointer must be 32 bit aligned however it is recommended it be made 128 bit aligned evenly divisible by 16 This register is not reset and must be initialized by the user prior to operation 31 16 Field Reset 0000_0000_0000_00...

Page 399: ...sitions are ignored by the hardware This register is not reset and must be initialized by the user prior to operation 31 16 Field R_DES_START Reset Uninitialized R W R W 15 2 1 0 Field R_DES_START Reset Uninitialized R W R W Address IPSBAR 0x1180 Figure 17 24 Receive Descriptor Ring Start Register ERDSR Table 17 33 ERDSR Field Descriptions Bits Name Descriptions 31 2 R_DES_START Pointer to start o...

Page 400: ...this bits 3 0 are forced low To minimize bus utilization descriptor fetches it is recommended that EMRBR be greater than or equal to 256 bytes The EMRBR register does not reset and must be initialized by the user Table 17 34 ETDSR Field Descriptions Bits Name Descriptions 31 2 X_DES_START Pointer to start of transmit buffer descriptor queue 1 0 Reserved should be cleared 31 16 Field Reset Uninitia...

Page 401: ... hardware to signal the buffer has been consumed Software may poll the BDs to detect when the buffers have been consumed or may rely on the buffer frame interrupts These buffers may then be processed by the driver and returned to the free list The ECR ETHER_EN signal operates as a reset to the BD DMA logic When ECR ETHER_EN is deasserted the DMA engine BD pointers are reset to point to the startin...

Page 402: ...rocess until software sets up another transmit frame and writes to TDAR When the DMA of each transmit buffer is complete the DMA writes back to the BD to clear the R bit indicating that the hardware consumer is finished with the buffer 17 6 1 2 Driver DMA Operation with Receive BDs Unlike transmit the length of the receive frame is unknown by the driver ahead of time Therefore the driver must set ...

Page 403: ...update the associated BDs then read the next BD in the receive descriptor ring If the FEC reads a receive BD and finds the E bit 0 it will poll this BD once more If the BD 0 a second time the FEC will stop reading receive BDs until the driver writes to RDAR 17 6 2 Ethernet Receive Buffer Descriptor RxBD In the RxBD the user initializes the E and W bits in the first longword and the pointer in seco...

Page 404: ...d Offset 0 Bit 8 M Miss Written by the FEC This bit is set by the FEC for frames that were accepted in promiscuous mode but were flagged as a miss by the internal address recognition Thus while in promiscuous mode the user can use the M bit to quickly determine whether the frame was destined to this station This bit is valid only if the L bit is set and the PROM bit is set 0 The frame was received...

Page 405: ... Offset 0 Bit 1 OV Overrun Written by the FEC A receive FIFO overrun occurred during frame reception If this bit is set the other status bits M LG NO CR and CL lose their normal meaning and will be zero This bit is valid only if the L bit is set Offset 0 Bit 0 TR Will be set if the receive frame is truncated frame length 2047 bytes If the TR bit is set the frame should be discarded and the other e...

Page 406: ...value affect hardware Offset 0 Bit 13 W Wrap Written by user 0 The next buffer descriptor is found in the consecutive location 1 The next buffer descriptor is found at the location defined in ETDSR Offset 0 BIt 12 TO2 Transmit software ownership This field is reserved for use by software This read write bit will not be modified by hardware nor will its value affect hardware Offset 0 Bit 11 L Last ...

Page 407: ...itten by user Data length is the number of octets the FEC should transmit from this BD s data buffer It is never modified by the FEC Bits 15 5 are used by the DMA engine bits 4 0 are ignored Offset 4 Bits 15 0 A 31 16 Tx data buffer pointer bits 31 16 1 Offset 6 Bits 15 0 A 15 0 Tx data buffer pointer bits 15 0 1 The transmit buffer pointer which contains the address of the associated data buffer ...

Page 408: ...17 52 MCF5282 User s Manual MOTOROLA Buffer Descriptors ...

Page 409: ...dule may facilitate exit from each mode Table 18 1 Watchdog Module Operation in Low power Modes In wait mode with the watchdog control register s WAIT bit WCR WAIT set watchdog timer operation stops In wait mode with the WCR WAIT bit cleared the watchdog timer continues to operate normally In doze mode with the WCR DOZE bit set the watchdog timer module operation stops In doze mode with the WCR DO...

Page 410: ...s made in halted mode remain 18 3 Block Diagram Figure 18 1 Watchdog Timer Block Diagram 18 4 Signals The watchdog timer module has no off chip signals 18 5 Memory Map and Registers This subsection describes the memory map and registers for the watchdog timer The watchdog timer has a IPSBAR offset for base address of 0x0014_0000 18 5 1 Memory Map Refer to Table 18 2 for an overview of the watchdog...

Page 411: ... WCR The 16 bit WCR configures watchdog timer operation Table 18 2 Watchdog Timer Module Memory Map IPSBAR Offset Bits 15 8 Bits 7 0 Access 1 1 S CPU supervisor mode access only S U CPU supervisor or user mode access User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error 0x0014_0000 Watchdog Control Register WCR S 0x0014_0002 Watchdog Modulu...

Page 412: ...egisters can be written and read normally When halted mode is exited timer operation continues from the state it was in before entering halted mode but any updates made in halted mode remain If a write once register is written for the first time in halted mode the register is still writable when halted mode is exited 1 Watchdog timer stopped in halted mode 0 Watchdog timer not affected in halted m...

Page 413: ... is reloaded into the watchdog counter by a service sequence Once written the WM 15 0 field is not affected by further writes except in halted mode Writing to WMR immediately loads the new modulus value into the watchdog counter The new value is also used at the next and all subsequent reloads Reading WMR returns the value in the modulus register Reset initializes the WM 15 0 field to 0xFFFF Note ...

Page 414: ...isters 15 14 13 12 11 10 9 8 Field WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 Reset 0000_0000 R W R W 7 6 5 4 3 2 1 0 Field WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 Reset 0000_0000 R W R W Address IPSBAR 0x0014_0006 0x0014_0007 Figure 18 5 Watchdog Service Register WSR ...

Page 415: ...tervals with minimal processor intervention The timer can either count down from the value written in the modulus register or it can be a free running down counter This device has four programmable interrupt timers PIT0 PIT3 19 2 Block Diagram Figure 19 1 PIT Block Diagram 16 bit PMR 16 bit PIT Counter COUNT 0 System Clock IPBUS 16 bit PCNTR IPBUS EN OVW DOZE HALTED Prescaler PRE 3 0 RLD PIF PIE L...

Page 416: ...e operation stops In doze mode with the PCSR DOZE bit cleared doze mode does not affect PIT operation When doze mode is exited the PIT continues to operate in the state it was in prior to doze mode In stop mode the system clock is absent and PIT module operation stops In halted mode with the PCSR HALTED bit set PIT module operation stops In halted mode with the PCSR HALTED bit cleared halted mode ...

Page 417: ...tatus register PCSR configures the timer s operation The PIT modulus register PMR determines the timer modulus reload value The PIT count register PCNTR provides visibility to the counter value Table 19 2 Programmable Interrupt Timer Modules Memory Map IPSBAR Offset for PITx Address Bits 15 8 Bits 7 0 Access 1 1 S CPU supervisor mode access only S U CPU supervisor or user mode access User mode acc...

Page 418: ...d should be cleared 11 8 PRE Prescaler The read write prescaler bits select the system clock divisor to generate the PIT clock To accurately predict the timing of the next count change the PRE 3 0 bits only when the enable bit EN is clear Changing the PRE 3 0 resets the prescaler counter System reset and the loading of a new value into the counter also reset the prescaler counter Setting the EN bi...

Page 419: ... in halted mode remain 0 PIT function not affected in halted mode 1 PIT function stopped in halted mode Note Changing the HALTED bit from 1 to 0 during halted mode starts the PIT timer Likewise changing the HALTED bit from 0 to 1 during halted mode stops the PIT timer 4 OVW Overwrite Enables writing to PMR to immediately overwrite the value in the PIT counter 0 Value in PMR replaces value in PIT c...

Page 420: ...ter and the counter begins decrementing toward 0x0000 If the PIE bit is set in PCSR the PIF flag issues an interrupt request to the CPU 15 14 13 12 11 10 9 8 Field PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8 Reset 1111_1111 R W R W 7 6 5 4 3 2 1 0 Field PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Reset 1111_1111 R W R W Address IPSBAR 0x0015_0002 and 0x0015_0003 PIT0 0x0016_0002 and 0x0016_0003 PIT1 0x0017_0002 and...

Page 421: ...unter reaches a count of 0x0000 the PIF flag is set in PCSR If the PIE bit is set in PCSR the PIF flag issues an interrupt request to the CPU When the OVW bit is set in PCSR the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000 Figure 19 6 Counter in Free Running Mode 19 6 3 Timeout Specifications The 16 bit PIT counter and prescaler support...

Page 422: ...he interrupt request generated by the PIT The PIF flag is set when the PIT counter reaches 0x0000 The PIE bit enables the PIF flag to generate interrupt requests Clear PIF by writing a 1 to it or by writing to the PMR Table 19 4 PIT Interrupt Requests Interrupt Request Flag Enable Bit Timeout PIF PIE ...

Page 423: ...rate output waveforms and timer software delays These functions allow simultaneous input waveform measurements and output waveform generation Additionally one of the channels channel 3 can be configured as a 16 bit pulse accumulator that can operate as a simple event counter or as a gated time accumulator The pulse accumulator uses the GPT channel 3 input output pin in either event mode or gated t...

Page 424: ...0F C1F Edge Detect PT1 LOGIC Edge Detect CxF Channel 2 Channel3 GPTC3H GPTC3L 16 Bit Comparator 16 Bit Latch C3F PT3 LOGIC Edge Detect IOS0 IOS1 IOS3 OM OL0 TOV0 OM OL1 TOV1 OM OL3 TOV3 EDG1A EDG1B EDG3A EDG3B EDG0A EDG0B TCRE Channel 3 Output Compare PAIF Clear Counter PAIF PAI Interrupt Logic CxI Interrupt Request Interrupt Request PAOVF CH 3 Compare CH 3 Capture CH 1 Capture MUX CLK 1 0 PACLK P...

Page 425: ...provides an overview of the signal properties NOTE Throughout this section an n in the pin name as in GPTn0 designates GPTA or GPTB 20 4 1 GPTn 2 0 The GPTn 2 0 pins are for channel 2 0 input capture and output compare functions These pins are available for general purpose input output I O when not configured for timer functions Low power Mode Watchdog Operation Mode Exit Wait Normal No Doze Norma...

Page 426: ...rved or unimplemented locations has no effect Table 20 3 GPT Modules Memory Map IPSBAR Offset Bits 7 0 Access 1 GPTA GPTB 0x1A_0000 0x1B_0000 GPT IC OC Select Register GPTIOS S 0x1A_0001 0x1B_0001 GPT Compare Force Register GPTCFORC S 0x1A_0002 0x1B_0002 GPT Output Compare 3 Mask Register GPTOC3M S 0x1A_0003 0x1B_0003 GPT Output Compare 3 Data Register GPTOC3D S 0x1A_0004 0x1B_0004 GPT Counter Reg...

Page 427: ...1B_0018 Pulse Accumulator Control Register GPTPACTL S 0x1A_0019 0x1B_0019 Pulse Accumulator Flag Register GPTPAFLG S 0x1A_001A 0x1B_001A Pulse Accumulator Counter Register High GPTPACNTH S 0x1A_001B 0x1B_001B Pulse Accumulator Counter Register Low GPTPACNTL S 0x1A_001C 0x1B_001C Reserved 2 0x1A_001D 0x1B_001D GPT Port Data Register GPTPORT S 0x1A_001E 0x1B_001E GPT Port Data Direction Register GPT...

Page 428: ...er channels These bits are read anytime always read 0x00 write anytime 1 Output compare enabled 0 Input capture enabled 7 4 3 0 Field FOC Reset 0000_0000 R W R W Address IPSBAR 0x1A_00001 0x1B_0001 Figure 20 3 GPT Input Compare Force Register GPCFORC Table 20 5 GPTCFORC Field Descriptions Bit s Name Description 7 4 Reserved should be cleared 3 0 FOC Force output compare Setting an FOC bit causes a...

Page 429: ...he data direction bit when the pin is configured for output compare IOSx 1 The OC3Mn bits do not change the state of the PORTTnDDR bits These bits are read anytime write anytime 1 Corresponding PORTTn pin configured as output 0 No effect 7 4 3 0 Field OC3D Reset 0000_0000 R W R W Address IPSBAR 0x1A_0003 0x1B_0003 Figure 20 5 GPT Output Compare 3 Data Register GPTOC3D Table 20 7 GPTOC3D Field Desc...

Page 430: ...x1B_0006 Figure 20 7 GPT System Control Register 1 GPTSCR1 Table 20 9 GPTSCR1 Field Descriptions Bit s Name Description 7 GPTEN Enables the general purpose timer When the timer is disabled only the registers are accessible Clearing GPTEN reduces power consumption These bits are read anytime write anytime 1 GPT enabled 0 GPT and GPT counter disabled 6 5 Reserved should be cleared 4 TFFCA Timer fast...

Page 431: ...ed 3 0 TOV Toggles the output compare pin on overflow for each channel This feature only takes effect when in output compare mode When set it takes precedence over forced output compare but not channel 3 override events These bits are read anytime write anytime 1 Toggle output compare pin on overflow feature enabled 0 Toggle output compare pin on overflow feature disabled 7 6 5 4 3 2 1 0 Field OM3...

Page 432: ...3 shares a pin with the pulse accumulator input pin To use the PAI input clear both the OM3 and OL3 bits and clear the OC3M3 bit in the output compare 3 mask register 7 6 5 4 3 2 1 0 Field EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A Reset 0000_0000 R W R W Address IPSBAR 0x1A_000B 0x1B_000B Figure 20 11 GPT Control Register 2 GPTCTL2 Table 20 12 GPTLCTL2 Field Descriptions Bit s Name Descripti...

Page 433: ... PUPT Enables pull up resistors on the GPT ports when the ports are configured as inputs 1 Pull up resistors enabled 0 Pull up resistors disabled 4 RDPT GPT drive reduction Reduces the output driver size 1 Output drive reduction enabled 0 Output drive reduction disabled 3 TCRE Enables a counter reset after a channel 3 compare 1 Counter reset enabled 0 Counter reset disabled Note When the GPT chann...

Page 434: ...flag When a channel flag is set it does not inhibit subsequent output compares or input captures 7 6 5 4 3 0 Field TOF CF Reset 0000_0000 R W R W Address IPSBAR 0x1A_000F 0x1B_000F Figure 20 15 GPT Flag Register 2 GPTFLG2 Table 20 16 GPTFLG2 Field Descriptions Bit s Name Description 7 TOF Timer overflow flag Set when the GPT counter rolls over from 0xFFFF to 0x0000 If the TOI bit in GPTSCR2 is als...

Page 435: ...ontain the output compare value To ensure coherent reading of the GPT counter such that a timer rollover does not occur between back to back 8 bit reads it is recommended that only word 16 bit accesses be used These bits are read anytime write anytime for the output compare channel writing to the input capture channel has no effect 7 6 5 4 3 0 Field PAE PAMOD PEDGE CLK PAOVI PAI Reset 0000_0000 R ...

Page 436: ...e 1 Apply logic 0 to RSTI pin 2 Initialize registers for pulse accumulator mode test 3 Apply appropriate level to PAI pin 4 Enable GPT 3 2 CLK Select the GPT counter input clock Changing the CLK bits causes an immediate change in the GPT counter clock input 00 GPT prescaler clock When PAE 0 the GPT prescaler clock is always the GPT counter clock 01 PACLK 10 PACLK 256 11 PACLK 65536 1 PAOVI Pulse a...

Page 437: ... edge is detected at the PAI pin In event counter mode the event edge sets PAIF In gated time accumulation mode the trailing edge of the gate signal at the PAI pin sets PAIF If the PAI bit in GPTPACTL is also set PAIF generates an interrupt request Clear PAIF by writing a 1 to it 1 Active PAI input 0 No active PAI input 15 0 Field PACNT Reset 0000_0000_0000_0000 R W R W Address IPSBAR 0x1A_001A 0x...

Page 438: ... output DDR bit 1 reads the latched value Writing to a pin configured as a GPT output does not change the pin state These bits are read anytime read pin state when corresponding PORTTn bit is 0 read pin driver state when corresponding GPTDDR bit is 1 write anytime 7 6 5 4 3 0 Field DDRT GPT Function IC OC Pulse Accumulator Function PAI Reset 0000_0000 R W R W Address IPSBAR 0x1A_001E 0x1B_001E Fig...

Page 439: ...re on channel n sets the CnF flag The CnI bit enables the CnF flag to generate interrupt requests 20 6 3 Output Compare Setting an I O select bit IOSn configures channel n as an output compare channel The output compare function can generate a periodic pulse with a programmable polarity duration and frequency When the GPT counter reaches the value in the channel registers of an output compare chan...

Page 440: ...de of operation The minimum pulse width for the PAI input is greater than two module clocks 20 6 5 Event Counter Mode Clearing the PAMOD bit configures the PA for event counter operation An active edge on the PAI pin increments the PA The PA edge bit PEDGE selects falling edges or rising edges to increment the PA An active edge on the PAI pin sets the PA input flag PAIF The PA input interrupt enab...

Page 441: ...e channel 3 output compare mask bit OC3M3 The PA counter register GPTPACNT reflects the number of pulses from the divide by 64 clock since the last reset NOTE The GPT prescaler generates the divide by 64 clock If the timer is not active there is no divide by 64 clock Figure 20 22 Channel 3 Output Compare Pulse Accumulator Logic 20 6 7 General Purpose I O Ports An I O pin used by the timer defaults...

Page 442: ... Driven by Pin Function Comments 0 0 X 4 X X X In Ext Digital input GPT disabled by GPTEN 0 0 1 X X X X Out Data reg Digital output GPT disabled by GPTEN 0 1 0 0 IC 0 IC disable d X 0 In Ext Digital input Input capture disabled by EDGn setting 1 1 0 0 X 0 Out Data reg Digital output Input capture disabled by EDGn setting 1 0 0 0 X 0 In Ext IC and digital input Normal settings for input capture 1 1...

Page 443: ...less of the state of the corresponding DDR bit 3 Setting an OC3M bit configures the corresponding PORTTn pin to be output OC3Mn makes the PORTTn pin an output regardless of the data direction bit when the pin is configured for output compare IOSn 1 The OC3Mn bits do not change the state of the PORTTnDDR bits 4 X Don t care 5 An output compare overrides the data direction bit of the output compare ...

Page 444: ...this flag NOTE When the fast flag clear all enable bit GPTSCR1 TFFCA is set any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG 20 8 3 Pulse Accumulator Input PAIF PAIF is set when the selected edge is detected at the PAI pin In event counter mode the event edge sets PAIF In gated time accumulation mode the trailing edge of the gate signal at the PAI pin sets PAI...

Page 445: ... 3 registers contain 0xFFFF and TCRE is set TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000 When the fast flag clear all bit GPTSCR1 TFFCA is set any access to the GPT counter registers clears GPT flag register 2 When TOF is set it does not inhibit future overflow events ...

Page 446: ...20 24 MCF5282 User s Manual MOTOROLA Interrupts ...

Page 447: ...the four identical timer modules DTIM0 DTIM1 DTIM2 or DTIM3 21 1 Overview Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the system clock or from an external clocking source using the DTINn signal If the system clock is selected it can be divided by 16 or 1 The selected clock source is routed to an 8 bit programmable pre...

Page 448: ...es are programmable through the timer registers shown in Table 21 1 21 2 1 Prescaler The prescaler clock input is selected from system clock divided by 1 or 16 or from the corresponding timer input DTINn DTINn is synchronized to the system clock The synchronization delay is between two and three system clocks The corresponding DMA Timer Divider DMA Timer Mode Register DTMRn Prescaler Mode Bits DMA...

Page 449: ... point DTERn REF is set If DTMRn ORRI is one and DTXMRn DMAEN is zero an interrupt is asserted If DTMRn ORRI is one and DTXMRn DMAEN is one a DMA request is asserted If the free run restart bit DTMRn FRR is set a new count starts If it is clear the timer keeps running 21 2 4 Output Mode When a timer reaches the reference value selected by DTRR it can send an output signal on DTOUTn DTOUTn can be a...

Page 450: ...Register DTRR2 0x488 DMA Timer2 Capture Register DTCR2 0x48C DMA Timer2 Counter Register DTCN2 0x4C0 DMA Timer3 Mode Register TMR3 DMA Timer3 Extended Mode Register DTXMR3 DMA Timer3 Event Register DTER3 0x4C4 DMA Timer3 Reference Register DTRR3 0x4C8 DMA Timer3 Capture Register DTCR3 0x4CC DMA Timer3 Counter Register DTCN3 15 8 7 6 5 4 3 2 1 0 Field PS CE OM ORRI FRR CLK RST Reset 0000_0000_0000_...

Page 451: ...t if 0 0 Disable DMA request or interrupt for reference reached does not affect DMA request or interrupt on capture function 1 Enable DMA request or interrupt upon reaching the reference value 3 FRR Free run restart 0 Free run Timer count continues to increment after reaching the reference value 1 Restart Timer count is reset immediately after reaching the reference value 2 1 CLK Input clock sourc...

Page 452: ...DMA request the processing of the DMA data transfer automatically clears both the REF and CAP flags via the internal DMA ACK signal Table 21 3 DTXMRn Field Descriptions Bits Name Description 7 DMAEN DMA request Enables DMA request output on counter reference match or capture edge event 0 DMA request disabled 1 DMA request enabled 6 1 Reserved should be cleared 0 MODE16 Selects the increment mode f...

Page 453: ...served should be cleared 1 REF Output reference event The counter value DTCNn equals the reference value DTRRn Writing a one to REF clears the event condition Writing a zero has no effect If REF 1 and DTMRn ORRI DTXMRn DMAEN 00 No DMA request or interrupt asserted 01 No DMA request or interrupt asserted 10 Assert an interrupt 11 Assert a DMA request 0 CAP Capture event The counter value has been l...

Page 454: ...egister Capture the timer value on an edge detected on DTINn Configure DTOUTn output mode Increment counter by 1 or by 65 537 16 bit mode Enable disable interrupt or DMA request on counter reference match or capture edge The DTMRn CLK register is configured to select the clock source to be routed to the prescaler System clock can be divided by 1 or 16 DTINn the maximum value of DTINn is 1 5 of the...

Page 455: ... EQU IPSBARx 0x444 Timer1 reference register DTCR0 EQU IPSBARx 0x408 Timer0 capture register DTCR1 EQU IPSBARx 0x448 Timer1 capture register DTCN0 EQU IPSBARx 0x40C Timer0 counter register DTCN1 EQU IPSBARx 0x44C Timer1 counter register DTER0 EQU IPSBARx 0x403 Timer0 event register DTER1 EQU IPSBARx 0x443 Timer1 event register TMR0 is defined as PS 0xFF divide clock by 256 CE 00 disable capture ev...

Page 456: ... beq T0_FINISH If so end timer0 example Otherwise jump back move b 0x02 D0 writing one to TER0 REF clears the event flag move b D0 TER0 jmp T0_LOOP T0_FINISH HALT End processing Example is finished 21 3 2 Calculating Time Out Values The formula below determines time out periods for various reference values Time out period 1 clock frequency x 1 or 16 x DTMRn PS 1 x DTRRn REF When calculating time o...

Page 457: ...eliminating CPU intervention between transfers Transfer RAM in the QSPI is indirectly accessible using address and data registers 22 2 Features Programmable queue to support up to 16 transfers without user intervention Supports transfer sizes of 8 to 16 bits in 1 bit increments Four peripheral chip select lines for control of up to 15 devices Baud rates from 129 4 Kbps to 16 67 Mbps at 66 MHz Prog...

Page 458: ...mand RAM whenever a command in the queue is executed More than one chip select signal can be asserted simultaneously Although QSPI_CS 3 0 will function as simple chip selects in most applications up to 15 devices can be selected by decoding them with an external 4 to 16 decoder Figure 22 1 QSPI Block Diagram Queue Control Block Queue Pointer System Clock 4 Done Comparator End Queue Pointer Status ...

Page 459: ... discussions of serial communication modules such as QSPI that support variable length data units To simplify these discussions the functional unit is referred to as a word regardless of length The user initiates QSPI operation by loading a queue of commands in command RAM writing transmit data into transmit RAM and then enabling the QSPI data transfer The QSPI executes the queued commands and set...

Page 460: ... in which case the transfer completes normally Leaving QWR NEWQP and QWR ENDQP set to 0x0 causes a single transfer to occur when the QSPI is enabled Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phase and polarity using QMR CPHA CPOL Data is transferred with the most significant bit msb first The number of bits transferred defaults to 8 but can ...

Page 461: ...egment located at 0x10 to 0x1F in the QSPI RAM space The user reads this segment to retrieve data from the QSPI Data words with less than 16 bits are stored in the least significant bits of the RAM Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry QWR CPTQP shows which queue entries have been executed The user can query this field to determine which...

Page 462: ...s A maximum of 16 commands can be in the queue Queue execution proceeds from the address in QWR NEWQP through the address in QWR ENDQP The QSPI executes a queue of commands defined by the control bits in each command RAM entry which sequence the following actions Chip select pins are activated Data is transmitted from transmit RAM and received into the receive RAM The synchronous transfer clock QS...

Page 463: ...SPI_CLK delay QDLYR QCD fSYS QDLYR QCD has a range of 1 127 When QDLYR QCD or QCR DSCK equals zero the standard delay of one half the QSPI_CLK period is used The command RAM delay after transmit enable bit QCR DT enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer The delay after transfer can be used to provide a peripheral deselect i...

Page 464: ...he QSPI executes the command at the command RAM address pointed to by QWR NEWQP Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits has been transferred the QSPI stores the working queue pointer value in QWR CPTQP increments the working queu...

Page 465: ...is set the QSPI finishes the current transfer then stops executing commands After the QSPI stops QDLYR SPE can be cleared 22 5 Programming Model Table 22 3 is the QSPI register memory map Reading reserved locations returns zeros The programming model for the QSPI consists of six registers They are the QSPI mode register QMR QSPI delay register QDLYR QSPI wrap register QWR QSPI interrupt register Q...

Page 466: ...4 13 10 9 8 7 0 Field MSTR DOHIE BITS CPOL CPHA BAUD Reset 0000_0001_0000_0100 R W R W Address IPSBAR 0x340 Figure 22 3 QSPI Mode Register QMR Table 22 4 QMR Field Descriptions Bits Name Description 15 MSTR Master mode enable 0 Reserved do not use 1 The QSPI is in master mode Must be set for the QSPI module to operate correctly 14 DOHIE Data output high impedance enable Selects QSPI_Dout mode of o...

Page 467: ...I_CLK 7 0 BAUD Baud rate divider The baud rate is selected by writing a value in the range 2 255 A value of zero disables the QSPI A value of 1 is an invalid setting The desired QSPI_CLK baud rate is related to the system clock and QMR BAUD by the following expression QMR BAUD fSYS 2 desired QSPI_CLK baud rate 15 14 8 7 0 Field SPE QCD DTL Reset 0000_0100_0000_0100 R W R W Address IPSBAR 0x344 Fig...

Page 468: ...Assertion of this bit causes the QSPI to stop execution of commands once it has completed execution of the current command 14 WREN Wraparound enable Enables wraparound mode 0 Execution stops after executing the command pointed to by QWR ENDQP 1 After executing command pointed to by QWR ENDQP wrap back to entry zero or the entry pointed to by QWR NEWQP and continue execution 13 WRTO Wraparound loca...

Page 469: ...ollision interrupt enable Interrupt enable for WCEF Setting this bit enables the interrupt and clearing it disables the interrupt 10 ABRTE Abort interrupt enable Interrupt enable for ABRT flag Setting this bit enables the interrupt and clearing it disables the interrupt 9 Reserved should be cleared 8 SPIFE QSPI finished interrupt enable Interrupt enable for SPIF Setting this bit enables the interr...

Page 470: ...cess requires a single wait state NOTE The QAR does not wrap after the last queue entry within each section of the RAM The application software must handle address range errors 22 5 5 QSPI Address Register QAR The QAR shown in Figure 22 8 is used to specify the location in the QSPI RAM that read and write operations affect 22 5 6 QSPI Data Register QDR The QDR shown in Figure 22 9 is used to acces...

Page 471: ...to inactive level defined by QWR CSIV when transfer is complete 1 Chip selects remain asserted after the transfer of 16 words of data see note below 14 BITSE Bits per transfer enable 0 Eight bits 1 Number of bits set in QMR BITS 13 DT Delay after transfer enable 0 Default reset value 1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that ...

Page 472: ...SPI RAM is set up for a queue of 16 transfers All four QSPI_CS signals are used in this example 1 Write the QMR with 0xB308 to set up 12 bit data words with the data shifted on the falling clock edge and a QSPI_CLK frequency of 4 125 MHz assuming a 66 MHz system clock 2 Write QDLYR with the desired delays QSPICS 3 0 QSPI_CLK QSPI_DOUT QSPI_DIN QS1 QS1 QSPICS to QSPI_CLK QS2 QSPI_CLK to QSPI_DOUT V...

Page 473: ...et up four transfers for each chip select The chip selects are active low in this example 6 Write QAR with 0x0000 to select the first transmit RAM entry 7 Write QDR with sixteen 12 bit words of data 8 Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15 9 Set QDLYR SPE to enable the transfers 10 Wait until the transfers are complete QIR SPIF is set when the transfers...

Page 474: ...22 18 MCF5282 User s Manual MOTOROLA Programming Model ...

Page 475: ...ed by the system clock eliminating the need for an external UART clock As Figure 23 1 shows each UART module interfaces directly to the CPU and consists of the following Serial communication channel Programmable clock generation Internal channel control logic Interrupt control logic Figure 23 1 Simplified Block Diagram NOTE UART0 can be clocked by the DTIN0 pin UART1 can be clocked by the DTIN1 pi...

Page 476: ...A requests for servicing See Section 23 5 2 2 Receiver 23 2 Serial Module Overview The MCF5282 contains three independent UART modules whose features are as follows Each can be clocked by the system clock eliminating a need for an external UART clock Full duplex asynchronous synchronous receiver transmitter channel Quadruple buffered receiver Double buffered transmitter Independently programmable ...

Page 477: ...ite UART clock select register1 UCSRn p 23 8 0x208 0x248 0x288 Read Do not access 2 Write UART command registers UCRn p 23 9 0x20C 0x24C 0x28C UART Read UART receive buffers URBn p 23 11 UART Write UART transmit buffers UTBn p 23 11 0x210 0x250 0x290 Read UART input port change registers UIPCRn p 23 12 Write UART auxiliary control registers1 UACRn p 23 13 0x214 0x254 0x294 Read UART interrupt stat...

Page 478: ... registers UOP0n3 p 23 15 1 UMR1n UMR2n and UCSRn should be changed only after the receiver transmitter is issued a software reset command That is if channel operation is not disabled undesirable results may occur 2 This address is for factory testing Reading this location results in undesired effects and possible incorrect transmission or reception of characters Register contents may also be chan...

Page 479: ...flect the status of the character at the top of the FIFO ERR must be 0 for correct A D flag information when in multidrop mode 1 Block mode The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since the last RESET ERROR STATUS command for the channel was issued See Section 23 3 5 UART Command Registers UCRn 4 3 PM Parity mode Selects the parity or multid...

Page 480: ...tion of RTS to automatically terminate a message transmission Attempting to program a receiver and transmitter in the same channel for RTS control is not permitted and disables RTS control for both 0 The transmitter has no effect on RTS 1 In applications where the transmitter is disabled after transmission completes setting this bit automatically clears UOP RTS one bit time after any characters in...

Page 481: ... 1 688 1110 1 938 0011 1 250 0 750 0111 1 500 1 000 1011 1 750 1111 2 000 7 6 5 4 3 2 1 0 Field RB FE PE OE TxEMP TxRDY FFULL RxRDY Reset 0000_0000 R W Read only Address IPSBAR 0x204 USR0 0x244 USR1 0x284 USR2 Figure 23 4 UART Status Register USRn Table 23 4 USRn Field Descriptions Bits Name Description 7 RB Received break The received break circuit detects breaks that originate in the middle of a...

Page 482: ...mitter empty 0 The transmit buffer is not empty Either a character is being shifted out or the transmitter is disabled The transmitter is enabled disabled by programming UCRn TC 1 The transmitter has underrun both the transmitter holding register and transmitter shift registers are empty This bit is set after transmission of the last stop bit of a character if there are no characters in the transm...

Page 483: ...n Section 23 5 2 Transmitter and Receiver Operating Modes show how these commands are used Table 23 5 UCSRn Field Descriptions Bits Name Description 7 4 RCS Receiver clock select Selects the clock source for the receiver channel 1101 Prescaled system clock 1110 DTIN divided by 16 1111 DTIN 3 0 TCS Transmitter clock select Selects the clock source for the transmitter channel 1101 Prescaled system c...

Page 484: ... UTXD low If the transmitter is empty the break may be delayed up to one bit time If the transmitter is active the break starts when character transmission completes The break is delayed until any character in the transmitter shift register is sent Any character in the transmitter holding register is sent after the break The transmitter must be enabled for the command to be accepted This command i...

Page 485: ... sets USRn TxRDY again Writes to the transmit buffer when the channel s TxRDY 0 and when the transmitter is disabled have no effect on the transmit buffer 1 0 RC This field selects a single command 00 NO ACTION TAKEN Causes the receiver to stay in its current mode If the receiver is enabled it remains enabled if disabled it remains disabled 01 RECEIVER ENABLE If the UART module is not in multidrop...

Page 486: ...ort Change Register UIPCRn Table 23 7 UIPCRn Field Descriptions Bits Name Description 7 5 Reserved should be cleared 4 COS Change of state high to low or low to high transition 0 No change of state since the CPU last read UIPCRn Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 µs occurred on the CTS input UACRn can be programmed to generate an interrupt to the CPU when a chang...

Page 487: ...SRn regardless of UIMRn settings UISRn is cleared when the UART module is reset 7 1 0 Field IEC Reset 0000_0000 R W W Address IPSBAR 0x210 UACR0 0x250 UACR1 0x290 UACR2 Figure 23 10 UART Auxiliary Control Register UACRn Table 23 8 UACRn Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 IEC Input enable control 0 Setting the corresponding UIPCRn bit has no effect on UISRn CO...

Page 488: ...the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of a received break 1 FFULL RxRDY RxRDY receiver ready if UMR1n FFULL RxRDY 0 FIFO full FFULL if UMR1n FFULL RxRDY 1 Duplicate of USRn FFULL RxRDY If FFULL is enabled for UART0 or UART1 DMA channels 2 or 3 are respectively interrupted when the FIFO is full 0 TxRDY Transmitter ready This bit is the duplication of ...

Page 489: ...e 23 15 Table 23 11 describes UOP1 and UOP0 fields 7 1 0 Field CTS Reset 1111_1111 R W R Address IPSBAR 0x234 UIP0 0x274 UIP1 0x2B4 UIP2 Figure 23 14 UART Input Port Register UIPn Table 23 10 UIPn Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 CTS Current state of clear to send The CTS value is latched and reflects the state of the input pin when UIPn is read Note This b...

Page 490: ...ons Table 23 11 UOP1 UOP0 Field Descriptions Bits Name Description 7 1 Reserved should be cleared 0 RTS Output port output Controls assertion UOP1 negation UOP0 of RTS output 0 Not affected 1 Asserts RTS with a write to UOP1 Negates RTS with a write to UOP0 ...

Page 491: ...figured to automatically transfer data by using the DMA rather than interrupting the core When the FIFO has data on the receive path a DMA request can be issued For more information on generating DMA requests refer to Section 23 5 6 1 2 Setting up the UART to Request DMA Service and Section 16 2 DMA Request Control DMAREQC Table 23 12 briefly describes the UART module signals NOTE The terms assert...

Page 492: ...signal on the DTINn pin that can be divided by 16 When not divided DTINn provides a synchronous clock mode when divided by 16 it is asynchronous Table 23 12 UART Module Signals Signal Description Transmitter Serial Data Output UTXDn UTXDn is held high mark condition when the transmitter is disabled idle or operating in the local loop back mode Data is shifted out on UTXDn on the falling edge of th...

Page 493: ...e 23 5 1 2 Calculating Baud Rates The following sections describe how to calculate baud rates 23 5 1 2 1 System Clock Baud Rates When the system clock is the UART clocking source it goes through a divide by 32 prescaler and then passes through the 16 bit divider of the concatenated UBG1n and UBG2n registers The baud rate calculation is as follows Using a 66MHz system clock and letting baud rate 96...

Page 494: ...nal Diagram 23 5 2 1 Transmitter The transmitter is enabled through the UART command register UCRn When it is ready to accept a character the UART sets USRn TxRDY The transmitter converts parallel data Divider 66MHz 32 x 9600 215 decimal 00D6 hexadecimal Baudrate Externalclockfrequency 16or1 16bitdivider Receiver Shift Register UART Command Register UCRn W UART Status Register USRn R Transmitter S...

Page 495: ...UART Command Registers UCRn The transmitter is reenabled through the UCRn to resume operation after a disable or software reset If the clear to send operation is enabled UCTSn must be asserted for the character to be transmitted If UCTSn is negated in the middle of a transmission the character in the shift register is sent and UTXD remains in mark state until UCTSn is reasserted If the transmitter...

Page 496: ...t bit is assumed and the receiver continues sampling the input at one bit time intervals at the theoretical center of the bit until the proper number of data bits and parity if any is assembled and one stop bit is detected Data on the URXD input is sampled on the rising edge of the programmed clock source The lsb is received first The data is then transferred to a receiver holding register and USR...

Page 497: ...eak in the middle of a character if the break persists through the next character time If the break begins in the middle of a character the receiver places the damaged character in the Rx FIFO stack and sets the corresponding USRn error bits and USRn RxRDY Then if the break lasts until the next character time the receiver places an all zero character into the Rx FIFO and sets USRn RB RxRDY Figure ...

Page 498: ...updated as characters reach the top of the FIFO stack Block mode offers a data reception speed advantage where the software overhead of error checking each character cannot be tolerated However errors are not detected until the check is performed at the end of an entire message the faulting character is not identified In either mode reading the USRn does not affect the FIFO The FIFO is popped only...

Page 499: ...ck and re sent on UTXD The receiver must be enabled but the transmitter need not be Figure 23 22 Automatic Echo Because the transmitter is inactive USRn TxEMP TxRDY are inactive and data is sent as it is received Received parity is checked but is not recalculated for transmission Character framing is also checked but stop bits are sent as they are received A received break is echoed as received un...

Page 500: ...R1n PM programs the UART to operate in a wake up mode for multidrop or multiprocessor applications In this mode a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations Although slave stations have their channel receivers disabled they continuously monitor the master s data stream When the master sends an address character the s...

Page 501: ...haracter is discarded if the received A D bit is zero data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register stack during read operations In either case the data bits are loaded into the data portion of the stack while the A D bit is loaded into the status portion of the stack normally used for a parity error USRn PE Framing err...

Page 502: ...stem initialization the calling routine allocates 2 words on the system stack On return to the calling routine SINIT passes UART status data on the stack If SINIT finds no errors the transmitter and receiver are enabled SINIT calls CHCHK to perform the checks When called SINIT places the UART in local loop back mode and checks for the following errors Transmitter never ready Receiver never ready P...

Page 503: ...external requests using the DMAREQC register and the source address set to the UART s receive buffer URB The UART may request DMA transfers on FIFO not empty or FIFO full The user selects the request source by setting bit 6 in the UART s mode register 1 UMR1 Setting UMR1 bit 6 0 allows DMA request on FIFO not empty while setting UMR1 bit 6 1 allows DMA requests on FIFO full The user should then se...

Page 504: ... 2 UART Module Initialization Sequence Table 23 15 shows the UART module initialization sequence Table 23 14 UART DMA Requests Register Bit Interrupt UMR1x 6 RxIRQ 0 DMA request on RxRDY 1 DMA request on FIFO full UIMRx 1 RxFIFO full will enable DMA requests Table 23 15 UART Module Initialization Sequence Register Setting UCRn Reset the receiver and transmitter Reset the mode pointer MISC 2 0 0b00...

Page 505: ... 23 31 Operation Figure 23 26 UART Mode Programming Flowchart Sheet 1 of 5 SERIAL MODULE SINIT INITIATE CHANNEL INTERRUPTS CHK1 CALL CHCHK SAVE CHANNEL STATUS ENABLE ANY ERRORS Y N ENABLE RECEIVER ASSERT REQUEST TO SEND SINITR RETURN ...

Page 506: ...f 5 CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK IS TRANSMITTER READY Y N SNDCHR RxCHK SEND CHARACTER TO TRANSMITTER HAS CHARACTER BEEN RECEIVED N Y A WAITED TOO LONG N N WAITED TOO LONG Y Y SET TRANSMITTER NEVER READY FLAG SET RECEIVER NEVER READY FLAG B ...

Page 507: ...Flowchart Sheet 3 of 5 A B B FRCHK HAVE FRAMING ERROR SET FRAMING ERROR FLAG PRCHK HAVE PARITY ERROR SET PARITY ERROR FLAG GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER SET INCORRECT CHARACTER FLAG N N Y CHRCHK Y N DISABLE TRANSMITTER RSTCHN RESTORE TO ORIGINAL MODE RETURN ...

Page 508: ...F A BREAK SIRQ ABRKI N CLEAR CHANGE IN BREAK STATUS BIT ABRKI1 N HAS END OF BREAK IRQ ARRIVED YET Y Y CLEAR CHANGE IN BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE N Y DOES CHANNEL A RECEIVER HAVE A CHARACTER INCH PLACE CHARACTER IN D0 RETURN ...

Page 509: ...MOTOROLA Chapter 23 UART Modules 23 35 Operation Figure 23 26 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH IS TRANSMITTER READY N Y SEND CHARACTER TO TRANSMITTER RETURN ...

Page 510: ...23 36 MCF5282 User s Manual MOTOROLA Operation ...

Page 511: ...aster bus it uses arbitration and collision detection to prevent data corruption in the event that multiple devices attempt to control the bus simultaneously This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly line computer 24 2 Interface Features The I2C module has the fo...

Page 512: ...ncy divider register I2FDR I2C control register I2CR I2C status register I2SR I2C data I O register I2DR These registers are described in Section 24 5 Programming Model Address Compare In Out Data Shift Start Stop Input Sync Clock Control Registers and ColdFire Interface Address Decode I2C Address Data MUX SDA SCL Address IRQ Data and Arbitration Control Register Internal Bus Register IADR I2C Fre...

Page 513: ... composed of the following parts 1 START signal When no other device is bus master both SCL and SDA lines are at logic high a device can initiate communication by sending a START signal see A in Figure 24 2 A START signal is defined as a high to low transition of SDA while SCL is high This signal denotes the beginning of a data transfer each data transfer can be several bytes long and awakens all ...

Page 514: ...e a STOP or START signal 4 STOP signal The master can terminate communication by generating a STOP signal to free the bus A STOP signal is defined as a low to high transition of SDA while SCL is at logical high F Note that a master can generate a STOP even if the slave has made an acknowledgment at which point the slave must release the bus Instead of signaling a STOP the master can repeat the STA...

Page 515: ...shorter low periods enter a high wait state during this time See Figure 24 4 When all devices involved have counted off their low period the synchronized clock SCL is released and pulled high There is then no difference between device clocks and the state of SCL so all of the devices start counting their high periods The first device to complete its high period pulls SCL low again Figure 24 4 Sync...

Page 516: ...t 31 24 23 16 15 8 7 0 0x300 I2C Address Register I2ADR p 24 6 Reserved 0x304 I2C Frequency Divider Register I2FDR p 24 7 Reserved 0x308 I2C Control Register I2CR p 24 8 Reserved 0x30C I2C Status Register I2SR p 24 9 Reserved 0x310 I2C Data I O Register I2DR p 24 10 Reserved 7 1 0 Field ADR Reset 0000_0000 R W R W Address IPSBAR 0x300 Figure 24 5 I2C Address Register I2ADR Table 24 2 I2ADR Field D...

Page 517: ... times bus signals are sampled at the prescaler frequency The serial bit clock frequency is equal to the system clock divided by the divider shown below IC Divider IC Divider IC Divider IC Divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384...

Page 518: ...ntly pending interrupt condition are not cleared 1 I2C module interrupts are enabled An I2C interrupt occurs if I2SR IIF is also set 5 MSTA Master slave mode select bit If the master loses arbitration MSTA is cleared without generating a STOP signal 0 Slave mode Changing MSTA from 1 to 0 generates a STOP and selects slave mode 1 Master mode Changing MSTA from 0 to 1 signals a START on the bus and ...

Page 519: ... calling address 5 IBB I2C bus busy bit Indicates the status of the bus 0 Bus is idle If a STOP signal is detected IBB is cleared 1 Bus is busy When START is detected IBB is set 4 IAL Arbitration lost Set by hardware in the following circumstances IAL must be cleared by software by writing zero to it SDA sampled low when the master drives high during an address or data transmit cycle SDA sampled l...

Page 520: ...CR IEN to enable the I2C bus interface system 4 Modify the I2CR to select or deselect master slave mode transmit receive mode and interrupt enable or not 1 IIF I2C interrupt Must be cleared by software by writing a zero to it in the interrupt routine 0 No I2C interrupt pending 1 An interrupt is pending which causes a processor interrupt request if IIEN 1 Set when one of the following occurs Comple...

Page 521: ...dition is built into the hardware that generates the START cycle Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions The following example signals START and transmits the first byte of data slave address CHFLAG MOVE B I2SR A0 Che...

Page 522: ... master transmitter in the interrupt routine see Figure 24 10 I2SR LEA L I2SR A7 Load effective address BCLR B 1 A7 Clear the IIF flag MOVE B I2CR A7 Push the address on stack BTST B 5 A7 check the MSTA flag BEQ S SLAVE Branch if slave mode MOVE B I2CR A7 Push the address on stack BTST B 4 A7 check the mode flag BEQ S RECEIVE Branch if in receive mode MOVE B I2SR A7 Push the address on stack BTST ...

Page 523: ...ESTART BSET B 2 A7 MOVE B A7 I2CR MOVE B CALLING A7 Transmit the calling address D0 R W MOVE B CALLING A7 MOVE B A7 I2DR 24 6 6 Slave Mode In the slave interrupt service routine software should poll the I2SR IAAS bit to determine if the controller has received its slave address If IAAS is set software should set the transmit receive mode select bit I2CR MTX according to the I2SR SRW Writing to the...

Page 524: ... end of the byte during which arbitration is lost An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR IAL 1 and I2CR MSTA 0 If a device that is not a master tries to transmit or do a START hardware inhibits the transmission clears MSTA without signalling a STOP generates an interrupt to the CPU and sets IAL to indicate a failed attempt to engage the bus When consi...

Page 525: ... from I2DR Generate STOP Signal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1 Tx Rx Set TX Mode Write Data to I2DR Set RX Mode Dummy Read from I2DR ACK from Receiver Tx Next Byte Read Data from I2DR and Store Switch to Rx Mode Dummy Read from I2DR RTE Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX R...

Page 526: ...24 16 MCF5282 User s Manual MOTOROLA I2C Programming Examples ...

Page 527: ...ion in the EMI environment of a vehicle cost effectiveness and required bandwidth A general working knowledge of the CAN protocol revision 2 0 is assumed in this document For details refer to the CAN protocol revision 2 0 specification 25 1 Features Based on and includes all existing Motorola TouCAN module features Motorola IP interface architecture Full implementation of the CAN protocol specific...

Page 528: ...ure Multimaster bus High immunity to EMI Short latency time for high priority messages Low power sleep mode with programmable wake up on bus activity A block diagram describing the various submodules of the FlexCAN module is shown in Figure 25 1 Each submodule is described in detail in subsequent sections Figure 25 1 FlexCAN Block Diagram and Pinout MB0 MB2 MB1 MB3 MB12 MB14 MB13 MB15 0 25k 0 5KB ...

Page 529: ...ed of two signals CANTX which is the serial transmitted data and CANRX which is the serial received data IPSBAR Offset 31 24 23 16 15 8 7 0 0x1C_0000 Module Configuration Register MCR Reserved 0x1C_0004 Reserved Control Register 0 CANCTRL0 Control Register 1 CANCTRL1 0x1C_0008 Prescaler Divider PRESDIV Control Register 2 CANCTRL2 Free Running Timer TIMER 0x1C_000C Reserved Reserved 0x1C_0010 Rx Gl...

Page 530: ... waveshaping and receive compare functions required for communicating on the CAN bus It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or defective stations 25 3 Message Buffers 25 3 1 Message Buffer Structure Figure 25 3 shows the extended 29 bit ID message buffer structure Figure 25 4 displays the standard 11 bit ID message buffer structure CAN Bus FlexCA...

Page 531: ...dentifier format frames 15 8 7 4 3 0 0x0 TIME STAMP CODE LENGTH CONTROL STATUS 0x2 ID 28 18 SRR IDE ID 17 15 ID_HIGH 0x4 ID 14 0 RTR ID_LOW 0x6 DATA BYTE 0 DATA BYTE 1 0x8 DATA BYTE 2 DATA BYTE 3 0xA DATA BYTE 4 DATA BYTE 5 0xC DATA BYTE 6 DATA BYTE 7 0xE Reserved 15 8 7 4 3 0 0x0 TIME STAMP CODE LENGTH CONTROL STATUS 0x2 ID 28 18 RTR 0 0 0 0 ID_HIGH 0x4 16 BIT TIME STAMP ID_LOW 0x6 DATA BYTE 0 DA...

Page 532: ...er Codes for Receive Buffers Rx Code Before Rx New Frame Description Rx Code After Rx New Frame Comment 0000 NOT ACTIVE message buffer is not active 0100 EMPTY message buffer is active and empty 0010 0010 FULL message buffer is full 0110 If a CPU read occurs before the new frame new receive code is 0010 0110 OVERRUN second frame was received into a full buffer before the CPU read the first one 010...

Page 533: ...essage buffer ID 14 0 Bits 14 0 of the extended identifier located in the ID LOW word of the message buffer Remote Transmission Request RTR This bit is located in the least significant bit of the ID LOW word of the message buffer 0 Data Frame 1 Remote Frame Table 25 6 Standard Format Frames Field Description ID 28 18 Contains bits 28 18 of the identifier located in the ID HIGH word of the message ...

Page 534: ...cessful completion of either transmission or reception NOTE Note that for both processes the first CPU action in preparing a MB should be to deactivate it by setting its code field to the proper value This requirement is mandatory to assure proper operation ID_HIGH ID_LOW Control Status Reserved 8 bytes Data field 0x80 0x8F 0x82 0x84 0x86 Message Buffer 0 Message Buffer 1 Message Buffer 2 Message ...

Page 535: ... value At the end of the successful transmission the value of the free running timer which was captured at the beginning of the Identifier field on the CAN bus is written into the Time Stamp field in the MB the Code field in the Control Status word of the MB is updated and a status flag is set in the IFLAG register 25 4 2 Receive Process The CPU prepares or changes an MB for frame reception by exe...

Page 536: ...the MB Note that the received identifier field is always stored in the matching MB thus the contents of the identifier field in a MB may change if the match was due to mask 25 4 2 1 Self Received Frames The FlexCAN receives self transmitted frames if there exists a matching receive MB 25 4 3 Message Buffer Handling In order to maintain data coherency and proper FlexCAN operation the CPU must obey ...

Page 537: ...deactivates the transmit message buffer after the message is transferred to the SMB the message will be transmitted but no interrupt will be requested and the transmit code will not be updated If a message buffer containing the lowest ID is deactivated while that message is undergoing the internal arbitration process to determine which message should be sent then that message may not be transmitte...

Page 538: ...hile a message buffer with a matching ID is locked the last received frame with that ID is kept within the serial message buffer while all preceding ones are lost There is no indication when this occurs 6 If the user reads the control status word of a receive message buffer while a frame is being transferred from a serial message buffer the BUSY code will be indicated The user should wait until th...

Page 539: ...in the first or second bit of intermission Detection of a dominant bit in the seventh last bit of the end of frame EOF field in receive frames Detection of a dominant bit in the eighth last bit of the error frame delimiter or overload frame delimiter 25 4 6 Time Stamp The value of the free running 16 bit timer is sampled at the beginning of the identifier field on the CAN bus For a message being r...

Page 540: ...processing time IPT equals three time quanta otherwise it equals two time quanta If PSEG2 equals two then the FlexCAN transmits one time quantum late relative to the scheduled sync segment If the prescaler and bit timing control fields are programmed to values that result in fewer than ten system clock periods per CAN bit time and the CAN bus loading is 100 anytime the rising edge of a start of fr...

Page 541: ...t Error Passive state If the FlexCAN state is Error Passive and either TXCTR counter or RXCTR then decrements to a value less than or equal to 127 while the other already satisfies this condition the ESTAT FCS field is updated to reflect it set Error Active state If the value of the TXCTR increases to be greater than 255 the ESTAT FCS field is updated to reflect it set Bus Off state and an interru...

Page 542: ... 2 c Select the S clock rate by programming the PRESDIV register d Select the internal arbitration mode LBUF bit in CANCTRL1 2 Initialize message buffers a The control status word of all message buffers must be written either as an active or inactive message buffer b All other entries in each message buffer should be initialized as required 3 Initialize mask registers for acceptance mask as needed...

Page 543: ...mechanisms to place the FlexCAN in debug mode the user must wait for the FRZACK bit to be set before accessing any other registers in the FlexCAN otherwise unpredictable operation may occur To exit debug mode the BKPT line must be negated or the HALT bit in CANMCR must be cleared Once debug mode is exited the FlexCAN will resynchronize with the CAN bus by waiting for 11 consecutive recessive bits ...

Page 544: ...tering low power stop mode Otherwise it may be interrupted while in STOP mode upon a non wake up condition If desired the WAKEMASK bit should be set to enable the WAKEINT If the STOP bit is set while the FlexCAN is in the bus off state then the FlexCAN will enter low power stop mode and stop counting recessive bit times The count will continue when STOP is cleared To place the FlexCAN in low power...

Page 545: ...ve to dominant edge 25 4 11 3 Auto Power Save Mode Auto power save mode enables normal operation with optimized power savings Once the auto power save APS bit in CANMCR is set the FlexCAN looks for a set of conditions in which there is no need for its clocks to be running If these conditions are met the FlexCAN stops its clocks thus saving power The following conditions will activate auto power sa...

Page 546: ... The FlexCAN has no hard wired protection against invalid bit field programming within its registers Specifically no protection is provided if the programming does not meet CAN protocol requirements Programming the FlexCAN control registers is typically done during system initialization prior to the FlexCAN becoming synchronized with the CAN bus The configuration registers can be changed after syn...

Page 547: ... enters low power stop mode or debug mode It is cleared once the FlexCAN exits either mode either by synchronization to the CAN bus or by the self wake mechanism 0 FlexCAN has exited low power stop mode or debug mode 1 FlexCAN is in low power stop mode or debug mode 10 WAKEMSK Wakeup interrupt mask The WAKEMSK bit enables wake up interrupt requests 0 Wake up interrupt is disabled 1 Wake up interru...

Page 548: ...reading CANMCR Refer to Section 25 4 11 2 Low Power Stop Mode for Power Saving for more information on entry into and exit from low power stop mode 0 Self wake disabled 1 Self wake enabled 5 APS Auto power save The APS bit allows the FlexCAN to automatically shut off its clocks to save power when it has no process to execute and to automatically restart these clocks when it has a task to execute w...

Page 549: ...d as a recessive bit 1 0 TXMODE Transmit pin configuration control This bit field controls the configuration of the CANTX pin See Table 25 10 Table 25 10 Transmit Pin Configuration TXMODE 1 0 Transmit Pin Configuration 00 Full CMOS 1 positive polarity CANTX 0 is a dominant level 1 Full CMOS drive indicates that both dominant and recessive levels are driven by the chip 01 Full CMOS1 negative polari...

Page 550: ...CAN stations with a special SYNC message global network time 0 Timer synchronization disabled 1 Timer synchronization enabled Note there can be a bit clock skew of four to five counts between different FlexCAN modules that are using this feature on the same network 4 LBUF Lowest buffer transmitted first The LBUF bit defines the transmit first scheme 0 Message buffer with lowest ID is transmitted f...

Page 551: ...ANCTRL2 Table 25 13 CANCTRL2 Field Descriptions Bits Name Description 7 6 RJW Resynchronization jump width The RJW field defines the maximum number of time quanta a bit time may be changed during resynchronization The valid programmed values are 0 through 3 The resynchronization jump width is calculated as follows Resynchronizaton Jump Width RJW 1 Time Quanta 5 3 PSEG1 PSEG1 2 0 Phase buffer segme...

Page 552: ...ss IPSBAR 0x1C_000A Figure 25 11 Free Running Timer TIMER Table 25 14 TIMER Field Descriptions Bits Name Description 15 0 TIMER The free running timer counter can be read and written by the CPU The timer starts from zero after reset counts linearly to 0xFFFF and wraps around The timer is clocked by the FlexCAN bit clock During a message it increments by one for each bit that is received or transmi...

Page 553: ... 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5 Rx_14_Mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 Rx_Msg in 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 Rx_Msg in 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14 7 1 Match for Extended Format MB3 2 Match for Standard Format MB2 3 Un Match for MB3 because of ID0 4 Un Match for MB2 because of I...

Page 554: ...d Its location in the mask bit 19 is always 1 regardless of any CPU write to this bit 19 Reserved The RTR SRR bit of a received frame is never compared to the corresponding bit in the MB ID field Note however that remote request frames RTR 1 are never received into MBs RTR mask bits locations in the mask bits 20 and 0 are always read as 0 regardless of any CPU write to these bits 18 1 MID Mask ID ...

Page 555: ...e the last read of this register 10 STUFERR Bit stuff error The STUFFERR bit indicates whether or not the bit stuffing that occurred in the last transmitted or received message was correct 0 No bit stuffing error was detected since the last read of this register 1 A bit stuffing error was detected since the last read of this register 9 TXWARN Transmit error status flag The TXWARN status flag refle...

Page 556: ...ERRINT Error interrupt The ERRINT bit is used to request an interrupt when the FlexCAN detects a transmit or receive error 0 No error interrupt request 1 If an event which causes one of the error bits in the error and status register to be set occurs the error interrupt bit is set If the ERRMSK bit in CANCTRL0 is set an interrupt request is generated To clear this bit first read it as a one then w...

Page 557: ...nding buffer is disabled 1 The interrupt for the corresponding buffer is enabled 15 14 13 12 11 10 9 8 Field BUF15I BUF14I BUF13I BUF1I BUF11I BUF10I BUF9I BUF8I Reset 0000_0000 R W R w 7 6 5 4 3 0 Field BUF7I BUF6I BUF5I BUF4I BUF3I BUF2I BUF1I BUF0I Reset 0000_0000 R W R W Address IPSBAR 0x1C_0024 Figure 25 15 Interrupt Flag Register IFLAG Table 25 19 IFLAG Field Descriptions Bits Name Descripti...

Page 558: ...RXECTR Field Descriptions Bits Name Description 7 0 RXECTR Receive error counter Indicates the current receive error count as defined in the CAN protocol See Section 25 4 9 FlexCAN Error Counters for more details 7 0 Field TXECTR Reset 0000_0000 R W R Address IPSBAR 0x1C_0028 Figure 25 17 FlexCAN Transmit Error Counter TXECTR Table 25 21 TXECTR Field Descriptions Bits Name Description 7 0 TXECTR T...

Page 559: ...e to access off chip resources When not used for their primary function many of the pins may be used as general purpose digital I O pins In some cases the pin function is set by the operating mode and the alternate pin functions are not supported The digital I O pins on the MCF5282 are grouped into 8 bit ports Some ports do not use all eight bits Each port has registers that configure monitor and ...

Page 560: ...XER PEL 4 ERXD 3 PEL 3 ERXD 2 PEL 2 ERXD 1 PEL 1 ERXER PEL 0 EMDIO PAS5 URXD2 EMDC PAS4 UTXD2 CANRX PAS3 URXD2 CANTX PAS2 UTXD2 SDA PAS1 URXD2 SCL PAS0 UTXD2 QSPI_CLK PQS2 QSPI_DIN PQS1 QSPI_DOUT PQS0 QSPI_CS 3 0 PQS 6 3 SRAS PSD5 SCAS PSD4 DRAMW PSD3 SCKE PSD0 SDRAM_CS 1 0 DTIN3 PTC 3 URTS1 URTS0 DTIN2 PTC 1 UCTS1 UCTS0 DTOUT2 PTC 0 UCTS1 UCTS0 DTIN1 PTD 3 URTS1 URTS0 DTOUT1 PTD 2 URTS1 URTS0 DTI...

Page 561: ...al I O support for all ports Registers for storing output pin data Registers for controlling pin data direction Registers for reading current pin state Registers for setting and clearing output pin data registers 26 1 3 Modes of Operation The operational modes for the MCF5282 ports are listed below For more detailed descriptions of each mode refer to Section 26 4 Functional Description Single chip...

Page 562: ...er start indication for external data transfer Port E 1 Timer A sync TIP1 PE 0 SYNCB Transfer in progress indication for external data transfer Port E 0 Timer B sync A 23 21 1 PF 7 5 CS 6 4 External address bus 23 21 Port F 7 5 Chip selects 6 4 A 20 0 1 PF 4 0 PG PH External address bus 20 0 Ports F 4 0 G H BS 3 0 1 PJ 7 4 Byte strobes for external data transfer Port J 7 4 SDRAM column address str...

Page 563: ...utput Port QS 0 SRAS PSD 5 SDRAM synchronous row address strobe Port SD 5 SCAS PSD 4 SDRAM synchronous column address strobe Port SD 4 DRAMW PSD 3 SDRAM write enable Port SD 3 SDRAM_CS 1 0 PSD 2 1 SDRAM row address strobes 1 0 Port SD 2 1 SCKE PSD 0 SDRAM clock enable Port SD 0 GPTA 3 0 2 PTA 3 0 General purpose timer A input output Port TA 3 0 GPTB 3 0 2 PTB 3 0 General purpose timer B input outp...

Page 564: ... data Port UA 2 URXD0 PUA 1 UART0 receive serial data Port UA 1 UTXD0 PUA 0 UART0 transmit serial data Port UA 0 1 The primary functionality of a pin is not necessarily the default function of the pin after reset Pins that have muxed GPIO functionality will default to GPIO inputs 2 Function available in master mode only 3 Pins not actually part of Port Module but included here for complete listing...

Page 565: ... S U 0x10_0038 PORTTDP SETTD PORTUAP SETUA Reserved2 S U Port Clear Output Data Registers 0x10_003C CLRA CLRB CLRC CLRD S U 0x10_0040 CLRE CLRF CLRG CLRH S U 0x10_0044 CLRJ CLRDD CLREH CLREL S U 0x10_0048 CLRAS CLRQS CLRSD CLRTC S U 0x10_004C CLRTD CLRUA Reserved2 S U Port Pin Assignment Registers 0x10_0050 PBCDPAR PFPAR PEPAR S U 0x10_0054 PJPAR PSDPAR PASPAR S U 0x10_0058 PEHLPAR PQSPAR PTCPAR P...

Page 566: ...tting the corresponding bits in the PORTnP SETn register They can be cleared by clearing the PORTn register or by clearing the corresponding bits in the CLRn register 7 6 5 4 3 2 1 0 Field PORTn7 PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 PORTn0 Reset 1111_1111 R W R W Address IPSBAR 0x10_0000 PORTA 0x10_0001 PORTB 0x10_0002 PORTC 0x10_0003 PORTD 0x10_0004 PORTE 0x10_0005 PORTF 0x10_0006 PORTG 0x10...

Page 567: ...ponding pin as an input 7 4 3 2 1 0 Field PORTn3 PORTn2 PORTn1 PORTn0 Reset 0000_1111 R W R R W Address IPSBAR 0x10_000F PORTTC 0x10_0010 PORTTD 0x10_0011 PORTUA Figure 26 5 Port Output Data Registers 4 bit Table 26 3 PORTn 8 bit 7 bit 6 bit and 4 bit Field Descriptions Register Bits Name Description 8 bit 7 0 PORTnx Port output data bits 1 Drives 1 when the port n pin is a digital output 0 Drives...

Page 568: ...DDRAS 0x10_0022 DDRSD Figure 26 8 Port Data Direction Registers 6 bit 7 4 3 2 1 0 Field DDRn3 DDRn2 DDRn1 DDRn0 Reset 0000_0000 R W R R W Address IPSBAR 0x10_0023 DDRTC 0x10_0024 DDRTD 0x10_0025 DDRUA Figure 26 9 Port Data Direction Registers 4 bit Table 26 4 DDRn 8 bit 6 bit and 4 bit Field Descriptions Register Bits Name Description 8 bit 7 0 DDRnx Port n data direction bits 1 Port n pin configu...

Page 569: ... 3 2 1 0 Field PORTnP7 SETn7 PORTnP6 SETn6 PORTnP5 SETn5 PORTnP4 SETn4 PORTnP3 SETn3 PORTnP2 SETn2 PORTnP1 SETn1 PORTnP0 SETn0 Reset Current Pin State R W R W Address IPSBAR 0x10_0028 PORTAP SETA 0x10_0029 PORTBP SETB 0x10_002A PORTCP SETC 0x10_002B PORTDP SETD 0x10_002C PORTEP SETE 0x10_002D PORTFP SETF 0x10_002E PORTGP SETG 0x10_002F PORTHP SETH 0x10_0030 PORTJP SETJ 0x10_0031 PORTDDP SETDD 0x10...

Page 570: ...t 0000 Current Pin State R W R W Address IPSBAR 0x10_0037 PORTTCP SETTC 0x10_0038 PORTTDP SETTD 0x10_0039 PORTUAP SETUA Figure 26 13 Port Pin Data Set Data Registers 4 bit Table 26 5 PORTnP SETn 8 bit 6 bit and 4 bit Field Descriptions Register Bits Name Description 8 bit 7 0 PORTxnP SETxn Port x Pin Data Set Data Bits 1 Port x pin state is 1 read set corresponding PORTx bit write 0 Port x pin sta...

Page 571: ...48 CLRAS 0x10_004A CLRSD Figure 26 16 Port Clear Output Data Registers 6 bit 7 4 3 2 1 0 Field CLRn3 CLRn2 CLRn1 CLRn0 Reset 0000_0000 R W R R W Address IPSBAR 0x10_004B CLRTC 0x10_004C CLRTD 0x10_004D CLRUA Figure 26 17 Port Clear Output Data Registers 4 bit Table 26 6 CLRn 8 bit 7 bit 6 bit and 4 bit Field Descriptions Register Bits Name Description 8 bit 7 0 CLRnx Port n clear output data regis...

Page 572: ...gital I O 1 Port B pins configured for primary function D 23 16 0 Port B pins configured for digital I O 6 PCDPA Ports C D pin assignment Configures the port C and D pins for their primary functions D 15 8 D 7 0 or digital I O 1 Port C D pins configured for primary function D 15 8 D 7 0 0 Port C D pins configured for digital I O 5 0 Reserved should be cleared Table 26 8 Reset Values for PBCDPAR Bi...

Page 573: ...ield Descriptions Bits Name Description 14 PEPA7 Port E pin assignment 7 This bit configures the port E7 pin for its primary function OE or digital I O 1 Port E7 pin configured for primary function OE 0 Port E7 pin configured for digital I O 12 PEPA6 Port E pin assignment 6 This bit configures the port E6 pin for its primary function TA or digital I O 1 Port E6 pin configured for primary function ...

Page 574: ... enabled by the SZEN bit in the CCR register Please refer to the Chapter 30 Chip Configuration Module CCM for more information on chip configuration and the SZEN bit 3 2 PEPA1 Port E pin assignment 1 This two bit field in PEPAR 3 2 configures the port E1 pin for its primary function TS alternate function SYNCA or digital I O 0x Port E1 pin configured for digital I O 10 Port E1 pin configured for a...

Page 575: ... Port F7 pin configured for digital I O Refer to Chapter 30 Chip Configuration Module CCM for more information on reset configuration 6 PFPA6 Port F pin assignment 6 The PFPA6 bit configures the port F6 pin for its primary function A22 alternate function CS5 or digital I O 1 Port F6 pin configured for primary function A22 or alternate function CS5 depending on the chip configuration 0 Port F6 pin ...

Page 576: ... for its primary function BS1 or digital I O 1 Port J5 pin configured for its primary function BS1 0 Port J5 pin configured for digital I O 4 PJPA4 Port J pin assignment 4 This bit configures the port J4 pin for its primary function BS0 or digital I O 1 Port J4 pin configured for its primary function BS0 0 Port J4 pin configured for digital I O 3 PJPA3 Port J pin assignment 3 This bit configures t...

Page 577: ...R 0x10_0055 Figure 26 22 Port SD Pin Assignment Register PSDPAR Table 26 13 PSDPAR Field Descriptions Bits Name Description 7 PSDPA Port SD pin assignment This bit configures the port SD 5 0 pins for their primary functions SRAS SCAS DRAMW SDRAM_CS 1 0 SCKE or digital I O 1 Port SD 5 0 pins configured for primary functions SRAS SCAS DRAMW SDRAM_CS 1 0 SCKE 0 Port SD 5 0 pin configured for digital ...

Page 578: ...alternate function URXD2 or digital I O 0x Port AS3 pin configured for digital I 0 10 Port AS3 pin configured for alternate function URXD2 11 Port AS3 pin configured for primary function CANRX 5 4 PASPA2 Port AS pin assignment 2 These bits configure the AS2 pin for its primary function CANTX alternate function UTXD2 or digital I O 0x Port AS2 pin configured for digital I 0 10 Port AS2 pin configur...

Page 579: ...PA6 PQSPA5 PQSPA4 PQSPA3 PQSPA2 PQSPA1 PQSPA0 Reset 0000_0000 R W R R W Address IPSBAR 0x10_0059 Figure 26 25 Port QS Pin Assignment Register PQSPAR Table 26 16 PQSPAR Field Description Bits Name Description 7 Reserved should be cleared 6 PQSPA6 Port QS pin assignment 6 This bit configures the port QS6 pin for its primary function QSPI_CS3 or digital I O 1 Port QS6 pin configured for primary funct...

Page 580: ...ield PTCPA3 PTCPA2 PTCPA1 PTCPA0 Reset 0000_0000 R W R W Address IPSBAR 0x10_005A Figure 26 26 Port TC Pin Assignment Register PTCPAR Table 26 17 PTCPAR Field Descriptions Bits Name Description 7 6 PTCPA3 Port TC pin assignment 3 This field configures the port TC3 pin for its primary function DTIN3 alternate 1 function URTS1 alternate 2 function URTS0 or digital I O 00 Port TC3 pin configured for ...

Page 581: ...ort TC0 pin configured for primary function DTOUT2 7 6 5 4 3 2 1 0 Field PTDPA3 PTDPA2 PTDPA1 PTDPA0 Reset 0000_0000 R W R W Address IPSBAR 0x10_005B Figure 26 27 Port TD Pin Assignment Register PTDPAR Table 26 18 PTDPAR Field Descriptions Bits Name Description 7 6 PTDPA3 Port TD pin assignment 3 This field configures the port TD3 pin for its primary function DTIN1 alternate 1 function URTS1 alter...

Page 582: ...2 1 0 Field PUAPA3 PUAPA2 PUAPA1 PUAPA0 Reset 0000_0000 R W R R W Address IPSBAR 0x10_005C Figure 26 28 Port UA Pin Assignment Register PUAPAR Table 26 19 PUAPAR Field Descriptions Bits Name Description 7 4 Reserved should be cleared 3 PUAPA3 Port UA pin assignment 3 This bit configures the port UA3 pin for its primary function URXD1 or digital I O 1 Port UA3 pin configured for primary function UR...

Page 583: ...ored and then driven to the corresponding port n pins configured as outputs Reading a PORTn register returns the current state of the register regardless of the state of the corresponding pins Reading a PORTnP PSETn register returns the current state of the corresponding pins when configured as digital I O regardless of whether the pins are inputs or outputs Every port has a PORTnP SETn register a...

Page 584: ...0 Digital Output Timing 26 5 Initialization Application Information The initialization for the MCF5282 ports module is done during reset configuration Some of the registers are reset to a predetermined state and others are reset according to which mode of operation is chosen by reset configuration Refer to Section 26 3 Memory Map Register Definition for more details on reset and initialization CLK...

Page 585: ... and status registers the conversion command word CCW table random access memory RAM and the result table RAM The bus interface unit BIU provides access to registers that configure the QADC control the analog to digital converter and queue mechanism and present formatted conversion results 27 1 Features Features of the QADC module include Internal sample and hold Up to eight analog input channels ...

Page 586: ...ied signed Left justified unsigned Unused analog channels can be used as discrete input output pins 27 2 Block Diagram Figure 27 1 QADC Block Diagram Digital External External Reference Analog Power 64 Entry Queue Control of 10 bit Conversion Command Words IPBUS Interface 10 bit Analog to Digital Converter Analog Input MUX and Digital Signal Functions 64 Entry Table of 10 bit 10 bit to 16 bit Resu...

Page 587: ... QADC completes the current conversion and then freezes If during the execution of the current conversion the queue operating mode for the active queue is changed or a queue 2 abort occurs the QADC freezes immediately When the QADC enters debug mode while a queue is active the current CCW location of the queue pointer is saved Debug mode Stops the analog clock Holds the periodic interval timer in ...

Page 588: ...es some recovery time tSR to stabilize the analog circuits 27 4 Signals The QADC uses the external signals shown in Figure 27 2 There are eight channel port signals that can support up to 18 channels when external multiplexing is used including internal channels All of the channel signals also have some general purpose input or input output GPIO functionality In addition there are also two analog ...

Page 589: ...ad from the port QA data register PORTQA when DDRQA specifies that the signals are inputs The digital data in PORTQA is driven onto the port QA signals when the corresponding bits in DDRQA specify output See Section 27 6 4 27 4 2 Port QB Signal Functions The four port QB signals can be used as analog inputs or as a 4 bit digital I O port 27 4 2 1 Port QB Analog Input Signals When used as analog in...

Page 590: ... bit in QADC control register 0 QACR0 When TRG 0 ETRIG1 triggers queue 1 and ETRIG2 triggers queue 2 When TRG 1 ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1 See Section 27 6 5 Control Registers 27 4 4 Multiplexed Address Output Signals In non multiplexed mode the QADC analog input signals are connected to an internal multiplexer which routes the analog signals into the internal A D converte...

Page 591: ...m the normal levels of noise present on the digital power supply 27 4 8 Dedicated Digital I O Port Supply Signal VDDH provides 5 V power to the digital I O functions of QADC port QA and port QB This allows those signals to tolerate 5 volts when configured as inputs and drive 5 volts when configured as outputs 27 5 Memory Map The QADC occupies 1 Kbyte or 512 half word 16 bit entries of address spac...

Page 592: ...n access termination transfer error if not in test mode S 0x19_0004 Reserved 3 3 Read writes have no effect and the access terminates with a transfer error exception 0x19_0006 Port QA Data Register PORTQA Port QB Data Register PORTQB S U 0x19_0008 Port QA Data Direction Register DDRQA Port QB Data Direction Register DDRQB S U 0x19_000a QADC Control Register 0 QACR0 S U 0x19_000c QADC Control Regis...

Page 593: ...al input only port Port QB can also be used for non multiplexed AN 3 0 and multiplexed ANZ ANY ANX ANW analog inputs PORTQA and PORTQB are not initialized by reset 7 6 0 Field SUPV Reset 1000_0000 R W R W R Address IPSBAR 0x19_0000 0x19_0001 Figure 27 3 QADC Module Configuration Register QADCMCR Table 27 3 QADCMCR Field Descriptions Bit s Name Description 15 QSTOP Stop enable 1 Force QADC to idle ...

Page 594: ...orresponding to PQA 1 0 and the two multiplexed address MA 1 0 output signals The MA 1 0 signals are forced to be digital outputs regardless of their data direction setting and the multiplexed address outputs are driven The data returned during a port data register read is the value of the MA 1 0 signals regardless of their data direction setting Similarly when the external trigger signals are ass...

Page 595: ...ablishes the QADC sampling clock QCLK with prescaler parameter fields and defines whether external multiplexing is enabled Typically these bits are written once when the QADC is initialized and not changed thereafter The bits in this register are read anytime write anytime except during stop mode 7 6 5 4 3 2 1 0 Field DDQA4 DDQA3 DDQA1 DDQA0 Reset 0000_0000 R W R R W R R W Address IPSBAR 0x19_0008...

Page 596: ...plexed up to 18 possible channels 0 Internally multiplexed up to 8 possible channels 14 13 Reserved should be cleared 12 TRG Trigger assignment Determines the queue assignment of the ETRIG 2 1 signals 1 ETRIG1 triggers queue 2 ETRIG2 triggers queue 1 0 ETRIG1 triggers queue 1 ETRIG2 triggers queue 2 11 7 Reserved should be cleared 6 0 QPR Prescaler clock divider Selects the system clock divisor to...

Page 597: ...52 1101011 216 0001100 26 0101100 90 1001100 154 1101100 218 0001101 28 0101101 92 1001101 156 1101101 220 0001110 30 0101110 94 1001110 158 1101110 222 0001111 32 0101111 96 1001111 160 1101111 224 0010000 34 0110000 98 1010000 162 1110000 226 0010001 36 0110001 100 1010001 164 1110001 228 0010010 38 0110010 102 1010010 166 1110010 230 0010011 40 0110011 104 1010011 168 1110011 232 0010100 42 011...

Page 598: ... 1 Enable queue 1 completion interrupt 0 Disable queue 1 completion interrupt 14 PIE1 Queue 1 pause interrupt enable Enables an interrupt request when queue 1 enters the pause state The interrupt request is initiated when conversion is complete for a CCW that has the pause bit set 1 Enable the queue 1 pause interrupt 0 Disable the queue 1 pause interrupt 13 SSE1 Queue 1 single scan enable Enables ...

Page 599: ...1101 Interval timer single scan mode time QCLK period 216 01110 Interval timer single scan mode time QCLK period 217 01111 Externally gated single scan mode started with SSE1 10000 Reserved mode 10001 Software triggered continuous scan mode 10010 External trigger rising edge continuous scan mode 10011 External trigger falling edge continuous scan mode 10100 Periodic timer continuous scan mode time...

Page 600: ...tually complete execution The beginning of queue 2 is defined by programming the BQ2 field in QACR2 BQ2 is usually set before or at the same time as the queue operating mode for queue 2 is selected If BQ2 6 0 64 queue 2 has no entries the entire CCW table is dedicated to queue 1 and CCW63 is the end of queue 1 If BQ2 6 0 is 0 the entire CCW table is dedicated to queue 2 A special case occurs when ...

Page 601: ...compared with the current value of the BQ2 6 0 pointer to detect a possible end of queue condition For example if BQ2 6 0 is changed to CCW3 while queue 1 is converting CCW2 queue 1 is terminated after the conversion is completed However if BQ2 6 0 is changed to CCW1 while queue 1 is converting CCW2 the QADC would not recognize a BQ2 6 0 end of queue condition until queue 1 execution reached CCW1 ...

Page 602: ... 27 9 shows the bits in the MQ1 field which enable different queue 2 operating modes 7 RESUME Selects the resumption point for queue 2 after its operation is suspended due to a queue 1 trigger event If RESUME is changed during the execution of queue 2 the change is not recognized until an end of queue condition is reached or the operating mode of queue 2 is changed 1 After suspension begin executi...

Page 603: ...single scan mode time QCLK period x 217 01111 Reserved mode 10000 Reserved mode 10001 Software triggered continuous scan mode 10010 Externally triggered rising edge continuous scan mode 10011 Externally triggered falling edge continuous scan mode 10100 Periodic timer continuous scan mode time QCLK period x 27 10101 Periodic timer continuous scan mode time QCLK period x 28 10110 Periodic timer cont...

Page 604: ...e setting PFn indicates that the results for the queue have not been collected during one scan coherently NOTE If a set CCW pause bit is encountered in either externally gated mode the pause flag will not set and execution continues without pausing This has allowed for the modified behavior of PF1 in the externally gated modes PFn is maintained by the QADC regardless of whether the corresponding i...

Page 605: ...oes not execute any CCWs from the paused queue until a trigger event occurs Consequently the QADC can service queue 2 while queue 1 is paused Only queue 2 can be in the suspended state When a trigger event occurs on queue 1 while queue 2 is executing the current queue 2 conversion is aborted and the queue 2 status is reported as suspended Queue 2 transitions back to the active state when queue 1 b...

Page 606: ... where the end of queue condition was detected Therefore when the end of queue condition is a CCW with the EOQ code channel 63 the CWP points to the CCW containing the EOQ When the last CCW in a queue is the last CCW table location CCW63 and it does not contain the EOQ code the end of queue is detected when the following CCW is read so the CWP points to word CCW0 Finally when queue 1 operation is ...

Page 607: ...ag Indicates that an unexpected trigger event has occurred for queue 1 TOR 1 2 can be set only while the queue is in the active state Once set TOR 1 2 is cleared only by a reset or by writing a 0 to it 1 At least one unexpected queue 1 trigger event has occurred or queue 1 reaches an end of queue condition for the second time in externally gated continuous scan 0 No unexpected queue 1 trigger even...

Page 608: ... queue 2 idle 0001 Queue 1 idle queue 2 paused 0010 Queue 1 idle queue 2 active 0011 Queue 1 idle queue 2 trigger pending 0100 Queue 1 paused queue 2 idle 0101 Queue 1 paused queue 2 paused 0110 Queue 1 paused queue 2 active 0111 Queue 1 paused queue 2 trigger pending 1000 Queue 1 active queue 2 idle 1001 Queue 1 active queue 2 paused 1010 Queue 1 active queue 2 suspended 1011 Queue 1 active queue...

Page 609: ...aused Q1 Active Q2 Trigger Pending Q1 Paused Q2 Trigger Pending Temporary Q2 Complete Delayed Transition Q1 Pause Bit Set Q2 Trigger Event Q1 Trigger Event Q1 Pause Bit Set Q1 Complete Q1 Trigger Event Q1 Complete Delayed Transition Q1 Complete Q1 Pause Bit Set Q1 Trigger Event Q2 Complete Q2 Pause Bit Set Q2 Trigger Event Q1 Trigger Event Q1 Complete Q1 Trigger Event Q1 Pause Bit Set Q2 Pause Bit...

Page 610: ...s to the last executed CCW in queue 1 regardless of which queue is active In contrast to CWP CPWQ1 is updated when a conversion result is written When the QADC finishes a conversion in queue 1 both the result register is written and CWPQ1 is updated When queue 1 operation is terminated after a CCW is read that is pointed to by BQ2 CWP points to BQ2 while CWPQ1 points to the last queue 1 CCW During...

Page 611: ...ses execution to continue from the pause to the next CCW 1 Enter pause state after execution of current CCW 0 Do not enter pause state after execution of current CCW NOTE The P bit does not cause the queue to pause in software initiated modes or externally gated modes 8 BYP Sample amplifier bypass Enables the amplifier bypass mode for a conversion and subsequently changes the timing The initial sa...

Page 612: ...for multiplexed mode Programming the channel field to channel 63 denotes the end of the queue Channels 60 to 62 are special internal channels When one of the special channels is selected the sampling amplifier is not used The value of VRL VRH or VRH VRL 2 is converted directly Programming any input sample time other than two has no benefit for the special internal channels except to lengthen the o...

Page 613: ...not listed are reserved or unimplemented and return undefined results Port Signal Name Analog Signal Name Other Functions Signal Type Binary Decimal PQB0 PQB1 PQB2 PQB3 ANW ANX ANY ANZ Input Input Input Input 000XX0 000XX1 010XX0 010XX1 0 2 4 6 1 3 5 7 16 18 20 22 17 19 21 23 PQA0 PQA1 MA0 MA1 Output Output 52 53 PQA3 PQA4 AN55 AN56 ETRIG1 ETRIG2 Input Output Input Output 110111 111000 55 56 VRL V...

Page 614: ...at corresponds to a half scale offset binary two s complement data format Conversion values corresponding to 1 2 full scale 0x0200 or higher are interpreted as positive values and have a sign bit of 0 An unsigned right justified conversion of 0x0200 would be represented as 0x0000 in this signed register where the sign 0 and the result 0 For an unsigned right justified conversion of 0x3FF full rang...

Page 615: ...e registers must be inactive This can be guaranteed by system operating conditions such as known completion of a software initiated queue single scan or no possibility of an externally triggered gated queue scan or by simply disabling the queues writing MQ1 and or MQ2 to 0 27 7 2 External Multiplexing External multiplexer chips concentrate a number of analog signals onto a few QADC inputs This is ...

Page 616: ...ernal multiplexer chips to expand the number of analog signals that may be converted Up to 16 analog channels can be converted through external multiplexer selection The externally multiplexed channels are automatically selected from the channel field of the CCW the same as internally multiplexed channels The QADC is configured for the externally multiplexed mode by setting the MUX bit in control ...

Page 617: ...the channel number in each CCW The QADC also converts the proper input channel ANW ANX ANY and ANZ by interpreting the CCW channel number As a result up to 16 externally multiplexed channels appear to the conversion queues as AN52 MA0 PQA0 AN53 MA1 PQA1 AN55 ETRIG1PQA3 AN56 ETRIG2 PQA4 AN0 ANW PQB0 AN1 ANX PQB1 AN2 ANY PQB2 AN3 ANZ PQB3 Port QB Port QA AN0 AN2 AN4 AN6 AN1 AN3 AN5 AN7 AN16 AN18 AN2...

Page 618: ...QADC analog subsystem which includes the front end analog multiplexer and analog to digital converter 27 7 3 1 Analog to Digital Converter Operation The analog subsystem consists of the path from the input signals to the A D converter block Signals from the queue control logic are fed to the multiplexer and state machine The end of conversion EOC signal and the successive approximation register SA...

Page 619: ... During the resolution period the voltage in the sample capacitor is converted to a digital value and stored in the SAR as shown in Figure 27 20 Initial sample time is fixed at two QCLK cycles Final sample time can be 2 4 8 or 16 QCLK cycles depending on the value of the IST field in the CCW Resolution time is 10 QCLK cycles A conversion requires a minimum of 14 QCLK cycles 7 µs with a 2 0 MHz QCL...

Page 620: ...7 21 Bypass Mode Conversion Timing 27 7 3 3 Channel Decode and Multiplexer The internal multiplexer selects one of the eight analog input signals for conversion The selected input is connected to the sample buffer amplifier or to the sample capacitor The multiplexer also includes positive and negative stress protection circuitry which prevents deselected channels from affecting the selected channe...

Page 621: ...he sample amplifier Once the end of conversion has been reached a signal is sent to the queue control logic indicating that a result is available for storage in the result RAM 27 8 Digital Control Subsystem The digital control subsystem includes the control logic to sequence the conversion activity the system clock and periodic interval timer control and status registers the conversion command wor...

Page 622: ... trigger overruns Once queue 1 reaches the completion or the paused state queue 2 begins executing again The programming of the RESUME bit in QACR2 determines which CCW is executed in queue 2 When simultaneous trigger events occur for queue 1 and queue 2 queue 1 begins execution and the queue 2 status is changed to trigger pending When subqueues are paused The pause feature can be used to divide q...

Page 623: ...ous scan mode is selected a trigger event occurring after the completion of the last subqueue after the queue completion flag is set causes the execution to continue with the first subqueue starting with the first CCW in the queue When the QADC encounters a CCW with the pause bit set the queue enters the paused state after completing the conversion specified in the CCW with the pause bit The pause...

Page 624: ...ing the execution time of each CCW in the queue In most of the situations there are four CCWs labeled C1 to C4 in both queue 1 and queue 2 In some of the situations CCW C2 is presumed to have the pause bit set to show the similarities of pause and end of queue as terminations of queue execution Trigger events are described in Table 27 22 When a trigger event causes a CCW execution in progress to b...

Page 625: ...queue In situation S1 Figure 27 23 one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event The trigger overrun error status bit is set and the premature trigger event is otherwise ignored A trigger event that occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress ...

Page 626: ...n 3 The next two situations consider trigger events that occur for the lower priority queue 2 while queue 1 is actively being serviced Situation S4 Figure 27 26 shows that a queue 2 trigger event is recognized while queue 1 is active is saved and as soon as queue 1 is finished queue 2 servicing begins T1 ACTIVE IDLE Q1 Q2 QS IDLE ACTIVE IDLE ACTIVE IDLE 1000 1000 0000 0010 0000 C1 C2 C3 C4 TOR2 T2...

Page 627: ...urring during queue 2 execution Because queue 1 has higher priority the conversion taking place in queue 2 is aborted so that there is no variable latency time in responding to queue 1 trigger events In situation 6 Figure 27 28 the conversion initiated by the second CCW in queue 2 is aborted just before the conversion is complete so that queue 1 execution can begin Queue 2 is considered suspended ...

Page 628: ...same two situations with the RESUME bit set to a 1 When the RESUME bit is set following suspension queue 2 resumes execution with the aborted CCW not the first CCW in the queue IDLE Q1 Q2 QS IDLE IDLE 0000 1000 ACTIVE C1 C2 T1 Q1 C1 C3 C4 IDLE Q2 PF1 PAUSE ACTIVE CF1 T1 ACTIVE SUSPEND 0100 ACTIVE ACTIVE 0110 1010 C1 C2 C3 C4 CF2 T2 0010 0000 RESUME 0 C2 T1 PAUSE Q1 Q2 QS IDLE ACTIVE IDLE ACTIVE ID...

Page 629: ...e being executed when a new trigger event occurs Trigger overrun on queue 2 thus allows the user to know that queue 1 is taking up so much QADC time that queue 2 trigger events are being lost IDLE Q1 Q2 QS IDLE IDLE 0000 1000 0010 ACTIVE C1 C2 T1 Q1 C1 C3 C4 IDLE Q2 PF1 PAUSE ACTIVE CF1 T1 ACTIVE SUSPEND 0100 ACTIVE ACTIVE 0110 1010 C2 C3 C4 CF2 T2 0000 RESUME 1 C2 T1 PAUSE Q1 Q2 QS IDLE ACTIVE ID...

Page 630: ...ess unlike the abort that occurs when queue 1 suspends queue 2 After the freeze condition is removed the QADC continues queue execution with the next CCW in sequence Trigger events that occur during freeze are not captured When a trigger event is pending for queue 2 before freeze begins that trigger event is remembered when the freeze is T1 T1 PAUSE Q1 Q2 QS IDLE ACTIVE IDLE ACTIVE IDLE 0010 0110 ...

Page 631: ...ed Situations 12 through 19 Figure 27 34 to Figure 27 41 show examples of all of the freeze situations Figure 27 34 CCW Freeze Situation 12 Figure 27 35 CCW Freeze Situation 13 Figure 27 36 CCW Freeze Situation 14 Figure 27 37 CCW Freeze Situation 15 C3 C4 CF1 C1 C2 T1 Q1 FREEZE C1 C2 T2 Q2 CF2 C3 C4 FREEZE C1 C2 T1 Q1 CF1 C3 C4 FREEZE T1 T1 T2 T2 TRIGGERS IGNORED C1 C2 T2 Q2 CF2 C3 C4 FREEZE T2 T...

Page 632: ... Figure 27 40 CCW Freeze Situation 18 Figure 27 41 CCW Freeze Situation 19 C1 C2 T1 Q1 CF1 C3 C4 FREEZE T1 T1 PF1 TRIGGERS IGNORED C1 C2 T2 Q2 CF2 C3 C4 FREEZE T2 T2 PF2 TRIGGERS IGNORED C1 C2 T1 Q1 CF1 C3 C4 FREEZE T2 C1 C2 Q2 C3 CF2 C4 TRIGGER CAPTURED RESPONSE DELAYED AFTER FREEZE C1 C2 T1 Q1 CF1 C4 FREEZE CF2 C4 C1 C2 T2 Q2 C3 C3 C4 ...

Page 633: ...ADC behavior For example if BQ2 is set to CCW0 CCW0 contains the EOQ code and a trigger event occurs on queue 1 the QADC reads CCW0 and detects both end of queue conditions The completion flag is set and queue 1 becomes idle Boundary conditions also exist for combinations of pause and end of queue One case is when a pause bit is in one CCW and an end of queue condition is in the next CCW The conve...

Page 634: ... Periodic timer continuous scan mode The following paragraphs describe single scan and continuous scan operations 27 8 4 Disabled Mode When disabled mode is selected the queue is not active Trigger events cannot initiate queue execution When both queue 1 and queue 2 are disabled there is no possibility of encountering wait states when accessing CCW table and result RAM When both queues are disable...

Page 635: ...single scan enable bit to a 1 or a 0 before the queue scan is complete has no effect however if the queue operating mode is changed the new queue operating mode and the value of the single scan enable bit are recognized immediately The conversion in progress is aborted and the new queue operating mode takes effect In software initiated single scan mode writing a 1 to the single scan enable bit cau...

Page 636: ... queue is completed the QADC clears the single scan enable bit The single scan enable bit can be written again to allow another scan of the queue to be initiated by the next external trigger edge The externally triggered single scan mode is useful when the input trigger rate can exceed the queue execution rate Analog samples can be taken in sync with an external event even though application softw...

Page 637: ...an enable bit is set in QACR1 or QACR2 the timer begins counting When the time interval elapses an internal trigger event is generated to start the queue and the QADC begins execution with the first CCW The QADC automatically performs the conversions in the queue until a pause or an end of queue condition is encountered When a pause occurs queue execution stops until the timer interval elapses aga...

Page 638: ... continuous scan mode the single scan enable bit in the queue control register does not have any meaning or effect As soon as the queue operating mode is programmed the selected trigger event can initiate queue execution In the case of software initiated continuous scan mode the trigger event is generated internally and queue execution begins immediately In the other continuous scan queue operatin...

Page 639: ...ueue While the time to internally generate and act on a trigger event is very short the queue status field can be read as momentarily indicating that the queue is idle The trigger overrun flag is never set while in software initiated continuous scan mode The software initiated continuous scan mode keeps the result registers updated more frequently than any of the other queue operating modes The re...

Page 640: ... The polarity of the external gate signal is fixed so that a high level opens the gate and a low level closes the gate Once the gate is open each CCW is read and the indicated conversions are performed until the gate is closed When the gate opens again queue execution automatically restarts at the beginning of the queue Software involvement is not needed between trigger events If a pause in a CCW ...

Page 641: ...timer generates a trigger event whenever the time interval elapses The trigger event may cause queue execution to continue following a pause or queue completion or may be considered a trigger overrun As with all continuous scan queue operating modes software action is not needed between trigger events Because both queues may be triggered by the periodic interval timer see Section 27 8 9 for a summ...

Page 642: ...to be software selectable The frequency of QCLK is set with the QPR field in QACR0 27 8 9 Periodic Interval Timer The QADC periodic interval timer can be used to generate trigger events at a programmable interval initiating execution of queue 1 and or queue 2 The periodic interval timer stays reset under these conditions Both queue 1 and queue 2 are programmed to any mode which does not use the pe...

Page 643: ... held in reset Removal of the QADC debug condition restarts the counter from the beginning Refer to Section 27 3 1 for more information 27 8 10 Conversion Command Word Table The conversion command word CCW table is 64 half word 128 byte long RAM with 10 bits of each entry implemented The CCW table is written by the user and is not modified by the QADC Each CCW requests the conversion of one analog...

Page 644: ...e queue can be scanned in single pass or continuous fashion When a single scan mode is selected the scan must be engaged by setting the single scan enable bit When a continuous scan mode is selected the queue remains active in the selected queue operating mode after the QADC completes each queue scan sequence Beginning of Queue 1 00 Channel Select Sample Hold A D Conversion Conversion Command Resu...

Page 645: ...pause is encountered or the end of the queue is detected An end of queue condition occurs when The CCW channel field is programmed with 63 to specify the end of the queue The end of queue 1 is implied by the beginning of queue 2 which is specified by the BQ2 field in QACR2 The physical end of the queue RAM space defines the end of either queue When any of the end of queue conditions is recognized ...

Page 646: ...nalog conversion specified by the corresponding CCW table entry The result word table can be read or written but in normal operation is only read to obtain analog conversions from the QADC Unimplemented bits read as 0s and writes have no effect NOTE Although the result RAM can be written some write operations like bit manipulation may not operate as expected because the hardware cannot access a tr...

Page 647: ...thin the limits defined by VDDA and VSSA as explained in this subsection 27 9 2 Analog Power Signals The analog supply signals VDDA and VSSA define the limits of the analog reference voltages VRH and VRL and of the analog multiplexer inputs Figure 27 44 is a diagram of the analog input circuitry Figure 27 44 Equivalent Analog Input Circuitry Because the sample amplifier is powered by VDDA and VSSA...

Page 648: ...A is 15 mV higher than VRL resulting in a minimum obtainable 10 bit conversion value of 0x0003 Figure 27 45 Errors Resulting from Clipping 27 9 3 Conversion Timing Schemes This section contains some conversion timing examples Figure 27 46 shows the timing for basic conversions where it is assumed that Q1 begins with CCW0 and ends with CCW3 CCW0 has pause bit set CCW1 does not have pause bit set Ex...

Page 649: ...s update when EOC triggers the write to the result register For the CCW with the pause bit set CCW0 CWP does not increment until triggered For the CCW with the pause bit clear CCW1 the CWP increments with the EOC The conversion results Q1 RESx show the result associated with CCWx such that R0 represents the result associated with CCW0 Figure 27 47 shows the timing for conversions in externally gat...

Page 650: ...e queue completed Figure 27 48 shows the timing for conversions in externally gated continuous scan mode with the same assumptions as in Figure 27 47 At the end of Q1 the completion flag CF1 sets and the queue restarts If the queue starts a second time and completes the trigger overrun flag TOR1 sets Figure 27 47 Gated Mode Single Scan Timing 0 8 0 8 0 CCW3 CCW2 CCW1 CCW0 LAST CCW0 CCW1 R3 R2 R1 R...

Page 651: ...om a common regulator filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned For example an RC low pass filter could be used to isolate the digital and analog supplies when generated by a common regulator If multiple high precision analog circuits are locally employed for example two A D converters the analog supplies should be isolated from eac...

Page 652: ...to improving or eliminating the problems associated with grounding excess transient currents involve star point ground systems One approach is to star point the different grounds at the power supply origin thus keeping the ground isolated Refer to Figure 27 49 Another approach is to star point the different grounds near the analog ground signal on the microcontroller by using small traces for conn...

Page 653: ...pecific considerations are voltages greater than VDDA or less than VSSA applied to an analog input which cause excessive currents into or out of the input Refer to MCF5282 Electrical Characteristics for more information on exact magnitudes Either stress conditions can potentially disrupt conversion results on neighboring inputs Parasitic devices associated with CMOS processes can cause an immediat...

Page 654: ...rrent into IIn the neighboring pin is determined by the KN current coupling ratio of the parasitic bipolar transistor KN 1 The IIn can be expressed by this equation IIn KN IINJ Where IINJ is either IINJN or IINJP A method for minimizing the impact of stress conditions on the QADC is to strategically allocate QADC inputs so that the lower accuracy inputs are adjacent to the inputs most likely to se...

Page 655: ...og signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not Figure 27 52 shows the connection of eight typical analog signal sources to one QADC analog input signal through a separate multiplexer chip Also an example of an analog signal source connected directly to a QADC analog input channel is displayed ...

Page 656: ...C54HC4051 MC74HC4051 MC54HC4052 MC74HC4052 MC54HC4053 etc RSource2 CFilter CSource RFilter2 CMUXIN 0 01 µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 01 µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 01 µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 01µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 01 µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 01 µF1 RSource2 CFilter CSource RFilter2 CMUXIN 0 ...

Page 657: ...cer or circuit supplying the analog signal to be measured See Section 27 9 7 2 In some cases the size of the capacitor at the pin may be very small Figure 27 53 is a simplified model of an input channel Refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the QADC Figure 27 53 Electrical Model of an A D Input Signal In Figure 27...

Page 658: ...is the total charge time As t approaches infinity VCF will equal VSRC This assumes no internal leakage With 10 bit resolution 1 2 of a count is equal to 1 2048 full scale value Assuming worst case VSRC full scale Table 27 24 shows the required time for CF to charge to within 1 2 of a count of the actual source voltage during 10 bit conversions Table 27 24 is based on the RC network in Figure 27 53...

Page 659: ...des are used and charge sharing effects with internal capacitors also contribute to the total leakage current Table 27 25 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance The error is listed in terms of 10 bit counts CAUTION Leakage below 200 nA is obtainable only within a limited temperature range 27 10 Interrupts The four interrupt ...

Page 660: ...eared 27 10 2 Interrupt Sources The QADC includes four sources of interrupt requests each of which is separately enabled Each time the result is written for the last conversion command word CCW in a queue the completion flag for the corresponding queue is set and when enabled an interrupt is requested In the same way each time the result is written for a CCW with the pause bit set the queue pause ...

Page 661: ...hich generates low voltage detect LVD interrupts and resets is implemented within the reset controller module 28 1 Features Module features include Seven sources of reset External Power on reset POR Watchdog timer Phase locked loop PLL loss of lock PLL loss of clock Software LVD reset Software assertable RSTO pin independent of chip reset state Software readable status flags indicating the cause o...

Page 662: ...ng CLKOUT edges causes the external reset request to be recognized and latched 28 3 2 RSTO This active low output signal is driven low when the internal reset controller module resets the chip When RSTO is active the user can drive override options on the data bus Table 28 1 Reset Controller Signal Properties Name Direction Input Hysteresis Input Synchronization RSTI I Y Y 1 1 RSTI is always synch...

Page 663: ...SBAR Offset Bits 7 0 Access 1 1 S U supervisor or user mode access 0x11_0000 RCR S U 0x11_0001 RSR S U 0x11_0002 Reserved2 0x11_0003 Reserved 2 2 Writes to reserved address locations have no effect and reads return 0s 7 6 5 4 0 Field SOFTRST FRCRSTOUT LVDF LVDIE LVDRE LVDE Reset 0000_0101 R W R W Address IPSBAR 0x11_0000 Figure 28 2 Reset Control Register RCR Table 28 3 RCR Field Descriptions Bit ...

Page 664: ... drops below VDD minimum The vector for this interrupt is shared with INT0 of the EPORT module Interrupt arbitration in the interrupt service routine is necessary if both of these interrupts are enabled Also LVDF is not cleared at reset however it will always initialize to a zero since the part will not come out of reset while in a low power state LVDE LVDRE bits are enabled out of reset 3 LVDIE L...

Page 665: ...used by watchdog timer timeout 0 Last reset not caused by watchdog timer timeout 3 POR Power on reset flag Indicates that the last reset was caused by a power on reset 1 Last reset caused by power on reset 0 Last reset not caused by power on reset 2 EXT External reset flag Indicates that the last reset was caused by an external device asserting the external RSTI pin 1 Last reset state caused by ex...

Page 666: ...Internal byte word or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs External writes including longword writes to 16 bit ports are also guaranteed to complete Asynchronous reset sources usually indicate a catastrophic failure Therefore the reset control logic does not wait for the current bus cycle to complete Reset is asserted immediately to the...

Page 667: ...controller asserts RSTO for approximately 512 cycles Then the part exits reset and begins operation 28 5 1 4 Loss of Clock Reset This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and either the PLL reference or the PLL itself fails The reset controller asserts RSTO for approximately 512 cycles after the PLL has acquired lock The part then exits reset and begins o...

Page 668: ... 5 2 Reset Control Flow The reset logic control flow is shown in Figure 28 4 In this figure the control state boxes have been numbered and these numbers are referred to within parentheses in the flow description that follows All cycle counts given are approximate ...

Page 669: ...OR SW RESET LOSS OF CLOCK LOSS OF LOCK RSTI NEGATED PLL MODE BUS CYCLE COMPLETE RCON ASSERTED PLL LOCKED ENABLE BUS MONITOR ASSERT RSTO AND LATCH RESET STATUS WAIT 512 CLKOUT CYCLES LATCH CONFIGURATION NEGATE RSTO POR OR LVD ASSERT RSTO AND LATCH RESET STATUS N N N Y Y Y 1 2 3 N N N 0 5 6 7 8 9 10 11 Y Y N N Y Y 12 4 9A 11A Y ...

Page 670: ...g 28 5 2 2 Internal Reset Request If reset is asserted by an asynchronous internal reset source such as loss of clock 1 or loss of lock 2 the reset control logic asserts RSTO 4 The reset control logic waits for the PLL to attain lock 9 9A before waiting 512 CLKOUT cycles 1 Then the reset control logic may latch the configuration according to the RCON pin level 11 11A before negating RSTO 12 If los...

Page 671: ...if another type of reset condition is detected during the reset sequence for the POR If a loss of clock or loss of lock condition is detected while waiting for the current bus cycle to complete 5 6 for an external reset request the EXT SOFT and or WDR bits along with the LOC and or LOL bits are set If the RSR bits are latched 7 during the EXT SOFT and or WDR reset sequence with no other reset cond...

Page 672: ...28 12 MCF5282 User s Manual MOTOROLA Functional Description ...

Page 673: ...kground debug mode BDM Provides low level debugging in the ColdFire processor complex In BDM the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers The external emulator uses a three pin serial full duplex channel See Section 29 5 Background Debug Mode BDM and Section 29 4 Programming Model Real time debug support BDM requires the proc...

Page 674: ...tate Development Serial Input DSI Internally synchronized input that provides data input for the serial communication port to the debug module Development Serial Output DSO Provides serial output communication for debug module responses DSO is registered internally Breakpoint BKPT Input used to request a manual breakpoint Assertion of BKPT puts the processor into a halted state after the current i...

Page 675: ...hen both storage elements contain valid data to be dumped to the DDATA port The core stalls until one FIFO entry is available Table 29 2 shows the encoding of these signals Table 29 2 Processor Status Encoding PST 3 0 Definition Hex Binary 0x0 0000 Continue execution Many instructions execute in one processor cycle If an instruction requires more processor clock cycles subsequent clock cycles are ...

Page 676: ...yed 3 The new target address is optionally available on subsequent cycles using the DDATA port The number of bytes of the target address displayed on this port is configurable 2 3 or 4 bytes 0x7 0111 Begin execution of return from exception RTE instruction 0x8 0xB 1000 1 011 Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles The value is driven ont...

Page 677: ...to the existing BDM commands that provide access to the processor s registers and the memory subsystem the debug module contains 19 registers to support the required functionality These registers are also accessible from the processor s supervisor programming model by executing the WDEBUG instruction write only Thus the breakpoint hardware in the debug module can be written by the external develop...

Page 678: ...M port using the RDMREG and WDMREG commands Address attribute trigger register Address low breakpoint register Address high breakpoint register 31 15 7 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 AATR ABLR ABHR CSR DBR DBMR PBR PBMR TDR PC breakpoint mask register PC breakpoint register Data breakpoint register Data breakpoint mask register Trigger definition register Configuration status register B...

Page 679: ...rites the data breakpoint in DBR Table 29 3 BDM Breakpoint Registers DRc 4 0 Register Name Abbreviation Initial State Page 0x00 Configuration status register CSR 0x00010_0000 p 29 10 0x01 0x05 Reserved 0x06 Address attribute trigger register AATR 0x0000_0005 p 29 8 0x07 Trigger definition register TDR 0x0000_0000 p 29 14 0x08 Program counter breakpoint register PBR p 29 13 0x09 Program counter bre...

Page 680: ...R Field Descriptions Bits Name Description 15 RM Read write mask Setting RM masks R in address comparisons 14 13 SZM Size mask Setting an SZM bit masks the corresponding SZ bit in address comparisons 12 11 TTM Transfer type mask Setting a TTM bit masks the corresponding TT bit in address comparisons 10 8 TMM Transfer modifier mask Setting a TMM bit masks the corresponding TM bit in address compari...

Page 681: ...h 001 User data access 010 User code access 011 Reserved 100 Reserved 101 Supervisor data access 110 Supervisor code access 111 Reserved TT 10 emulator mode 0xx 100 Reserved 101 Emulator mode data access 110 Emulator mode code access 111 Reserved TT 11 acknowledge CPU space transfers 000 CPU space access 001 111 Interrupt acknowledge levels 1 7 These bits also define the TM encoding for BDM memory...

Page 682: ...MREG and WDMREG commands Table 29 6 ABLR Field Description Bits Name Description 31 0 Address Low address Holds the 32 bit address marking the lower bound of the address breakpoint range Breakpoints for specific addresses are programmed into ABLR Table 29 7 ABHR Field Description Bits Name Description 31 0 Address High address Holds the 32 bit address marking the upper bound of the address breakpo...

Page 683: ...the MCF5282 19 17 Reserved should be cleared 16 IPW Inhibit processor writes Setting IPW inhibits processor initiated writes to the debug module s programming model registers IPW can be modified only by commands from the external development system 15 MAP Force processor references in emulator mode 0 All emulator mode references are mapped into supervisor code and data spaces 1 The processor maps ...

Page 684: ...e always reported before the next instruction begins execution and trigger reporting can be considered precise 5 IPI Ignore pending interrupts 1 Core ignores any pending interrupt requests signalled while in single instruction step mode 0 Core services any pending interrupt requests that were signalled while in single step mode 4 SSM Single step mode Setting SSM puts the processor in single step m...

Page 685: ...ed with the processor s program counter register as defined in TDR Figure 29 9 shows the PC breakpoint register Table 29 9 DBR Field Descriptions Bits Name Description 31 0 Data Data breakpoint value Contains the value to be compared with the data value from the processor s local bus as a breakpoint trigger Table 29 10 DBMR Field Descriptions Bits Name Description 31 0 Mask Data breakpoint mask Th...

Page 686: ...ervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 29 5 3 3 Command Set Descriptions DRc 4 0 0x08 Figure 29 9 Program Counter Breakpoint Register PBR Table 29 12 PBR Field Descriptions Bits Name Description 31 0 Address PC breakpoint address The 32 bit address to be compared with the PC as a breakpoint trigger 31 0 ...

Page 687: ... Field Descriptions Bits Name Description 31 30 TRC Trigger response control Determines how the processor responds to a completed trigger condition The trigger response is always displayed on DDATA 00 Display on DDATA only 01 Processor halt 10 Debug interrupt 11 Reserved 15 14 LxT Level x trigger This is a Rev B function only The Level x Trigger bit determines the logic operation for the trigger b...

Page 688: ...rd 25 9 EDLL Lower lower data byte Low order byte of the low order word 24 8 EDLM Lower middle data byte High order byte of the low order word 23 7 EDUM Upper middle data byte Low order byte of the high order word 22 6 EDUU Upper upper data byte High order byte of the high order word 21 5 DI Data breakpoint invert Provides a way to invert the logical sense of all the data breakpoint comparators Th...

Page 689: ... be considered in the following two special cases After the system reset signal is negated the processor waits for 16 processor clock cycles before beginning reset exception processing If the BKPT input is asserted within eight cycles after RSTI is negated the processor enters the halt state signaling halt status 0xF on the PST outputs While the processor is in this state all resources accessible ...

Page 690: ... is sampled and DSO is driven Figure 29 12 BDM Serial Interface Timing DSCLK and DSI are synchronized inputs DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor clock as well as the DSI DSO is delayed from the DSCLK enabled CLK rising edge registered after a BDM state machine state change All events in the debug module s serial state machine are based on the proc...

Page 691: ...the status of CPU generated messages listed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor clock periods S Data Message 0 xxxx Valid data transfer 0 0xFFFF Status OK 1 0x0000 Not ready with response come again 1 0x0001 Error Terminated bus cycle data invalid 1 0xFFFF Illegal...

Page 692: ... 3 3 3 0x1900 byte 0x1940 word 0x1980 lword Write memory location WRITE Write the operand data to the memory location specified by the longword address Steal 29 5 3 3 4 0x1800 byte 0x1840 word 0x1880 lword Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result A DUMP command retri...

Page 693: ...data or operand data 15 10 9 8 7 6 5 4 3 2 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 29 15 BDM Command Format Table 29 18 BDM Field Descriptions Bit Name Description 15 10 Operation Specifies the command These values are listed in Table 29 17 9 0 Reserved should be cleared 8 R W Direction of operand transfer 0 Data is written to the CPU or to memory from the development sy...

Page 694: ...d command is decoded as unimplemented which is indicated by the illegal command encoding If this occurs the development system should retransmit the command NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the debug module can accept a new serial transfer after 32 processor clock periods In cycle 3 the development system supplies the low order 16 address ...

Page 695: ...s summarized in Table 29 17 NOTE The BDM status bit S is 0 for normally completed commands S 1 for illegal commands not ready responses and transfers with bus errors Section 29 5 2 BDM Serial Interface describes the receive packet format Motorola reserves unassigned command opcodes for future expansion Unused command formats in any revision level perform a NOP and return an illegal command respons...

Page 696: ... data is supplied most significant word first Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete 29 5 3 3 3 Read Memory Location READ Read data at the longword address Address space is defined by BAAR TT TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligne...

Page 697: ... 0x0001 S 1 is returned if a bus error occurs 15 12 11 8 7 4 3 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0x4 0x0 A 31 16 A 15 0 Result D 15 0 Longword Command 0x1 0x9 0x8 0x0 A 31 16 A 15 0 Result D 31 16 D 15 0 Figure 29 21 READ Command Result Formats XXX NOT READY READ LONG MS ADDR NOT READY LS ADDR NOT READY NEXT CMD NOT READY NEXT CMD LS RE...

Page 698: ...AAR TT TM Hardware forces low order address bits to zeros for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Formats 15 12 11 8 7 4 3 1 Byte 0x1 0x8 0x0 0x0 A 31 16 A 15 0 X X X X X X X X D 7 0 Word 0x1 0x8 0x4 0x0 A 31 16 A 15 0 D 15 0 Longword 0x1 0x8 0x8 0x0 A 31 16 A 15 0 D 31 16 D 15 0 Figure 29 23 WRITE Command Fo...

Page 699: ... large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP an illegal command response is returned The DUMP command retrieves subsequent operands The initial address is incremented by the operand size 1 2 or 4 and saved in a temporary register Subsequent DUMP commands use ...

Page 700: ... NOP can be used for intercommand padding without corrupting the address pointer The size field is examined each time a DUMP command is processed allowing the operand size to be dynamically altered Command Result Formats 15 12 11 8 7 4 3 0 Byte Command 0x1 0xD 0x0 0x0 Result X X X X X X X X D 7 0 Word Command 0x1 0xD 0x4 0x0 Result D 15 0 Longword Command 0x1 0xD 0x8 0x0 Result D 31 16 D 15 0 Figu...

Page 701: ...remented by the operand size 1 2 or 4 and saved in a temporary register after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary register If an initial WRITE is not executed preceding the first FILL command the illegal command response is returned NOTE The FILL command does not check f...

Page 702: ...32 bits respectively Result Data Command complete status 0xFFFF is returned when the register write is complete A value of 0x0001 with S set is returned if a bus error occurs 15 12 11 8 7 4 3 0 Byte 0x1 0xC 0x0 0x0 X X X X X X X X D 7 0 Word 0x1 0xC 0x4 0x0 D 15 0 Longword 0x1 0xC 0x8 0x0 D 31 16 D 15 0 Figure 29 27 FILL Command Format XXX NOT READY FILL B W DATA NOT READY NEXT CMD NOT READY WRITE...

Page 703: ... the command is ignored Command Sequence Figure 29 30 GO Command Sequence Operand Data None Result Data The command complete response 0xFFFF is returned during the next shift operation 29 5 3 3 8 No Operation NOP NOP performs no operation and may be used as a null command where required Command Formats Command Sequence Figure 29 32 NOP Command Sequence Operand Data None Result Data The command com...

Page 704: ...4 3 0 Command 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 Rc Result D 31 16 D 15 0 Figure 29 33 RCREG Command Result Formats Table 29 19 Control Register Map Rc Register Definition 0x002 Cache Control Register CACR 0x004 Access Control Register ACR0 0x005 Access Control Register ACR1 0x800 Other Stack Pointer OTHER_A7 0x801 Vector Base Register VBR 0x804 MAC Status Register MACSR 0x805 MAC Mask Register M...

Page 705: ...of the two hardware registers is a function of the operating mode of the processor if SR S 1 then A7 Supervisor Stack Pointer other_A7 User Stack Pointer else A7 User Stack Pointer other_A7 Supervisor Stack Pointer The BDM programming model supports reads and writes to the A7 and other_A7 registers directly It is the responsibility of the external development system to determine the mapping of the...

Page 706: ... modes wcreg data accn write the desired accumulator wcreg saved_data macsr restore the original macsr Additionally it is required that writes to the accumulator extension registers be performed after the corresponding accumulators are updated This is needed since a write to any accumulator alters the contents of the corresponding extension register For more information on saving and restoring the...

Page 707: ...elected debug module register and return the 32 bit result The only valid register selection for the RDMREG command is CSR DRc 0x00 Note that this read of the CSR clears CSR FOF TRG HALT BKPT as well as the trigger status bits CSR BSTAT if either a level 2 breakpoint has been triggered or a level 1 breakpoint has been triggered and no level 2 breakpoint has been enabled Command Result Formats Tabl...

Page 708: ... inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction Command Format Table 29 3 shows the definition of the DRc write encoding Command Sequence Figure 29 40 WDMREG Command Sequence Table 29 20 Definition of DRc Encoding Read DRc 4 0 Debug Register Definition Mnemonic Initial State Page 0x00 Configuration Status CSR 0x0 p 29 10 0x01 0x1F R...

Page 709: ...g the external development system 29 6 1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways The response desired is programmed into TDR As shown in Table 29 21 when a breakpoint is triggered an indication CSR BSTAT is provided on the DDATA output port when it is not displaying captured processor status operands or branch addresses The breakpoint status...

Page 710: ...The core enters emulator mode when exception processing begins After the standard 8 byte exception stack is created the processor fetches a unique exception vector 12 from the vector table Execution continues at the instruction address in the vector corresponding to the breakpoint triggered All interrupts are ignored while the processor is in emulator mode The debug interrupt handler can use super...

Page 711: ...gisters For BDM commands that access memory the debug module requests the processor s local bus The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access After the debug module bus cycle the processor reclaims the bus Breakpoint registers must be carefully configured in ...

Page 712: ...truction Set Table 29 22 shows the PST DDATA specification for user mode instructions Rn represents any Dn An register In this definition the y suffix generally denotes the source and x denotes the destination operand For a given instruction the optional operand data is displayed only for those effective addresses referencing memory The DD nomenclature refers to the DDATA outputs Table 29 22 PST D...

Page 713: ... Dx PST 0x1 PST 0xB DD source operand divs w ea y Dx PST 0x1 PST 0x9 DD source operand divu l ea y Dx PST 0x1 PST 0xB DD source operand divu w ea y Dx PST 0x1 PST 0x9 DD source operand eor l Dy ea x PST 0x1 PST 0xB DD source PST 0xB DD destination eori l imm Dx PST 0x1 ext l Dx PST 0x1 ext w Dx PST 0x1 extb l Dx PST 0x1 ff1 l Dx PST 0x1 jmp ea x PST 0x5 PST 0x9AB DD target address 1 jsr ea x PST 0...

Page 714: ...ea y PST 0x1 PST 0xB DD destination operand pulse PST 0x4 rems l ea y Dx Dw PST 0x1 PST 0xB DD source operand remu l ea y Dx Dw PST 0x1 PST 0xB DD source operand rts PST 0x1 PST 0xB DD source operand PST 0x5 PST 0x9AB DD target address scc Dx PST 0x1 sub l ea y Rx PST 0x1 PST 0xB DD source operand sub l Dy ea x PST 0x1 PST 0xB DD source PST 0xB DD destination subi l imm Dx PST 0x1 subq l imm ea x ...

Page 715: ...es This includes the following ea x values An d16 An d8 An Xi d8 PC Xi 2 For Move Multiple instructions MOVEM the processor automatically generates line sized transfers if the operand address reaches a 0 modulo 16 boundary and there are four or more registers to be transferred For these line sized transfers the operand data is never captured nor displayed regardless of the CSR value The automatic ...

Page 716: ...in the given mode move l Accy Rx PST 0x1 move l MACSR CCR PST 0x1 move l MACSR Rx PST 0x1 move l MASK Rx PST 0x1 move l Accext01 Rx PST 0x1 move l Accext23 Rx PST 0x1 msac l Ry Rx Accx PST 0x1 msac l Ry Rx ea Rw Accx PST 0x1 PST 0xB DD source operand msac w Ry Rx Accx PST 0x1 msac w Ry Rx ea Rw Accx PST 0x1 PST 0xB DD source operand Table 29 24 PST DDATA Specification for Supervisor Mode Instructi...

Page 717: ...ged 2 x 13 Figure 29 41 Recommended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved 1 GND GND RESET Pad Voltage2 GND PST2 PST0 DDATA2 DDATA0 Motorola reserved GND Core Voltage BKPT DSCLK Developer reserved 1 DSI DSO PST3 PST1 DDATA3 DDATA1 GND Motorola reserved CLKOUT 2Supplied by target 1Pins reserved for BDM developer use TA ...

Page 718: ...29 46 MCF5282 User s Manual MOTOROLA Motorola Recommended BDM Pinout ...

Page 719: ...or phase lock loop PLL mode with internal or external reference Selects output pad drive strength Selects boot device and data port size Selects bus monitor configuration Selects low power configuration Selects transfer size function of the external bus Selects processor status PSTAT and processor debug data DDATA functions Selects BDM or JTAG mode 30 2 Modes of Operation The CCM configures the ch...

Page 720: ...d D pins and PJ 5 4 BS 1 0 can be configured as general purpose input output I O and when interfacing to 8 bit ports the ports B C and D pins and PJ 7 5 BS 3 1 can be configured as general purpose input output I O 30 2 2 Single Chip Mode In single chip mode all memory is internal to the chip All external bus pins are configured as general purpose I O 30 3 Block Diagram Figure 30 1 Chip Configurati...

Page 721: ...t 30 4 3 D 26 24 21 19 16 Reset Configuration Override If the external RCON pin is asserted during reset then the states of these data pins during reset determine the chip mode of operation boot device clock mode and certain module configurations after reset 30 5 Memory Map and Registers This subsection provides a description of the memory map and registers 30 5 1 Programming Model The CCM program...

Page 722: ...nce Table 30 3 Chip Configuration Module Memory Map IPSBAR Offset Bits 31 16 Bits 15 0 Access 1 1 S CPU supervisor mode access only User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error 0x0011_0004 Chip Configuration Register CCR Low Power Control Register LPCR 2 2 See Chapter 7 Power Management for a description of the LPCR It is shown her...

Page 723: ...ial drive strength for selected pad output drivers For maximum capacitive load set the LOAD bit to select full drive strength For reduced power consumption and reduced electromagnetic interference EMI clear the LOAD bit to select partial drive strength 0 Default drive strength 1 Full drive strength Table 30 2 shows the read write accessibility of this write once bit 14 11 Reserved should be cleare...

Page 724: ...01 32768 010 16384 011 8192 100 4096 101 2048 110 1024 111 512 Table 30 2 shows the read write accessibility of this write once bit 15 10 9 8 7 6 5 4 3 2 1 0 Field RCSC RPLLSEL RPLLREF RLOAD BOOTPS BOOTSEL MODE Reset 0000_0000_1110_0000 R W R Address IPSBAR 0x11_0008 Figure 30 3 Reset Configuration Register RCON Table 30 5 RCON Field Descriptions Bits Name Description 15 10 Reserved should be clea...

Page 725: ... to be external Table 30 7 shows the different port configurations for BOOTPS The default function of the boot port size can be overridden during reset configuration 2 BOOTSEL Boot select Reflects the default selection for the boot device 0 Boot from internal boot device This is the value used for the MCF5282 1 Boot from external boot device 1 Reserved should be cleared 0 MODE Chip configuration m...

Page 726: ...uration During reset the pins for the reset override functions are immediately configured to known states Table 30 9 shows the states of the external pins while in reset 15 8 7 0 Field PIN PRN Reset 0010_0000_0000_0000 R W R Address IPSBAR 0x11_000a Figure 30 4 Chip Identification Register CIR Table 30 8 CIR Field Description Bits Name Description 15 8 PIN Part identification number Contains a uni...

Page 727: ... default operation mode defined in the RCON register If the external RCON pin is asserted pin functions are determined by the override values driven on the external data bus pins I O Output State Input State D 26 24 21 19 16 PA 2 0 PB 5 3 0 Digital I O or primary function Input Must be driven by external logic RCON RCON function for all modes 2 2 During reset the external RCON pin assumes its RCON...

Page 728: ...6 PF 6 5 A 22 21 01 PF 7 6 CS6 CS5 PF 5 A 21 11 PF 7 6 CS6 CS5 CS4 1 Modifying the default configurations is possible only if the external RCON pin is asserted 2 The D 31 27 23 22 20 15 0 pins do not affect reset configuration 3 The external reset override circuitry drives the data bus pins with the override values while RSTO is asserted It must stop driving the data bus pins within one CLKOUT cyc...

Page 729: ...trength configuration can be changed by programming the LOAD bit of the chip configuration register 30 6 5 Clock Mode Selection The clock mode is selected during reset and reflected in the PLLMODE PLLSEL and PLLREF bits of SYNSR Once reset is exited the clock mode cannot be changed Table 30 13 summarizes clock mode selection during reset configuration Table 30 11 Chip Configuration Mode Selection ...

Page 730: ...ers to a known startup state as described in Section 30 5 Memory Map and Registers The CCM controls chip configuration at reset as described in Section 30 6 Functional Description 30 8 Interrupts The CCM does not generate interrupt requests Table 30 13 Clock Mode Selection 1 1Modifying the default configurations is possible only if the external RCON pin is asserted low Clock Mode Synthesizer Statu...

Page 731: ...test logic that complies with the IEEE 1149 1 standard for boundary scan testability to help with system diagnostic and manufacturing testing This architecture provides access to all data and chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST Figure 31 1 shows the block diagram of the JTAG module ...

Page 732: ...ss instruction Samples the system pins during operation and transparently shift out the result Selects between JTAG TAP controller and Background Debug Module BDM using a dedicated JTAG_EN pin 4 BIT TAP INSTRUCTION REGISTER 3 0 1 BIT BYPASS REGISTER 148 BIT BOUNDARY SCAN REGISTER 32 BIT IDCODE REGISTER TRST DSCLK TCLK TMS BKPT 0 31 0 147 TAP CONTROLLER TDI DSI 1 0 TDO DSO JTAG Module to Debug Modu...

Page 733: ...pin function selected depending upon JTAG_EN logic state When one module is selected the inputs into the other module are disabled or forced to a known logic level as shown in Table 31 3 in order to disable the corresponding module Table 31 1 Signal Properties Name Direction Function Reset State Pull up JTAG_EN Input JTAG BDM selector input TCLK Input JTAG Test clock input Active TMS BKPT Input JT...

Page 734: ...tor The BKPT pin is used to request an external breakpoint Assertion of BKPT puts the processor into a halted state after the current instruction completes 31 3 1 4 TDI DSI Test Data Input Development Serial Input The TDI pin is the LSB first data and instruction input TDI is sampled on the rising edge of TCLK The TDI pin has an internal pull up resistor The DSI pin provides data input for the deb...

Page 735: ...ister IR The JTAG module uses a 4 bit shift register with no parity The IR transfers its value to a parallel hold register and applies an instruction on the falling edge of TCLK when the TAP state machine is in the update IR state To load an instruction into the shift portion of the IR place the serial data on the TDI pin before each rising edge of TCLK The MSB of the IR is the bit closest to the ...

Page 736: ...update DR state 31 4 2 6 Boundary Scan Register The boundary scan register is connected between TDI and TDO when the EXTEST or SAMPLE PRELOAD instruction is selected It captures input pin data forces fixed values on output pins and selects a logic value and direction for bidirectional pins or high impedance for tri stated pins The boundary scan register contains bits for bonded out and non bonded ...

Page 737: ...ontroller is a state machine that changes state based on the sequence of logical values on the TMS pin Figure 31 3 shows the machine s states The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCLK signal Asserting the TRST signal asynchronously resets the TAP controller to the test logic reset state As Figure 31 3 shows holding TMS at logic 1 while...

Page 738: ...ter while applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift SAMPLE PRELOAD 0010 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation RUN TEST IDLE TEST LOGIC RESET 1 1 SELECT DR SCAN CAPTURE DR EXIT1 DR PAUSE DR UPDATE DR SELECT IR SCAN SHIFT DR EXIT2 DR CAPTURE IR SHIFT IR EXIT1 ...

Page 739: ...llowing entry into the capture DR state IDCODE is the default instruction placed into the instruction register when the TAP resets Thus after a TAP reset the IDCODE register is selected automatically 31 5 3 3 SAMPLE PRELOAD Instruction The SAMPLE PRELOAD instruction has two functions SAMPLE obtain a sample of the system data and control signals present at the MCU input pins and just before the bou...

Page 740: ...g edge of TCLK when the TAP controller transitions from update IR to run test idle state Once asserted the part disables the TCLK TMS and TDI inputs into JTAG and forces these JTAG inputs to logic 1 The TAP controller remains in the run test idle state until the TRST input is asserted logic 0 31 5 3 5 ENABLE_TEST_CTRL Instruction The ENABLE_TEST_CTRL instruction selects a 3 bit shift register TEST...

Page 741: ...igured as outputs to the fixed values that are preloaded and held in the boundary scan update register CLAMP enhances test efficiency by reducing the overall shift path to a single bit the bypass register while conducting an EXTEST type of instruction through the boundary scan register 31 5 3 9 BYPASS Instruction The BYPASS instruction selects the bypass register creating a single bit shift regist...

Page 742: ... not blocked in low power stop mode To consume minimal power the TCLK input should be externally connected to VDD The TMS TDI and TRST pins include on chip pull up resistors For minimal power consumption in low power stop mode these three pins should be either connected to VDD or left unconnected 31 6 2 Nonscan Chain Operation Keeping the TAP controller in the test logic reset state ensures that t...

Page 743: ...MOTOROLA Chapter 32 Mechanical Data 32 1 Chapter 32 Mechanical Data This chapter contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5282 ...

Page 744: ... F A1 A0 D31 NC VDD VSS VDD VDD VDD VDD VSS VDD QSPI_ DOUT QSPI_ CLK QSPI_ CS0 QSPI_ CS1 G D30 D29 D28 D27 VDD VDD VSS VSS VSS VSS VDD VDD QSPI_ CS2 QSPI_ CS3 DRAMW SDRAM_ CS0 H D26 D25 D24 D23 VDD VDD VSS VSS VSS VSS VDD VDD SDRA_ CS1 SCKE SRAS SCAS J D22 D21 D20 D19 VDD VDD VSS VSS VSS VSS VDD VDD DTOUT0 DTIN0 DTOUT1 DTIN1 K D18 D17 D16 NC VDD VDD VSS VSS VSS VSS VDD VDD DTOUT2 DTIN2 DTOUT3 DTIN...

Page 745: ... ECRS PEH0 J11 VDD A12 VDDF J12 VDD A13 DDATA1 PDD5 J13 DTOUT0 PTD0 UCTS1 UCTS0 A14 PST2 PDD2 J14 DTIN0 PTD1 UCTS1 UCTS0 A15 PST0 PDD0 J15 DTOUT1 PTD2 URTS1 URTS0 A16 VSS J16 DTIN1 PTD3 URTS1 URTS0 B1 A14 PG6 K1 D18 PB2 B2 A13 PG5 K2 D17 PB1 B3 A17 PF1 K3 D16 PB0 B4 A19 PF3 K4 NC1 B5 VSSF K5 VDD B6 A22 PF6 CS5 K6 VDD B7 ETXD2 PEL6 K7 VSS B8 ERXER PEL0 K8 VSS B9 ERXD2 PEL2 K9 VSS B10 EMDC PAS4 UTXD...

Page 746: ...S2 PJ2 C16 IRQ3 PNQ3 L16 CS3 PJ3 D1 A9 PG1 M1 D11 PC3 D2 A8 PG0 M2 D10 PC2 D3 A7 PH7 M3 D9 PC1 D4 A6 PH6 M4 D8 PC0 D5 VDDF M5 VSS D6 ETXEN PEH6 M6 VDD D7 ETXD0 PEH5 M7 VDD D8 NC M8 VDD D9 ERXD0 PEH1 M9 VDD D10 ETXER PEL4 M10 VDD D11 VDDF M11 VDD D12 DDATA2 PDD6 M12 VSS D13 NC M13 NC D14 IRQ2 PNQ2 M14 TIP PE0 SYNCB D15 IRQ1 PNQ1 M15 TS PE1 SYNCA D16 CANRX PAS3 URXD2 M16 SIZ0 PE2 SYNCB E1 A5 PH5 N1 ...

Page 747: ...E7 F1 A1 PH1 P1 D4 PD4 F2 A0 PH0 P2 VDDH F3 D31 PA7 P3 AN55 PQA3 ETRIG1 F4 NC P4 VRH F5 VDD P5 VSSA F6 VSS P6 D0 PD0 F7 VDD P7 UTXD1 PUA2 F8 VDD P8 VSSPLL F9 VDD P9 DSCLK TRST F10 VDD P10 BKPT TMS F11 VSS P11 RSTO F12 VDD P12 GPTB1 PTB1 F13 QSPI_DOUT PQS0 P13 GPTA1 PTA1 F14 QSPI_CLK PQS2 P14 BS3 PJ7 F15 QSPI_CS0 PQS3 P15 TEA PE5 F16 QSPI_CS1 PQS4 P16 TA PE6 G1 D30 PA6 R1 AN3 PQB3 ANZ G2 D29 PA5 R2...

Page 748: ...S0 PSD1 R16 BS0 PJ4 H1 D26 PA2 T1 VSSA H2 D25 PA1 T2 AN2 PQB2 ANY H3 D24 PA0 T3 AN0 PQB0 ANW H4 D23 PB7 T4 AN53 PQA1 MA1 H5 VDD T5 VRL H6 VDD T6 D2 PD2 H7 VSS T7 UTXD0 PUA0 H8 VSS T8 EXTAL H9 VSS T9 TCLK H10 VSS T10 DSO TDO H11 VDD T11 RCON H12 VDD T12 GPTB3 PTB3 H13 SDRAM_CS1 PSD2 T13 GPTA3 PTA3 H14 SCKE PSD0 T14 CLKMOD1 H15 SRAS PSD5 T15 BS2 PJ6 H16 SCAS PSD4 T16 VSS 1 No connect Table 32 1 MCF5...

Page 749: ...F80 MCF5282 RISC Microprocessor 256 MAPBGA 80 MHz 40 to 85 C X Y D E LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 0 20 METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA M M 3 A B C D E F G H J K L M N P R T 1 2 3 4 5 6 7 10 11 12 13 14 15 16 e 15X e 15X b 256X M 0 25 Y Z M 0 10 X Z S DETAIL K VIEW M M ROTATED 90 CLOCKWISE S A Z Z A2 A1 4 0 15 Z 0 30 256X 5 K NOTES 1 DIMENSIONS ARE IN MILL...

Page 750: ...32 8 MCF5282 User s Manual MOTOROLA Ordering Information ...

Page 751: ...pecifications will be published after complete characterization and device qualifications have been completed NOTE The parameters specified in this MCU document supersede any values found in the module specifications 33 1 Maximum Ratings Table 33 1 Absolute Maximum Ratings1 2 Rating Symbol Value Unit Supply Voltage VDD 0 3 to 4 0 V Clock Synthesizer Supply Voltage VDDPLL 0 3 to 4 0 V RAM Memory St...

Page 752: ...e level e g either VSS or VDD 3 Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values 6 0V voltage excludes XTAL and EXTAL pads 4 All functional non supply pins are internally clamped to VSS and VDD 5 Power supply must maintain r...

Page 753: ... with the board horizontal C W Junction to ambient 200 ft min Four layer board 2s2p θJMA 231 2 C W Junction to board θJB 153 3 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package C W Junction to case θJC 104 4 Thermal resistance between the die and the case top surface as measured by the ...

Page 754: ...Hysteresis VHYS 0 06 x VDD mV Input Leakage Current Vin VDD or VSS Input only pins Iin 1 0 1 0 µA High Impedance Off State Leakage Current Vin VDD or VSS All input output and output pins IOZ 1 0 1 0 µA Output High Voltage All input output and all output pins IOH 2 0 mA VOH VDD 0 5 __ V Output Low Voltage All input output and all output pins IOL 2 0mA VOL __ 0 5 V Weak Internal Pull Up Device Curre...

Page 755: ...mory Supply Current Read Program or Erase5 Idle STOP IDDF 30 64 20 10 mA mA mA µA Analog Supply Current Normal Operation Low Power Stop IDDA 5 0 10 0 mA µµAµ 1 Refer to Table 33 4 through Table 33 8 for additional PLLQADC and Flash specifications 2 This parameter is characterized before qualification rather than 100 tested 3 Refer to the chip configuration section for more information Drivers for ...

Page 756: ...an 100 tested 5 Proper PC board layout procedures must be followed to achieve specifications tcst 10 ms EXTAL Input High Voltage Crystal Mode All other modes 1 1 Bypass External VIHEXT VDD 1 0 2 0 VDD VDD V EXTAL Input Low Voltage Crystal Mode All other modes 1 1 Bypass External VILEXT VSS VSS 1 0 0 8 V XTAL Output High Voltage IOH 1 0 mA VOL VDD 1 0 V XTAL Output Low Voltage IOL 1 0 mA VOL 0 5 V ...

Page 757: ...y with reference to VRL VRH 0 3 6 0 V VSS Differential Voltage VSS VSSA 0 1 0 1 V VDD Differential Voltage 2 2 Refers to allowed random sequencing of power supplies VDD VDDA 6 0 4 0 V VREF Differential Voltage VRH VRL 0 3 6 0 V VRH to VDDA Differential Voltage 3 3 Refers to allowed random sequencing of power supplies VRH VDDA 6 0 6 0 V VRL to VSSA Differential Voltage VRL VSSA 0 3 0 3 V VDDH to VD...

Page 758: ... QADC converter specifications are only guaranteed for VDDH and VDDA 5 0V 0 5V VDDH and VDDA may be powered down to 2 7V with only GPIO functions supported 2 To obtain full scale full range results VSSA VRL VINDC VRH VDDA 3 Parameter applies to the following pins Port A PQA 4 3 AN 56 55 ETRIG 2 1 PQA 1 0 AN 53 52 MA 1 0 Port B PQB 3 0 AN 3 0 AN Z W 4 Current measured at maximum system clock freque...

Page 759: ... 0 14 0 µs 4 Stop Mode Recovery Time TSR 10 µs 5 Resolution2 2 At VRH VRL 5 12 V one count 5 mV 5 mV 6 Absolute total unadjusted error 3 4 5 FQCLK 2 0 MHz 2 2 clock input sample time 3 Accuracy tested and guaranteed at VRH VRL 5 0V 0 5V 4 Current Coupling Ratio K is defined as the ratio of the output current Iout measured on the pin under test to the injection current Iinj when both adjacent pins ...

Page 760: ...ts from 1 0 1 P E 10 0002 2 Reprogramming of a Flash array block prior to erase is not required Cycles Data retention at average operating temperature of 85 C Retention 10 Years Table 33 10 Processor Bus Input Timing Specifications Name Characteristic1 1 Timing specifications have been indicated taking into account the full drive strength for the pads Symbol Min Max Unit B0 CLKOUT tCYC 12 5 ns Con...

Page 761: ... Outputs B6a CLKOUT high to chip selects valid 1 tCHCV 0 5tCYC 10 ns B6b CLKOUT high to byte enables BS 3 0 valid2 tCHBV 0 5tCYC 10 ns B6c CLKOUT high to output enable OE valid3 tCHOV 0 5tCYC 10 ns B7 CLKOUT high to control output BS 3 0 OE invalid tCHCOI 0 5tCYC 2 ns B7a CLKOUT high to chip selects invalid tCHCI 0 5tCYC 2 ns Invalid Invalid CLKOUT 66 67 MHz TSETUP THOLD Input Setup And Hold 1 5V ...

Page 762: ...ddress A 23 0 and control TS SIZ 1 0 TIP R W invalid tCHAI 2 ns Data Outputs B11 CLKOUT high to data output D 31 0 valid tCHDOV 10 ns B12 CLKOUT high to data output D 31 0 invalid tCHDOI 2 ns B13 CLKOUT high to data output D 31 0 high impedance tCHDOZ 6 ns 1 CSn transitions after the falling edge of CLKOUT 2 BS transitions after the falling edge of CLKOUT 3 OE transitions after the falling edge of...

Page 763: ... Write Internally Terminated Timing Figure 33 3 shows a bus cycle terminated by TA showing timings listed in Table 33 11 CLKOUT CSn A 23 0 R W BS 3 0 D 31 0 TA H H S0 S2 S3 S1 S4 S5 S0 S1 S2 S3 S4 S5 TEA H B6a B8 B7a B6c B7 B6b B7 B4 B5 B11 B12 B9 B9 B8 B6b B13 OE B0 B7 B9 TS TIP B8 B8 B9 B8 B9 SIZ 1 0 B7a B6a B8 ...

Page 764: ... Figure 33 3 Read Bus Cycle Terminated by TA Figure 33 4 shows a bus cycle terminated by TEA it displays the timings listed in Table 33 11 CLKOUT CSn A 23 0 OE R W BS 3 0 TA H S0 S2 S3 S1 S4 S5 S0 S1 TEA H B6a B8 B7a B9 B6c B7 B6b B7 B2a B1a D 31 0 B4 B5 B8 B9 TS B9 TIP B8 SIZ 1 0 ...

Page 765: ...eristics 33 15 Processor Bus Output Timing Specifications Figure 33 4 Read Bus Cycle Terminated by TEA CLKOUT CSn A 23 0 OE R W BS 3 0 TEA H S0 S2 S3 S1 S4 S5 S0 S1 TA H B6a B8 B7a B9 B6c B7 B6b B7 B2a B1a D 31 0 B8 B9 TS B9 TIP B8 SIZ 1 0 ...

Page 766: ...10 ns D2 CLKOUT high to SDRAM control valid tCHDCV 10 ns D3 CLKOUT high to SDRAM address invalid tCHDAI 2 ns D4 CLKOUT high to SDRAM control invalid tCHDCI 2 ns D5 SDRAM data valid to CLKOUT high tDDVCH 6 ns D6 CLKOUT high to SDRAM data invalid tCHDDI 1 ns D72 2 D7 and D8 are for write cycles only CLKOUT high to SDRAM data valid tCHDDVW 10 ns D82 CLKOUT high to SDRAM data invalid tCHDDIW 2 ns A 23...

Page 767: ...3 6 V VSS 0 V VDDH 5 V NUM Characteristic Symbol Min Max Unit G1 G2 CLKOUT High to GPIO Output Valid tCHPOV 12 ns CLKOUT High to GPIO Output Invalid tCHPOI 2 ns G3 G4 GPIO Input Valid to CLKOUT High tPVCH 10 ns CLKOUT High to GPIO Input Invalid tCHPI 2 ns A 23 0 SRAS SCAS1 D 31 0 ACTV PALL NOP SDRAM_CS 1 0 WRITE Row Column CLKOUT DRAMW BS 3 0 D1 D2 D4 D8 D4 0 1 2 3 4 5 6 7 8 9 10 11 12 D7 NOP 1 DA...

Page 768: ...d Timer 2 Because of long delays associated with the PQA PQB pads signals on the PQA PQB pins will be updated on the following edge of the clock Table 33 14 Reset and Configuration Override Timing VDD 2 7 to 3 6 V VSS 0 V 1 NUM Characteristic Symbol Min Max Unit R1 RSTI Input valid to CLKOUT High tRVCH 10 ns R2 CLKOUT High to RSTI Input invalid tCHRI 2 ns R3 RSTI Input valid Time 2 tRIVT 5 tCYC R4...

Page 769: ... STOP the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to the system Thus RSTI must be held a minimum of 100 ns Table 33 15 I2 C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 Bus clocks I2 Clock low period 8 Bus clocks I3 SCL SDA rise time VIL 0 5 V to VIH 2 4 V 1 mS I4 Data hold time 0 ns I5 SCL...

Page 770: ...to scale the actual data transition time to move it to the middle of the SCL low period The actual position is affected by the prescale and division values programmed into the IFDR however the numbers given in Table 33 16 are minimum values Start condition hold time 6 Bus clocks I2 1 Clock low period 10 Bus clocks I3 2 2 Because SCL and SDA are open collector type outputs which the processor can o...

Page 771: ...K maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed twice the ETXCLK frequency The transmit outputs ETXD 3 0 ETXEN ETXER can be programmed to transition from either the rising or falling edge of ETXCLK and the timing is the same in either case This options allows the use of non compliant MII PHYs Refer to the Ethernet chap...

Page 772: ... 33 12 MII Async Inputs Timing Diagram Table 33 18 MII Transmit Signal Timing Num Characteristic1 1 ETXCLK ETXD0 and ETXEN have the same timing in 10 Mbit 7 wire interface mode Min Max Unit M5 ETXCLK to ETXD 3 0 ETXEN ETXER invalid 5 ns M6 ETXCLK to ETXD 3 0 ETXEN ETXER valid 25 ns M7 ETXCLK pulse width high 35 65 ETXCLK period M8 ETXCLK pulse width low 35 65 ETXCLK period Table 33 19 MII Async In...

Page 773: ...ed in Table 33 20 Figure 33 13 MII Serial Management Channel Timing Diagram Table 33 20 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 EMDC falling edge to EMDIO output invalid minimum propagation delay 0 ns M11 EMDC falling edge to EMDIO output valid max prop delay 25 ns M12 EMDIO input to EMDC rising edge setup 10 ns M13 EMDIO input to EMDC rising edge hold 0 ns M14 EMD...

Page 774: ... 1 All timing references to CLKOUT are given to its rising edge when bit 3 of the SDRAM control register is 0 Min Max Unit T1 DTIN0 DTIN1 DTIN2 DTIN3 cycle time 3 tCYC T2 DTIN0 DTIN1 DTIN2 DTIN3 pulse width 1 tCYC Table 33 22 QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit QS1 QSPI_CS 3 0 to QSPI_CLK 1 tcyc 510 tcyc ns QS2 QSPI_CLK high to QSPI_DOUT valid 12 ns QS3 QSPI_CLK ...

Page 775: ...ns 4 TCLK Rise and Fall Times tJCRF 0 0 3 0 ns 5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 5 0 ns 6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 25 0 ns 7 TCLK Low to Boundary Scan Output Data Valid tBSDV 0 0 30 0 ns 8 TCLK Low to Boundary Scan Output High Z tBSDZ 0 0 30 0 ns 9 TMS TDI Input Data Setup Time to TCLK Rise tTAPBST 5 0 ns 10 TMS TDI Input Data Hold Time afte...

Page 776: ...igure 33 17 Test Access Port Timing Figure 33 18 TRST Timing Input Data Valid Output Data Valid Output Data Valid TCLK Data Inputs Data Outputs Data Outputs Data Outputs VIL VIH 5 6 7 8 7 Input Data Valid Output Data Valid Output Data Valid TCLK TDI TDO TDO TDO TMS VIL VIH 9 10 11 12 11 BKPT TCLK TRST 14 13 ...

Page 777: ... D1 PST DDATA to TCLK setup 5 ns D2 TCLK to PST DDATA hold 2 ns D3 DSI to DSCLK setup 1 CLKOUT cycles D4 1 1 DSCLK and DSI are synchronized internally D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT DSCLK to DSO hold 4 CLKOUT cycles D5 DSCLK cycle time 5 CLKOUT cycles D6 BKPT input data setup time to CLKOUT Rise 5 0 ns D7 BKPT input data hold time to CLKOUT R...

Page 778: ...al time trace timing for the values in Table 33 24 Figure 33 20 Real Time Trace AC Timing Figure 33 21 shows BDM serial port AC timing for the values in Table 33 24 Figure 33 21 BDM Serial Port AC Timing CLKOUT PST 3 0 D2 D1 DDATA 3 0 DSI DSO Current Next CLKOUT Past Current DSCLK D3 D4 D5 ...

Page 779: ...4 Access Control Register 0 ACR0 32 CPU 0x005 Access Control Register 1 ACR1 32 CPU 0x800 Other Stack Pointer OTHER_A7 32 CPU 0x801 Vector Base Register VBR 32 CPU 0x804 MAC Status Register MACSR 8 CPU 0x805 MAC Mask Register MASK 16 CPU 0x806 MAC Accumulator 0 ACC0 16 CPU 0x807 MAC Accumulator 0 1 extension bytes ACCext01 16 CPU 0x808 MAC Accumulator 2 3 extension bytes ACCext23 16 CPU 0x809 MAC ...

Page 780: ...roller 0 256 bytes IPSBAR 0x00_0D00 Interrupt Controller 1 256 bytes IPSBAR 0x00_0F00 Global Interrupt Acknowledge Cycles 256 bytes IPSBAR 0x00_1000 Fast Ethernet Controller Registers and MIB RAM 1 K IPSBAR 0x00_1400 Fast Ethernet Controller FIFO Memory 1K IPSBAR 0x10_0000 Ports 64K IPSBAR 0x11_0000 Reset Controller Chip Configuration and Power Management 64K IPSBAR 0x12_0000 Clock Module 64K IPSB...

Page 781: ... 8 IPSBAR 0x028 Peripheral Access Control Register 4 PACR4 8 IPSBAR 0x02A Peripheral Access Control Register 5 PACR5 8 IPSBAR 0x02B Peripheral Access Control Register 6 PACR6 8 IPSBAR 0x02C Peripheral Access Control Register 7 PACR7 8 IPSBAR 0x02E Peripheral Access Control Register 8 PACR8 8 IPSBAR 0x030 Grouped Peripheral Access Control Register 0 GPACR0 8 IPSBAR 0x031 Grouped Peripheral Access C...

Page 782: ...ct Control Register 6 CSCR6 16 DMA Registers IPSBAR 0x100 Source Address Register 0 SAR0 32 IPSBAR 0x104 Destination Address Register 0 DAR0 32 IPSBAR 0x108 DMA Control Register 0 DCR0 32 IPSBAR 0x10C Byte Count Register 0 BCR01 32 IPSBAR 0x110 DMA Status Register 0 DSR0 8 IPSBAR 0x140 Source Address Register 1 SAR1 32 IPSBAR 0x144 Destination Address Register 1 DAR1 32 IPSBAR 0x148 DMA Control Re...

Page 783: ...Baud Rate Generator Register 10 UBG10 8 IPSBAR 0x21C Read Reserved3 8 UART Baud Rate Generator Register 20 UBG20 8 IPSBAR 0x234 Read UART Input Port Register 0 UIP0 8 Write Reserved3 8 IPSBAR 0x238 Read Reserved3 8 Write UART Output Port Bit Set Command Register 0 UOP10 8 IPSBAR 0x23C Read Reserved3 8 Write UART Output Port Bit Reset Command Register 0 UIP00 8 IPSBAR 0x240 UART Mode Registers 12 U...

Page 784: ...T Status Register 2 USR2 8 Write UART Clock Select Register 21 UCSR2 8 IPSBAR 0x288 Read Reserved3 8 Write UART Command Register 2 UCR2 8 IPSBAR 0x28C Read UART Receive Buffer 2 URB2 8 Write UART Transmit Buffer 2 UTB2 8 IPSBAR 0x290 Read UART Input Port Change Register 2 UIPCR2 8 Write UART Auxiliary Control Register 21 UACR2 8 IPSBAR 0x294 Read UART Interrupt Status Register 2 UISR2 8 Write UART...

Page 785: ...r Extended Mode Register 0 DTXMR0 8 IPSBAR 0x403 DMA Timer Event Register 0 DTER0 8 IPSBAR 0x404 DMA Timer Reference Register 0 DTRR0 32 IPSBAR 0x408 DMA Timer Capture Register 0 DTCR0 32 IPSBAR 0x40C DMA Timer Counter Register 0 DTCN0 32 IPSBAR 0x440 DMA Timer Mode Register 1 DTMR1 16 IPSBAR 0x442 DMA Timer Extended Mode Register 1 DTXMR1 8 IPSBAR 0x443 DMA Timer Event Register 1 DTER1 8 IPSBAR 0...

Page 786: ...R 0xC42 Interrupt Control Register 0 02 ICR002 8 IPSBAR 0xC43 Interrupt Control Register 0 03 ICR003 8 IPSBAR 0xC44 Interrupt Control Register 0 04 ICR004 8 IPSBAR 0xC45 Interrupt Control Register 0 05 ICR005 8 IPSBAR 0xC46 Interrupt Control Register 0 06 ICR006 8 IPSBAR 0xC47 Interrupt Control Register 0 07 ICR007 8 IPSBAR 0xC48 Interrupt Control Register 0 08 ICR008 8 IPSBAR 0xC49 Interrupt Cont...

Page 787: ...ICR037 8 IPSBAR 0xC66 Interrupt Control Register 0 38 ICR038 8 IPSBAR 0xC67 Interrupt Control Register 0 39 ICR039 8 IPSBAR 0xC68 Interrupt Control Register 0 40 ICR040 8 IPSBAR 0xC69 Interrupt Control Register 0 41 ICR041 8 IPSBAR 0xC6A Interrupt Control Register 0 42 ICR042 8 IPSBAR 0xC6B Interrupt Control Register 0 43 ICR043 8 IPSBAR 0xC6C Interrupt Control Register 0 44 ICR044 8 IPSBAR 0xC6D ...

Page 788: ...ster High 1 IPRH1 32 IPSBAR 0xD04 Interrupt Pending Register Low 1 IPRL1 32 IPSBAR 0xD08 Interrupt Mask Register High 1 IMRH1 32 IPSBAR 0xD0C Interrupt Mask Register Low 1 IMRL1 32 IPSBAR 0xD10 Interrupt Force Register High 1 INTFRCH1 32 IPSBAR 0xD14 Interrupt Force Register Low 1 INTFRCL1 32 IPSBAR 0xD18 Interrupt Level Request Register 1 ILRR1 8 IPSBAR 0xD19 Interrupt Acknowledge Level and Prior...

Page 789: ...pt Acknowledge Cycle Registers IPSBAR 0xFE0 Global Software Interrupt Acknowledge Register GSWACKR 8 IPSBAR 0xFE4 Global Level 1 Interrupt Acknowledge Register GL1IACKR 8 IPSBAR 0xFE8 Global Level 2 Interrupt Acknowledge Register GL2IACKR 8 IPSBAR 0xFEC Global Level 3 Interrupt Acknowledge Register GL3IACKR 8 IPSBAR 0xFF0 Global Level 4 Interrupt Acknowledge Register GL4IACKR 8 IPSBAR 0xFF4 Global...

Page 790: ... Ring ETDSR 32 IPSBAR 0x1188 Maximum Receive Buffer Size EMRBR 32 IPSBAR 0x1200 0x13FF RAM used to store management counters MIB_RAM 32 GPIO Registers IPSBAR 0x10_0000 Port A Output Data Register PORTA 8 IPSBAR 0x10_0001 Port B Output Data Register PORTB 8 IPSBAR 0x10_0002 Port C Output Data Register PORTC 8 IPSBAR 0x10_0003 Port D Output Data Register PORTD 8 IPSBAR 0x10_0004 Port E Output Data R...

Page 791: ...8 IPSBAR 0x10_0017 Port D Data Direction Register DDRD 8 IPSBAR 0x10_0018 Port E Data Direction Register DDRE 8 IPSBAR 0x10_0019 Port F Data Direction Register DDRF 8 IPSBAR 0x10_001A Port G Data Direction Register DDRG 8 IPSBAR 0x10_001B Port H Data Direction Register DDRH 8 IPSBAR 0x10_001C Port J Data Direction Register DDRJ 8 IPSBAR 0x10_001D Port DD Data Direction Register DDRDD 8 IPSBAR 0x10...

Page 792: ...Data Register PORTGP SETG 8 IPSBAR 0x10_002F Port H Pin Data Set Data Register PORTHP SETH 8 IPSBAR 0x10_0030 Port J Pin Data Set Data Register PORTJP SETJ 8 IPSBAR 0x10_0031 Port DD Pin Data Set Data Register PORTDDP SETDD 8 IPSBAR 0x10_0032 Port EH Pin Data Set Data Register PORTEHP SETEH 8 IPSBAR 0x10_0033 Port EL Pin Data Set Data Register PORTELP SETEL 8 IPSBAR 0x10_0034 Port AS Pin Data Set ...

Page 793: ...x10_0045 Port DD Clear Output Data Register CLRDD 8 IPSBAR 0x10_0046 Port EH Clear Output Data Register CLREH 8 IPSBAR 0x10_0047 Port EL Clear Output Data Register CLREL 8 IPSBAR 0x10_0048 Port AS Clear Output Data Register CLRAS 8 IPSBAR 0x10_0049 Port QS Clear Output Data Register CLRQS 8 IPSBAR 0x10_004A Port SD Clear Output Data Register CLRSD 8 IPSBAR 0x10_004B Port TC Clear Output Data Regis...

Page 794: ...nfiguration and Power Management Registers IPSBAR 0x11_0000 Reset Control Register RCR 8 IPSBAR 0x11_0001 Reset Status Register RSR 8 IPSBAR 0x11_0004 Chip Configuration Register CCR 16 IPSBAR 0x11_0007 Low Power Control Register LPCR 8 IPSBAR 0x11_0008 Reset Configuration Register RCON 16 IPSBAR 0x11_000A Chip Identification Register CIR 16 Clock Module Registers IPSBAR 0x12_0000 Synthesizer Cont...

Page 795: ...0x15_0002 PIT Modulus Register 0 PMR 0 16 IPSBAR 0x15_0004 PIT Count Register 0 PCNTR 0 16 Programmable Interrupt Timer 1 Registers IPSBAR 0x16_0000 PIT Control and Status Register 1 PCSR 1 16 IPSBAR 0x16_0002 PIT Modulus Register 1 PMR 1 16 IPSBAR 0x16_0004 PIT Count Register 1 PCNTR 1 16 Programmable Interrupt Timer 2 Registers IPSBAR 0x17_0000 PIT Control and Status Register 2 PCSR 2 16 IPSBAR ...

Page 796: ...W0 CCW63 64x16 0x19_0280 0x19_02FE Right Justified Unsigned Result Register RJURR0 RJURR63 64x16 0x19_0300 0x19_037E Left Justified Signed Result Register LJSRR0 LJSRR63 64x16 0x19_0380 0x19_03FE Left Justified Unsigned Result Register LJURR0 LJURR63 64x16 General Purpose Timer A Registers IPSBAR 0x1A_0000 GPTA IC OC Select Register GPTAIOS 8 IPSABAR 0x1A_0001 GPTA Compare Force Register GPTACFORC...

Page 797: ...ister GPTAPACTL 8 IPSBAR 0x1A_0019 Pulse Accumulator Flag Register GPTPAFLG 8 IPSBAR 0x1A_001a Pulse Accumulator Counter Register GPTAPACNT 8 IPSBAR 0x1A_001D GPTA Port Data Register GPTAPORT 8 IPSBAR 0x1A_001E GPTA Port Data Direction Register GPTADDR 8 General Purpose Timer B Registers IPSBAR 0x1B_0000 GPTB IC OC Select Register GPTBIOS 8 IPSBAR 0x1B_0001 GPTB Compare Force Register GPTBCFORC 8 ...

Page 798: ...1B_0016 GPTB Channel 3 Register GPTBC3 16 IPSBAR 0x1B_0018 Pulse Accumulator Control Register GPTBPACTL 8 IPSBAR 0x1B_0019 Pulse Accumulator Flag Register GPTBPAFLG 8 IPSBAR 0x1B_001A Pulse Accumulator Counter Register GPTBPACNT 16 IPSBAR 0x1B_001D GPTB Port Data Register GPTBPORT 8 IPSBAR 0x1B_001E GPTB Port Data Direction Register GPTBDDR 8 FlexCAN Registers IPSBAR 0x1C_0000 Module Configuration...

Page 799: ...MSEC 32 IPSBAR 0x1D_0010 CFM Protection Register CFMPROT 32 IPSBAR 0x1D_0014 CFM Supervisor Access Register CFMSACC 32 IPSBAR 0x1D_0018 CFM Data Access Register CFMDACC 32 IPSBAR 0x1D_0020 CFM User Status Register CFMUSTAT 8 IPSBAR 0x1D_0024 CFM Command Register CFMCMD 8 1 The DMA module originally supported a left justified 16 bit byte count register BCR This function was later reimplemented as a...

Page 800: ...A 22 MCF5282 User s Manual MOTOROLA ...

Page 801: ... 36 WRITE 29 26 CPU halt 29 16 operation with processor 29 39 packet format receive 29 19 transmit 29 19 recommended pinout 29 46 register accesses EMAC 29 33 stack pointer 29 33 serial interface 29 18 timing diagrams BDM serial port AC timing 33 28 real time trace AC timing 33 28 Bit error BITERR 25 29 Bit reverse register BITREV instruction 2 29 Bit stuff error STUFFERR 25 29 Branch instruction ...

Page 802: ...0 2 Chip select module 8 16 and 32 bit port sizing 12 4 memory map 12 5 operation external boot 12 4 general 12 3 low power modes 7 8 port sizing 12 4 overview 12 1 registers address CSARn 12 6 control CSCRn 12 8 mask CSMRn 12 7 CLAMP 31 11 Clock module block diagram 9 3 features 9 1 memory map 9 5 operation 1 1 PLL mode 9 2 during reset 9 11 external clock mode 9 2 low power modes 7 11 9 2 normal...

Page 803: ...g model 29 5 registers address attribute trigger AATR 29 8 address breakpoint ABLR ABHR 29 9 configuration status CSR 29 10 data breakpoint mask DBR DBMR 29 12 program counter breakpoint mask PBR PBMR 29 13 trigger definition TDR 29 14 support real time 29 37 taken branch 29 4 trace real time 29 3 Debug interrupt 2 15 29 38 Divide by zero exception 2 14 DMA controller channel prioritization 16 13 ...

Page 804: ...ion fractional 3 8 general 3 3 programming model 2 5 registers BDM accesses 29 33 mask MASK 3 11 status MACSR 3 6 ENABLE_TEST_CTRL instruction 31 10 End of frame EOF 25 13 EPORT low power modes 7 12 11 1 memory map 11 3 overview 11 1 programming model 7 1 registers data direction EPDDR 11 4 flag EPFR 11 6 pin assignment EPPAR 11 4 pin data EPPDR 11 6 port data EPDR 11 5 port interrupt enable EPIER...

Page 805: ...n fault halt 2 16 29 17 FEC see Ethernet FF1 instruction 2 31 Fill buffer 4 1 Flash see ColdFire Flash module FlexCAN bit timing 25 14 CAN system overview 25 4 error counters 25 15 features 25 1 format frames 25 5 25 7 IDLE bit 25 29 initialization sequence 25 16 interrupts 25 19 memory map 25 3 message buffers BUSY 25 6 EMPTY 25 6 FULL 25 6 handling 25 10 locking and releasing 25 12 receive deact...

Page 806: ...ontrol 1 2 GPTSCRn 20 8 20 11 toggle on overflow GPTTOV 20 9 reset 20 21 GPIO block diagram 26 2 electrical characteristics timing 33 17 features 26 3 initialization 26 26 memory map 26 6 operation 26 3 low power modes 7 10 overview 26 1 26 3 registers port AS pin assignment PASPAR 26 19 port B C D pin assignment PBCDPAR 26 14 port clear output data CLRn 26 12 port data direction DDRn 26 9 port E ...

Page 807: ...10 1 prioritization 10 3 priority mask I bit 2 7 programmable interrupt timers 19 8 QADC operation 27 75 sources 27 76 recognition 10 3 sources 10 12 vector determination 10 4 memory map 10 5 operation general 10 3 low power modes 7 10 registers IACKLPRn 10 11 interrupt control ICRnx 10 11 interrupt force high low INTFRCHn INTFRCLn 10 9 interrupt pending high low IPRHn IPRLn 10 6 interrupt request...

Page 808: ...ers 20 4 GPIO 26 6 interrupt controller 10 5 JTAG 31 5 power management 7 2 programmable interrupt timers 19 3 QADC 27 7 reset controller 28 3 SCM 8 2 8 15 SDRAM controller 15 4 watchdog timer 18 2 Message buffers extended format frames 25 5 25 7 handling 25 10 overload frames 25 13 receive codes 25 6 deactivation 25 11 error status flag RXWARN 25 29 pin configuration control RXMODE 25 23 remote f...

Page 809: ...ogramming model 7 1 registers low power control LPCR 7 4 low power interrupt control LPICR 7 2 Prescaler divide PRESDIV bits 25 25 Privilege violation exception 2 14 Processor status 29 3 29 40 Program counter 2 3 Programmable interrupt timers block diagram 19 1 interrupts 19 8 memory map 19 3 operation free running 19 7 low power modes 7 12 19 2 set and forget 19 6 overview 19 1 registers control...

Page 810: ...ed unsigned result RJURR 27 29 status 0 1 QASRn 27 19 27 26 successive approximation SAR 27 37 test QADCTEST 27 9 result coherency 27 31 stress conditions 27 69 timing diagrams conversion in gated mode continuous scan 27 67 conversion in gated mode single scan 27 66 conversion timing 27 36 conversion timing bypass mode 27 36 QSPI baud rate selection 22 6 description 22 1 electrical characteristics...

Page 811: ...MFR 17 29 MII speed control MSCR 17 31 opcode pause duration OPD 17 37 physical address low 17 35 physical address low high PALR PAUR 17 35 receive buffer size EMRBR 17 44 receive control RCR 17 33 receive descriptor active RDAR 17 26 receive descriptor ring start ERDSR 17 42 registers transmit buffer descriptor ring start ETSDR 17 43 transmit control TCR 17 34 transmit descriptor active TDAR 17 2...

Page 812: ...ata direction DDRQA DDRQB 27 10 result word table 27 62 right justified unsigned result RJURR 27 29 status 0 1 QASRn 27 19 27 26 successive approximation SAR 27 37 test QADCTEST 27 9 QSPI address QAR 22 14 command RAM QCRn 22 15 data QDR 22 14 delay QDLYR 22 11 interrupt QIR 22 13 mode QMR 22 10 wrap QWR 22 12 reset controller control RCR 28 3 status RSR 28 4 SCM bus master park MPARK 8 12 core re...

Page 813: ...block diagram 15 2 burst page mode 15 13 definitions 15 1 example DACR initialization 15 21 DCR initialization 15 20 DMR initialization 15 22 initialization code 15 24 interface configuration 15 20 initialization 15 17 interfacing 15 13 memory map 15 4 operation general 15 3 low power modes 7 8 synchronous address multiplexing 15 9 general guidelines 15 9 overview 15 1 registers address and contro...

Page 814: ...0 14 23 transmit data 1 3 ETXD3 1 14 24 transmit enable ETXEN 14 23 transmit error ETXER 14 24 external boot mode 14 17 FlexCAN receive CANRX 14 26 transmit CANTX 14 26 general purpose timers external clock input SYNCx 14 27 20 4 GPTB3 0 14 27 GPTn2 0 20 3 GPTn3 20 4 GPTx3 0 14 27 I2C serial clock SCL 14 26 serial data SDA 14 26 interrupts IRQ7 1 14 23 JTAG JTAG_EN 31 3 TCLK 31 4 test data input d...

Page 815: ...purpose timers programmable interrupt see programmable inter rupt timers watchdog see watchdog timer 18 2 Timing diagrams debug BDM serial port AC timing 33 28 real time trace AC timing 33 28 Ethernet MII async input signal 33 22 general input timing requirements 33 11 GPIO 33 18 digital input 26 25 digital output 26 26 I2 C input output timing 33 20 JTAG BKPT timing 33 27 boundary scan 33 26 test...

Page 816: ...r UBG1n UBG2n 23 14 input port UIPn 23 15 interrupt status mask UISRn UIMRn 23 13 mode 2 1 UMRnn 23 4 23 6 output port command UOP1n UOP0n 23 15 receive buffers URBn 23 11 status USRn 23 7 transmit buffers UTBn 23 11 User programming model 2 2 V Variant address 29 4 W Wait mode 7 6 Wake interrupt WAKEINT 25 18 25 30 Watchdog timer block diagram 18 2 memory map 18 2 operation low power 7 12 18 1 ov...

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