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9 CREATING A HARDWARE LOGIC
9.1 Main Blocks in the Hardware Logic Outline Window
Setting examples of the SSI encoder block
This section shows setting examples of the SSI encoder block suitable for a receive frame from the SSI encoder and
communication specifications.
■
Multi turn
The following example is for the receive frame of a multi turn encoder. The receive frame consists of the elements below.
• Multi turn: 13 bits
• Single turn: 14 bits
• Status bit: 1 bit
• Parity bit: 1 bit
• Parameter
*1 For details on the encoder specifications, refer to the manual for the encoder used.
• Parameters of "Data Frame Setting"
*2 For details on the encoder specifications, refer to the manual for the encoder used.
Encoder specifications
SSI encoder block setting
Remarks
Item
Setting value
Encoder type
Multi turn
Encoder Type
Multi Turn
Transmission speed
1MHz
Transmission Speed
1.0MHz
Monoflop time
16
μ
s
Monoflop Time
16
Signal Error Detection
Enable
Set "Enable" to use the signal error detection.
Set "Disable" not to use it.
Direction
Forward
Set "Forward" to count a position data from the
SSI encoder in the forward direction. Set
"Reverse" to reverse the counting direction.
Encoder specifications
SSI encoder block setting
Remarks
Item
Setting value
Data type
Gray
Input Data Type
Gray code
Data frame length
28 bits
Data Frame Length
28
The parity bit is not included.
Multi turn data length
13 bits
Multi Turn Data Length
13
Multi turn data start bit
position
0
Multi Turn Start Bit
0
Specify the receive frame bit position where
multi turn data starts.
Encoder resolution
16384
Encoder Resolution
0
Changing the setting value from its default (0) is
not required because the single turn data length
is 14 bits and the encoder resolution is 16384 (=
2
14
).
Single turn data length
14 bits
Single Turn Data Length
14
Single turn data start bit
position
13
Single Turn Start Bit
0
Setting is not required.
Parity check
Odd parity
Parity
Odd
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
M12 M11M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
S
P
Clock
DATA
Multi turn start bit position
Receive frame
bit position
Most
significant bit
Least significant bit
Multi turn: 13 bits
Single turn: 14 bits
Data frame length: 28 bits
Parity bit
Status bit: 1 bit
Summary of Contents for MELSEC-L Series LD40PD01
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