Mitsubishi Electric MELSEC-L Series LD40PD01, User Manual

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9 CREATING A HARDWARE LOGIC
9.1 Main Blocks in the Hardware Logic Outline Window
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9
■
Delay time
A delay time is calculated by multiplying "Delay Time(Unit)" by "Delay Time(Step)".
An error of one unit time may be generated in delay time. However, the error can be reduced by setting the delay time as
shown below.
• Change the value of "Delay Time (Unit)" as small as possible.
• Set a large value for "Delay Time (Step)".
Ex.
The following table lists examples of the delay time of 20 μ s. Compared with example 2, an error is smaller in the setting of
example 1.
■ Link with SSI encoder blocks
When an SSI encoder block is arranged in the hardware logic outline window, the "Clock" terminal of the SSI encoder block
and the "Input" terminal of an external output block are automatically linked.
The default value is set for the setting value of the external output block automatically linked and the value cannot be
changed.
High/Low states of external output signals
The following table lists the High/Low states of external output signals in each setting combination of input signals to external
output blocks and "Logic Select".
When an error occurs in the CPU module, a signal is output according to the output setting of "Error-time Output Mode"
independent of the setting of Inversion or Not-Inversion.
Example Delay Time(Step) Delay Time(Unit) Error
Example 1 1 μ s 20 steps An error of maximum 1 μ s is generated in the output timing.
Example 2 10
μ
s 2 steps An error of maximum 10
μ
s is generated in the output timing.
Output type "Logic Select"
"Non-Inversion" "Inversion"
DC
Differential
High
Low
ON
OFF
Input terminal
OUT Output
High
Low
ON
OFF
Input terminal
OUT Output
High
Low
High
Low
High
Low
Input terminal
OOutput
OUT_DIF -Output
High
Low
High
Low
High
Low
Input terminal
OOutput
OUT_DIF -Output