2-28
Workstation 4 and 4 LX Field Service Guide
WS4 Technical Overview
Complex Programmable Logic Device (CPLD)
NOPOWER
When the workstation is in the
ON
state and the user presses and holds the power
button for more than four seconds, the workstation transitions to the
NOPOWER
state.
Refer to Figure 2-15. When the power button is pressed and held, the CPLD
pulses the
ON_OFF_SW
input to the SC3200 CPU. The power management logic
within the SC3200 CPU responds by setting
ONCTL#
high to disable the +3V
supply. The CPLD logically inverts
ONCTL#
to
ONCTL
disabling the processor
VCORE
regulator, as well as the +5V, +12V, and -12V sections of the on-board
power supply.
The voltages designated ‘Always’ remain active, supplying power to various
components such as the CPLD and Ethernet Controller. +3V Always drives U36,
a LM1117 voltage regulator configured to 2V to the
VSBL
pin of the
processor. This keeps the CPU power management logic active in order to detect
further transitions of the
ON_OFF_SW
signal from the CPLD.
Reset Circuit (REF: AB28/ABRD36 Sheets 12 and 17)
Figure 2-17 shows the AB28 or ABRD36 System Board hardware reset circuit.
Figure 2-17: Workstation 4 Reset Circuit
A Hardware Reset can be produced from one of two sources. The Workstation 4
includes a hardware reset switch mounted to the system board, accessible from the
underside of the workstation. The switch is connected to the CPLD at
RST_IN#
. The
CPLD performs signal conditioning and switch de-bounce, and if
PWRGD
is true,
toggles the
PORST#
signal to the CPU.
