Workstation 4 and 4 LX Field Service Guide
2-23
WS4 Technical Overview
Complex Programmable Logic Device (CPLD)
Complex Programmable Logic Device (CPLD)
REF: AB28/ABRD36 - Sheet 17
AB28 series Workstation 4 System Boards use the ispLSI2064E 44-Pin High Density
Programmable Logic Device, designated U22. This device contains 1000 gates, 32
8-bit registers, and 32 programmable IO pins.
ABRD36-B System Boards feature the ispMACH LC4128V device and the
component designation changes to U49. This device contains a greater number of
gates, registers and programmable IO pins, but retains full compatibility with the
CPLD on the AB28 series of System Boards.
The CPLD performs many WS4 low level control functions including:
•
Power and Reset button control
•
Software reset control
•
LCD Backlight Control
•
Cash Drawer Open and Open Drawer Detection
•
System Board Hardware Revision
•
Resume From Suspend Control
•
Wake On LAN (WOL) Control
CPU Interface and Register Control
The SC3200 CPU communicates to the CPLD through a dedicated interface
composed of several Super IO GPIO pins. The interface consists of seven data bits,
labeled
SIO_PWM0
-
SIO_PWM6
and four control bits labeled
DIR
,
ADDR0
,
ADDR1
,
and
STROBE
. The ABRD36 system board adds another control line called
BTN_CNTR4
since the CLPD used on this board has more internal registers that the
device on the AB28 series system boards.
SIO_PWM0 - SIO_PWM6
contains 7-bits of data to be written to or read from the
CPLD registers. The
DIR
pin determines in which direction information moves on this
bus.
When
DIR
= 0, and the
STROBE
pin transitions from low to high, the 7-bits of data on
SIO_PWM0 - SIO_PWM6
are written to the CLPD register specified by
ADDR0
and
ADDR1.
When
DIR
= 1, and
STROBE
transitions from low to high, the 7-bits of data from the
CPLD register specified by
ADDR0
and
ADDR1
are placed on
SIO_PWM0 -
SIO_PWM6
where it can be read by the CPU.
Table 2-1, on the following page summaries the CPLD control signals.
