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Workstation 4 and 4 LX Field Service Guide
WS4 LX Technical Overview
W83627HF Super IO
W83627HF Super IO
REF: ABRD86 - Sheet 16
The WS4 LX system board includes a Super IO module to cover additional IO
requirements. Some features of the device as used on the LX system board are
mentioned below.
Low Pin Count (LPC) Interface
The interface between the CS5536 Companion Device and the Super IO is based on
the Intel
®
Low Pin Count Interface Specification as described in the LPC 1.0
specification. It is a PCI-like bus composed of seven signal lines used to replace the
traditional legacy ISA bus. Figure 4-4, below provides a brief description of each
interface signal.
Other features include:
•
Specification Rev 1.0 compatible
•
Reduce the cost of traditional ISA bus devices
•
Performs the same bus cycle types as ISA: memory, I/O, DMA, and Bus Master
•
Interrupts are communicated with the serial interrupt (SERIRQ) protocol.
Figure 4-4: Low Pin Count Interface Signal Description
Serial Interface
The Super IO includes two high-speed 16550 UARTs, labelled UART A and UART B.
Each UART includes a 16-byte send/receive FIFO, a programmable baud rate
generator, and complete modem control capabilities.
UART A
UART A is assigned to the IO Panel DB9 COM Port, configured as COM 1.
Name
Type
Description
LAD[3:0]
I/O
LPC Multiplexed Command, Address and
Data
LFRAME#
O
LPC Frame: Indicates the start of an LPC
cycle
LDRQ#
I
LPC Serial DMA/Master Request Inputs:
Used to request DMA or bus master access.
LDRQ[1]#
I
LPC Serial DMA/Master Request Input:
Second DMA or bus master request.
SERIRQ
I/O
Serialized IRQ. Required by devices that
need interrupt support.
