Keysight U3606A, Programmer'S Reference Manual, Page: 29 / 372

Introduction to SCPI 1
SCPI Status System
U3606A Programmer’s Reference 15
Status Byte register
The Status Byte register group reports the conditions from the other
status registers. Clearing an event register from one of the other registers
will clear the corresponding bits in the Status Byte condition register.
Data that is waiting in the U3606A output buffer is immediately reported
on the “Message Available” bit (bit 4).
Bit definitions: Status Byte register
The Status Byte condition register will be cleared when:
• you execute the clear status (
*CLS
) command, or
• you read the event register from one of the other register groups. (Only
the corresponding bits are cleared in the condition register.)
The Status Byte enable register is cleared when you execute the *SRE 0
command.
Bit number Decimal value Definition
0 Not used Not used “0” is returned.
1 Not used Not used “0” is returned.
2 Error queue 4 One or more errors have been stored in the Error Queue. Use the
SYSTem:ERRor?
query to read and delete errors.
3 Questionable Data
summary 8 One or more bits are set in the Questionable Data register. Bits must be
enabled using the
STATus:QUEStionable:ENABle
command.
4 Message available 16 Data is available in the instrument output buffer.
5 Standard Event summary 32 One or more bits are set in the Standard Event register. Bits must be
enabled using the
*ESE
command.
6 Master Status summary 64 One or more bits are set in the Status Byte Register and may generate a
Request for Service (RQS). Bits must be enabled using the
*SRE
command.
7 Not used Not used “0” is returned.
N O T E
Refer to Chapter 15, “IEEE-488.2 Common Commands,” starting on page
319 for more details of the common commands mentioned above.