Intel Xeon, Design Manual

Page: 173 / 305

Design Guide 173
Platform Power Delivery Guidelines
12.2.9 Processor Decoupling
The inductance of the system due to cables and power planes slows the power supply's ability to
respond quickly to a current transient. Decoupling a power plane can be broken into several
independent parts. The closer to the load the capacitor is placed, the more inductance is bypassed.
By bypassing the inductance of leads, power planes etc., less capacitance is required. However,
closer to the load there is less room for capacitance. Therefore, trade-offs must be made.
The Intel Xeon processor causes very large switching transients. These sharp surges of current
occur at the transition between low power mode and high power mode. The designer must support
a current slew rate of 450 A/µs at the socket pins. Larger bulk storage (CBULK), such as
electrolytic capacitors, supply current during longer lasting changes in current demand by the
component, such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition.
All of this power bypassing is required due to the relatively slow speed at which a DC-to-DC
converter can react. A typical voltage converter has a reaction time on the order of 1 µs to 100 µs,
while the processor's current steps are on the order of 100 ns to 200 ns. Bulk capacitance supplies
energy from the time the high-frequency decoupling capacitors are drained, until the power supply
can react to the demand. More correctly, the bulk capacitors in the system slow the transient
requirement seen by the power source to a rate that it is able to supply, while the high-frequency
capacitors slow the transient requirement seen by the bulk capacitors to a rate that they can supply.
A load-change transient occurs when coming out of or entering a low power mode. Load-change
transients for the Intel Xeon processor are on the order of 55 A. These are not only quick changes
in current demand, but also long lasting average current requirements. This occurs when the
STPCLK# pin is asserted or de-asserted, and during Auto HALT. Auto HALT is a low power state
that the processor enters when the HALT op-code is executed.
Note: Note that even during normal operation (not STPCLK# or Halt), the processor current
requirements can change by as much as 70% (± 10%) of the max current very quickly.
Maintaining voltage tolerance during these changes in current requires high-density bulk
capacitors with low Effective Series Resistance (ESR), and low Effective Series Inductance (ESL).
Use thorough analysis when choosing these components.
12.2.9.1 High-Frequency Decoupling
The system boards should include high-frequency capacitors as close to the socket power and
ground pins as possible. Place as many capacitors as possible in the socket cut out area.
Table 12-5
lists the recommended high-frequency capacitance for Intel Xeon processor baseboards.
If there is difficulty in placing the 1210 size 22 µF capacitors (as listed in Table 12-5 ), replace
those with a same number of 1206 size 10 µF capacitors using similar placement guidelines.
However, increase the number of OS-CONs (as defined in
Table 12-6 ) from 9 to 10 to compensate
for the reduced total capacitance.
Table 12-5. Processor High-Frequency Capacitance Recommendations
High-Frequency Capacitance Quantity ESR ESL
0805 Package, 1 µF (Signal Integrity) 8 8 m
Ω
702 pH
1210 Package, 22 µF (Power Decoupling) 20 10 m
Ω
1.1 nH