Intel® Server System S9200WK Product Family Setup and Service Guide
78
Appendix B.
General Memory Population Rules
•
Only multiples of 8 DIMMs are supported to be installed on a compute module (8,16,24).
•
On the compute module, each DIMM slot is labeled by CPU #, die #, memory channel, and slot # such as
CPU0_0_DIMM_A1.
•
Mixing DIMMs of different frequencies and latencies is not supported within or across processors. If a
mixed configuration is encountered, the BIOS attempts to operate at the highest common frequency and
the lowest latency possible.
•
Mixing of DDR4 DIMM Types (RDIMM, LRDIMM) within the processor attached DIMM slots or across
processors is not supported. This is a Fatal Error Halt in Memory Initialization.
•
DIMMs should be populated evenly across memory controllers within a processor.
•
Memory channels should be populated in alphabetical order.
•
For liquid cooled compute modules with DIMMs of 64GB capacity, DIMMs must be populated in pairs to
each side of the memory heat spreaders within the liquid cooling loop, and a DIMM retention clip must
be installed to secure them to the DIMM heat spreader.
Figure 83. DIMM population for liquid cooled compute modules with 8 DIMMs of up to 32GB capacity
