Intel Agilex, Configuration User Manual, Page: 60 / 196

The PFL II IP core supports dual flash memory devices in burst read mode to achieve faster configuration times. You can
connect two MT29EW CFI flash memory devices to the host in parallel using the same data bus, clock, and control signals.
During FPGA configuration, the
AVST_CLK
frequency is four times faster than the
flash_clk
frequency.
Figure 20. PFL II IP core with Dual CFI Flash Memory Devices
The flash memory devices must have the same memory density from the same device family and manufacturer.
CFI Compliant Flash External Host with PFL II IP Core Intel FPGA
CFI Compliant Flash
16
16
ADDR[24..0]
NCE
NWE
NOE
DATA[15..0]
ADDR[24..0]
NCE
NWE
NOE
DATA[15..0]
flash_addr[24..0]
flash_nce
flash_nwe
flash_noe
flash_data[31..0]
fpga_conf_done
fpga_nstatus
fpga_nconfig
avst_data
avst_clk
CONF_DONE
nSTATUS
nCONFIG
AVSTx8_DATA/AVST_DATA
AVSTx8_CLK/AVST_CLK
avst_valid
avst_ready
AVSTx8_VALID/AVST_VALID
AVST_READY
10kΩ
V
CCIO_SDM
10kΩ
V
CCIO_SDM
3.1.10.1.2. Controlling Avalon-ST Configuration with PFL II IP Core
The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory
device, and configure the Intel Agilex device using the Avalon-ST configuration scheme.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Intel
®
Agilex
™
Configuration User Guide
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