3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP
Core
3.1.10.1. Functional Description
You can use the Parallel Flash Loader II Intel FPGA IP (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX
10 devices to complete the following tasks:
•
Program configuration data into a flash memory device using JTAG interface.
•
Configure the Intel Agilex device with the Avalon-ST configuration scheme from the flash memory device.
Note: Intel Agilex device configuration is not available in the current release.
Note:
Use the Parallel Flash Loader II IP Intel FPGA IP and not the earlier Parallel Flash Loader IP with the Avalon-ST configuration
scheme in Intel Agilex devices.
3.1.10.1.1. Generating and Programming a .pof into CFI Flash
The Intel Quartus Prime software generates the
.sof
when you compile your design. You use the
.sof
to generate the
.pof
.
This process includes the following steps:
1. Generating a
.pof
for the PFL II IP using the Intel Quartus Prime File
➤
Programming File Generator.
2. Using the Intel Quartus Prime Programmer to write the Intel Agilex device
.pof
to the flash device.
Figure 19.
Programming the CFI Flash Memory with the JTAG Interface
External
Host
CFI Flash
Memory
Configuration Data
Common
Flash
Interface
PFL II
Quartus Prime
Software
using JTAG
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Intel
®
Agilex
™
Configuration User Guide
59