2.4. Additional Clock Requirements for HPS, PCIe, and HBM2
The Intel Agilex device has additional clock requirements for PCIe, HPS EMIF IP, eSRAM, and the High Bandwidth Memory
(HBM2) IP.
To avoid configuration failures, the Intel Agilex device requires additional clocks for transceivers, PCIe, HPS EMIF IP, and all E-
tile variants. You must provide a free-running, stable reference clock to these blocks before configuration begins. This
reference clock is in addition to the configuration clock requirements for an internal or external oscillator described in
on page 39.
These blocks and their specific clock names are as listed below.
•
HBM2:
pll_ref_clk
and
ext_core_clk
•
HPS EMIF:
pll_ref_clk
•
E-tile transceivers: REFCLK_GXE
•
P-tile transceivers: REFCLK_GXP
Note:
The transceiver power supplies must be at nominal levels for successful configuration. You can use the V
CC
and V
CCP
power
supplies for limited transceiver channel testing. Designs that include many transceivers require an auxiliary power supply to
operate reliably.
2.5. Intel Agilex Configuration Pins
The Intel Agilex device uses SDM_IO pins for device configuration. Here are the states that SDM I/O go through:
1. After power-on, SDM I/O pins 0, 8, and 16 have weak pull-downs. All other SDM I/O pins have weak pull-ups. (These
initial voltage levels ensure correct operation during initialization. For example, for Avalon-ST configuration
SDM_IO8
is
the Avalon-ST ready signal which should not be asserted until the device reaches the FPGA Configuration state.)
2. The Boot ROM samples
MSEL
to determine the configuration scheme you specified and drives pins required for that
configuration scheme. SDM I/O pins not required for the your configuration scheme remain weakly pulled up.
3. In approximately 10 ms the SDM I/O pins take on the state that your design specifies.
4. After device cleaning, the SDM reads pin information from firmware and restores the pin states that your design specifies.
If you reconfigure the device, the SDM uses the updated pin information when initializing the device.
2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09
Intel
®
Agilex
™
Configuration User Guide
25