3.4. JTAG Configuration
JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure
the Intel Agilex FPGA directly with the
.sof
file. Configuration using the JTAG device chain allows faster development because
it does not require you to program an external flash memory. You can also use JTAG to reprogram if the image stored in quad
SPI memory. You can also use the JTAG configuration scheme to reprogram the quad SPI memory if the quad SPI content is
corrupted or invalid.
The Intel Quartus Prime software generates a
.sof
containing the FPGA design information. You can use the
.sof
with a
JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the Intel FPGA Ethernet Cable
both can support the V
CCIO_SDM
supply at 1.8 V. Alternatively, you can use the JamSTAPL Format File (
.jam
) or Jam Byte Code
File (
.jbc
) for JTAG configuration.
Intel Agilex devices automatically compress the configuration bitstream. You cannot disable compression in Intel Agilex
devices.
Table 31.
Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Mode
Data Width (bits)
Max Clock Rate
Max Data Rate
MSEL[2:0]
Passive
JTAG
1
30 MHz
30 Mb
3'b111
Note:
The JTAG port has the highest priority and overrides the
MSEL
pin settings. Consequently, you can configure the Intel Agilex
device over JTAG even if the
MSEL
pin specify a different configuration scheme unless you disabled JTAG for security reasons.
Table 32.
Power Rails for the Intel Agilex Device Configuration Pins
You can view the pin assignments for fixed pins in the Pin-Out File for your device. You specify SDM I/O pin functions using the Device
➤
Configuration
➤
Device and Pin Options dialog box in the Intel Quartus Prime software.
Configuration Function
Pin Type
Direction
Powered by
TCK
Fixed
Input
V
CCIO_SDM
TDI
)
Fixed
Input
V
CCIO_SDM
TMS
)
Fixed
Input
V
CCIO_SDM
continued...
(8)
The JTAG pins can access the HPS JTAG chain in Intel Agilex SoC devices.
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Intel
®
Agilex
™
Configuration User Guide
113