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Contents

1. Intel

®

 Agilex

™

 Configuration User Guide................................................................................................................................ 5

1.1. Intel

®

 Agilex

™

 Configuration Overview.............................................................................................................................5

1.1.1. Configuration and Related Signals....................................................................................................................... 8
1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex Devices................................................................... 9

1.2. Intel Agilex Configuration Architecture........................................................................................................................... 11

1.2.1. Secure Device Manager................................................................................................................................... 12

2. Intel Agilex Configuration Details........................................................................................................................................ 16

2.1. Intel Agilex Configuration Timing Diagram......................................................................................................................16
2.2. Configuration Flow Diagram......................................................................................................................................... 20
2.3. Reset Release Intel FPGA IP......................................................................................................................................... 23
2.4.  Additional Clock Requirements for HPS, PCIe, and HBM2................................................................................................. 25
2.5. Intel Agilex Configuration Pins...................................................................................................................................... 25

2.5.1. SDM Pin Mapping............................................................................................................................................ 26
2.5.2. MSEL Settings................................................................................................................................................ 27
2.5.3. Device Configuration Pins for Optional Configuration Signals................................................................................. 28

2.6. Configuration Clocks....................................................................................................................................................38

2.6.1. Setting Configuration Clock Source....................................................................................................................38
2.6.2. OSC_CLK_1 Clock Input...................................................................................................................................39

3. Intel Agilex Configuration Schemes..................................................................................................................................... 41

3.1. Avalon-ST Configuration.............................................................................................................................................. 41

3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types ................................................................ 43
3.1.2. Enabling Avalon-ST Device Configuration............................................................................................................44
3.1.3. The AVST_READY Signal ................................................................................................................................. 45
3.1.4. RBF Configuration File Format...........................................................................................................................48
3.1.5. Avalon-ST Single-Device Configuration...............................................................................................................49
3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme............................................................................. 52
3.1.7. QSF Assignments for Avalon-ST x8....................................................................................................................53
3.1.8. QSF Assignments for Avalon-ST x16.................................................................................................................. 55
3.1.9. QSF Assignments for Avalon-ST x32.................................................................................................................. 57
3.1.10. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core............................. 59

Contents

Intel

®

 Agilex

™

 Configuration User Guide

Send Feedback

2

Summary of Contents for Agilex

Page 1: ...Intel Agilex Configuration User Guide Updated for Intel Quartus Prime Design Suite 19 3 Subscribe Send Feedback UG 20205 2019 10 09 Latest document on the web PDF HTML...

Page 2: ...Pins for Optional Configuration Signals 28 2 6 Configuration Clocks 38 2 6 1 Setting Configuration Clock Source 38 2 6 2 OSC_CLK_1 Clock Input 39 3 Intel Agilex Configuration Schemes 41 3 1 Avalon ST...

Page 3: ...AG Configuration Scheme Hardware Components and File Types 114 3 4 2 JTAG Device Configuration 115 3 4 3 JTAG Multi Device Configuration 118 3 4 4 Debugging Guidelines for the JTAG Configuration Schem...

Page 4: ...pplication Image 177 5 Intel Agilex Configuration Features 180 5 1 Device Security 180 5 2 Configuration via Protocol 180 5 3 Partial Reconfiguration 182 6 Intel Agilex Debugging Guide 183 6 1 Configu...

Page 5: ...es support design security and partial reconfiguration All Intel Agilex active configuration schemes support remote system update RSU with quad SPI flash memory To implement RSU in passive configurati...

Page 6: ...u can use these pins as regular I Os after the device enters user mode Avalon ST supports backpressure using the AVST_READY and AVST_VALID pins Because the time to decompress the incoming bitstream va...

Page 7: ...ter the Intel Agilex enters user mode you can use the CvP update mode to reconfigure the FPGA fabric This mode has the following advantages Allows reprogramming of the core to run different algorithms...

Page 8: ...availability portability and compatibility Because Intel Agilex devices operate at 1 8 volt an intermediate voltage level shifter may be required to interface with the higher voltage I Os in SD MMC d...

Page 9: ...Intel provides the following cables to download your design to the Intel Agilex device on the PCB Download cables support prototyping activity by providing detailed debug messages via Intel Quartus P...

Page 10: ...ables provides more information about the download cables and includes links to the user guides for all cables listed in the table above 1 Intel Agilex Configuration User Guide UG 20205 2019 10 09 Int...

Page 11: ...ork to distribute the configuration bitstream to Local Sector Managers LSMs You cannot access this network LSMs The LSM is a microprocessor Each configuration sector includes an LSM The LSM parses con...

Page 12: ...p the SDM triple redundant lockstep processors run code from the boot ROM The boot ROM code authenticates the Intel generated configuration firmware and configuration bitstream ensuring that configura...

Page 13: ...artial Reconfiguration PR IP CRAM Hard IP in SDM External Hard IP Soft IP Key External PR Controller IP Temperature Sensor Voltage Sensor Here is an overview of the additional functions the SDM contro...

Page 14: ...ou generate a configuration bitstream using the File Programming File Generator menu item the bitstream assembler adds all firmware including the SDM firmware that matches the Intel Quartus Prime Pro...

Page 15: ...set This use guide defines a state when the FPGA is functional Configuration and initialization are complete When you select the HPS First option the SDM first configures the HPS SDRAM pins loads the...

Page 16: ...xt pullup internal signal UG 20205 2019 10 09 Send Feedback Intel Corporation All rights reserved Agilex Altera Arria Cyclone Enpirion Intel the Intel logo MAX Nios Quartus and Stratix words and logos...

Page 17: ...on The SDM receives the configuration bitstream on the interface that the MSEL bus specified in Step 1 The diagram shows AVST_READY and AVST_VALID continuously high It is possible for AVST_READY to de...

Page 18: ...uring the error state nCONFIG should be in the high state The application must drive nCONFIG from high to low and then from low to high to restart configuration 3 The SDM enters the idle state The ext...

Page 19: ...devices Intel Agilex Device Datasheet For the following timing diagrams that define set up hold and propagation delay timing parameters AS Configuration Serial Output Timing Diagram AS Configuration...

Page 20: ...W nSTATUS LOW Pulse nCONFIG LOW nCONFIG LOW Configuration Pass Flow Configuration Fail Flow Reconfiguration Flow nCONFIG HIGH nSTATUS HIGH nSTATUS LOW nSTATUS HIGH CONF_DONE HIGH INIT_DONE HIGH nCONFI...

Page 21: ...CONFIG high The host should not drive nCONFIG high before all clocks are stable Idle The SDM remains in IDLE state until the external host initiates configuration by driving the nCONFIG pin from low t...

Page 22: ...ult in intermittent application logic failures The nCONFIG pin should remain high in user mode You may re configure the device by driving nCONFIG pin from low to high Device Clean In the Device Clean...

Page 23: ...e function in both FPGA First and HPS First configuration modes Intel recommends that you hold your design in reset while the nINIT_DONE signal is high or while the INIT_DONE pin is low When you insta...

Page 24: ...Intel FPGA IP in your design you must feed the INIT_DONE signal back into your design as an input to your reset logic as shown in this figure Board INIT_DONE Reset Application Logic Intel FPGA 2 Inte...

Page 25: ...uire an auxiliary power supply to operate reliably 2 5 Intel Agilex Configuration Pins The Intel Agilex device uses SDM_IO pins for device configuration Here are the states that SDM I O go through 1 A...

Page 26: ...nts listed in in the table below Use the assignments in this table for MSEL and AVSTx8_DATA0 to AVSTx8_DATA8 and AS x4 Table 3 SDM Pin Mapping for Avalon ST x8 and AS x4 SDM Pins MSEL Function Configu...

Page 27: ...am RUP VCCIO_SDM MSEL 0 4 7k RDN MSEL 0 4 7k OR Table 4 MSEL Settings for Each Configuration Scheme of Intel Agilex Devices Configuration Scheme MSEL 2 0 Avalon ST x32 000 Avalon ST x16 101 Avalon ST...

Page 28: ...r optional configuration signals do not have dedicated pin assignments Device Configuration Pins without Fixed Assignments Note Although the CONF_DONE and INIT_DONE configuration signals are not requi...

Page 29: ...DM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4...

Page 30: ...orted SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 SEU_ERROR SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7...

Page 31: ...O0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16...

Page 32: ...2 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 nCATTRIP SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_...

Page 33: ...le and assign the SDM I O pins using the Intel Quartus Prime software Complete the following steps to assign these additional configuration pins 1 On the Assignments menu click Device 2 In the Device...

Page 34: ...4 Click OK to confirm and close the Configuration Pin dialog box 2 Intel Agilex Configuration Details UG 20205 2019 10 09 Intel Agilex Configuration User Guide Send Feedback 34...

Page 35: ...nd Pin Options dialog box select the Dual Purpose Pins category 3 In the Dual purpose pins table set the pin functionality in the Value column 4 Click OK to confirm and close the Device and Pin Option...

Page 36: ...ut Schmitt Trigger Input Weak pull up SDM_IO 0 SDM_IO 8 SDM_IO 16 SDM I O bank I O Schmitt Trigger Input or 1 8 V LVCMOS 8 Weak pull down SDM_IO 7 1 SDM_IO 15 9 SDM I O bank I O Schmitt Trigger Input...

Page 37: ...and Pin Options Power Management VID Slave device type parameter If you are using a different PMBus regular change the default setting from LTM4677 to Other Figure 10 Specifying the Slave Device Type...

Page 38: ...oscillator or OSC_CLK_1 with the supported frequency By default the SDM uses the internal oscillator for device configuration Specify an OSC_CLK_1 clock source for the fastest configuration time Comp...

Page 39: ...250 MHz Intel Agilex devices include an internal oscillator in addition to OSC_CLK_1 which runs the configuration process at a frequency between 170 230 MHz Intel Agilex devices always use this intern...

Page 40: ...he fastest possible configuration Refer to Setting Configuration Clock Source for instructions setting this frequency using the Intel Quartus Prime Software You can also specify this frequency by edit...

Page 41: ...ion data bus You specify SDM I O pin functions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software For the Avalon ST x16 and x32 configuration you can...

Page 42: ...level translation between the FPGA and external host because some signals to accommodate both power requirements Note Although the INIT_DONE configuration signal is not required for configuration Int...

Page 43: ...lock diagram illustrates the components and design flow using the Avalon ST configuration scheme Figure 11 Components and Design Flow for pof Programming Quartus Software flow on PC Quartus Prime Prog...

Page 44: ...Avalon Interface Specifications for protocol details Note Intel Agilex devices using Avalon ST x32 configuration and DDR x72 external memory interfaces are limited to a maximum of three memory interfa...

Page 45: ...before sending more data The Intel Agilex device asserts the AVST_READY signal when the device is ready to accept data The AVST_READY signal is only valid when the nSTATUS pin is high In addition the...

Page 46: ..._ready_reg2 signal is the AVST_READY signal that is synchronous to AVST_CLK You must properly constrain the AVST_CLK and AVST_DATA signals at the host Perform timing analysis on both signals between t...

Page 47: ...onfiguration scheme only use dual purpose I O pins that you can use as general purpose I O pins after configuration Related Information Avalon Interface Specifications 3 Intel Agilex Configuration Sch...

Page 48: ...ouble Word 01EE1B02 LSB BYTE0 02 BYTE1 1B BYTE2 EE MSB BYTE3 01 D 7 0 D 15 8 D 23 16 D 31 24 0000 0010 0001 1011 1110 1110 0000 0001 Table 11 Writing 16 bit Data For a x16 data bus the first byte in t...

Page 49: ...tion Control Signals Compact Flash Interface External Compact Flash Memory ADDR DATA rbf little endian Control CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_n...

Page 50: ...ct Flash Interface External Compact Flash Memory ADDR DATA rbf little endian Control CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_nconfig fpga_data 15 0 10k...

Page 51: ...ct Flash Interface External Compact Flash Memory ADDR DATA rbf little endian Control CPLD FPGA External Host fpga_clk fpga_ready fpga_valid fpga_conf_done fpga_nstatus fpga_nconfig fpga_data 31 0 10k...

Page 52: ...ceive configuration data The AVST_CLK and AVSTx8_CLK clock signals cannot pause when configuration data is not being transferred Data is not transferred when AVST_READY and AVST_VALID are low The AVST...

Page 53: ...SDM IO Assignments set_global_assignment name USE_PWRMGT_SCL SDM_IO0 set_global_assignment name USE_PWRMGT_SDA SDM_IO12 set_global_assignment name USE_PWRMGT_ALERT SDM_IO9 set_global_assignment name...

Page 54: ...e Software Related Information PMBus Master Mode In the Intel Stratix 10 Power Management User Guide Intel Quartus Prime Pro Settings File Reference Manual 3 Intel Agilex Configuration Schemes UG 2020...

Page 55: ..._assignment name USE_PWRMGT_ALERT SDM_IO9 set_global_assignment name USE_CONF_DONE SDM_IO16 set_global_assignment name USE_SEU_ERROR SDM_IO5 Configuration settings set_global_assignment name STRATIXV_...

Page 56: ...e Software Related Information PMBus Master Mode In the Intel Stratix 10 Power Management User Guide Intel Quartus Prime Pro Settings File Reference Manual 3 Intel Agilex Configuration Schemes UG 2020...

Page 57: ...MGT_ALERT SDM_IO12 set_global_assignment name USE_CONF_DONE SDM_IO5 set_global_assignment name USE_INIT_DONE SDM_IO0 set_global_assignment name USE_SEU_ERROR SDM_IO1 Configuration settings set_global_...

Page 58: ...e Software Related Information PMBus Master Mode In the Intel Stratix 10 Power Management User Guide Intel Quartus Prime Pro Settings File Reference Manual 3 Intel Agilex Configuration Schemes UG 2020...

Page 59: ...not the earlier Parallel Flash Loader IP with the Avalon ST configuration scheme in Intel Agilex devices 3 1 10 1 1 Generating and Programming a pof into CFI Flash The Intel Quartus Prime software ge...

Page 60: ...tel FPGA CFI Compliant Flash 16 16 ADDR 24 0 NCE NWE NOE DATA 15 0 ADDR 24 0 NCE NWE NOE DATA 15 0 flash_addr 24 0 flash_nce flash_nwe flash_noe flash_data 31 0 fpga_conf_done fpga_nstatus fpga_nconfi...

Page 61: ...want to program the flash memory device with non Intel FPGA data for example initialization storage for an ASSP You can use the PFL II IP core to program the flash memory device for the following purp...

Page 62: ...lash Memories in 16 Bit Mode The flash memory addresses in 16 bit flash memory shift one bit down in comparison with the flash addresses in PFL II IP core The flash address in the flash memory starts...

Page 63: ...igure 25 Cypress and Micron M28 M29 Flash Memory in 16 Bit Mode The address bit numbers in the PFL II IP core and the flash memory device are the same 22 21 20 2 1 0 address 23 bits 22 21 20 2 1 0 add...

Page 64: ...KB boundary If the first valid start address is 0x000000 the next valid start address is an multiple of 0x20000 3 1 10 1 5 Storing Option Bits In addition to design data the flash memory stores the o...

Page 65: ...d FPGA Configuration for the What operating mode will be used parameter on the General tab The following figure shows the FPGA Configuration option Figure 26 General Tab of the PFL II IP Select FPGA C...

Page 66: ...s Start address must match the address you specify for What is the byte address of the option bits in hex when specifying the PFL II IP parameters The Intel Quartus Prime Programming File Generator ge...

Page 67: ...ess 0x2C 0x2F Page 5 end address 0x30 0x33 Page 6 start address 0x34 0x37 Page 6 end address 0x38 0x3B Page 7 start address 0x3C 0x3F Page 7 end address 0x40 0x7F Reserved 0x80 6 pof version 0x81 0xFF...

Page 68: ...the start address Table 13 Start Address Bit Content Bit Width Description 31 11 21 Addressable start address 10 1 10 Reserved bits 0 1 Page valid bit 0 Valid 1 Error Table 14 End Address Bit Content...

Page 69: ...2 b00000000110101001011100011000011 0xD4B8C3 The start and end address must be correlated with the start and end address for each page printed in the map file 3 1 10 1 7 Implementing Page Mode and Opt...

Page 70: ...ess Page Valid Page 0 Address Page Valid End Address 0x000000 8 Bits 32 Bits The following figure shows the layout of the option bits for a single page Because the start address must be on an 8 KB bou...

Page 71: ...01 Page Start Address 17 13 Page Start Address 25 18 Page Start Address 33 26 Page End Address 9 2 Page End Address 17 10 Page End Address 25 18 0x002004 0x002005 0x002006 Page End Address 33 26 Page...

Page 72: ...selection 1 Click File Programming File Generator 2 For Device family select Intel Agilex 3 For Configuration mode select Avalon ST configuration scheme that you plan to use 4 For Output directory cli...

Page 73: ...t Files To Generate Input File Source and Configuration Device Generate Selected Files 8 To specify a sof that contains the configuration bitstream on the Input Files tab click Add Bitstream 3 Intel A...

Page 74: ...ces 11 Click OPTIONS and then Edit In the Edit Partition dialog box specify the Start address of the Options in flash memory This address must match the address you specify for What is the byte addres...

Page 75: ...or Flash Device Start address 12 With the flash device selected click Add Partition to specify a partition in flash memory 3 Intel Agilex Configuration Schemes UG 20205 2019 10 09 Send Feedback Intel...

Page 76: ...b For Input File specify the sof c From the Page dropdown list select the page to write this sof d For Address mode select the addressing mode to use The following modes are available 3 Intel Agilex...

Page 77: ...PFL II instantiation for FPGA configuration on the General tab for What operating mode will be used select FPGA Configuration 7 Use this Flash Programming Only instance of the PFL II IP to write data...

Page 78: ...column of the pof 4 Click Start to program the CPLD 5 After the programming progress bar reaches 100 click Auto Detect For example if you are using dual Micron or Macronix flash devices the programmer...

Page 79: ...e Programmer window on the Edit menu select Define New CFI Flash Device The following table lists the three functions available in the Define CFI Flash Device window Table 16 Functions of the Define C...

Page 80: ...lash extended device identifier only applicable for AMD compatible CFI flash memory device Flash device is Intel compatible Turn on the option if the CFI flash is Intel compatible Typical word program...

Page 81: ...to tri state when not in use On Off Allows the PFL II IP core to tri state all pins interfacing with the flash memory device when the PFL II IP core does not require access to the flash memory Table...

Page 82: ...ion The PFL II IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming With a larger FIFO size programming time is shorter Add Block CRC verifi...

Page 83: ...PFL II IP core reconfigures the FPGA with data from the page that failed If you select Retry from fixed address the PFL II IP core reconfigures the FPGA a fixed address What is the byte address to re...

Page 84: ...nals Table 22 PFL II Signals Pin Type Weak Pull Up Function pfl_nreset Input Asynchronous reset for the PFL II IP core Pull high to enable FPGA configuration To prevent FPGA configuration pull low whe...

Page 85: ...are only using the PFL II IP for flash programming pfl_flash_access_request Output For system level synchronization When necessary this pin connects to a processor or an arbiter The PFL II IP core dr...

Page 86: ...vice A low signal resets the flash memory device fpga_nconfig Open Drain Output 10 kW Pull Up Resistor Connects to the nCONFIG pin of the FPGA A low pulse resets the FPGA and initiates configuration T...

Page 87: ...se Input VCCIO_SDM CONF_DONE SDM I O Output VCCIO_SDM AS_nCSO 3 0 SDM I O Output VCCIO_SDM AS_DATA 3 0 SDM I O Bidirectional VCCIO_SDM AS_CLK SDM I O Output VCCIO_SDM Note Although the CONF_DONE and I...

Page 88: ...ng block diagram illustrates the components and design flow using the AS configuration scheme Figure 34 Components and Design Flow for jic Programming Quartus Software flow on PC Quartus Prime Program...

Page 89: ...al flash programming via Intel FPGA JTAG pins This file type is available only for ASx4 configuration A newly populated board using the ASx4 configuration scheme requires initial SDM firmware programm...

Page 90: ...Flash Memory AS_CLK AS_nCS0 Download cable 10 pin male header DATA 3 0 DCLK nCS0 Configuration Control Signals Optional Monitoring 10k Optional Configuration Data Signals To JTAG Header or JTAG Chain...

Page 91: ...e as MSEL only during POR state After the FPGA device enters user mode you can repurpose the MSEL pins as chip select pins You must to ensure appropriate chip select pin connections to the configurati...

Page 92: ...0 1 AS_nCS0 2 AS_nCS0 3 Download cable 10 pin male header JTAG mode DATA 3 0 DCLK CS Configuration Control Signals Configuration Data Signals Optional Monitoring 10k Optional HPS Data Signals MSEL VCC...

Page 93: ...oading and Clock Source Capacitance Loading pF Maximum Supported AS_CLK MHz OSC_CLK_1 MHz Internal Oscillator MHz 10 133 125 115 19 108 115 30 100 77 37 80 77 80 50 58 140 25 25 Related Information MS...

Page 94: ...pacitance loading of the flash device The table below lists the maximum allowable skew delay depending on the AS_CLK frequency Intel recommends that you to perform IBIS simulations to ensure that the...

Page 95: ...party software programs the configuration data directly into the serial flash device You must set MSEL to JTAG When MSEL is set to JTAG the SDM tristates the following AS pins AS_CLK AS_DATA0 AS_DATA3...

Page 96: ...LK nCS AS_DATA 1 AS_DATA 2 AS_DATA 3 AS_CLK 4 7 k VCCIO_SDM GND VCCIO_SDM VCCIO_SDM 10 k MSEL 0 AS_nCSO 0 MSEL 1 MSEL 2 ASfastmode PullMSEL 1 low ASnormalmode PullMSEL 1 high ASfast normalmode PullMSE...

Page 97: ...and programs the serial flash device The SDM emulates AS programming Figure 40 Programming Your Serial Configuration Device Using JTAG and SDM Emulation of AS Intel FPGA Board Secure Device Manager AS...

Page 98: ...2 AS_DATA 3 AS_CLK 4 7 k GND GND VCCIO_SDM VCCIO_SDM 10 k VCCIO_SDM 10 k 4 7 k VCCIO_SDM MSEL 0 AS_nCSO 0 MSEL 1 MSEL 2 ASfastmode PullMSEL 1 lowusing4 7 k resistor ASnormalmode PullMSEL 1 highusing4...

Page 99: ...h JTAG interface and programs the serial flash device 3 2 7 Serial Flash Memory Layout Serial flash devices store the configuration data in sections The following diagram illustrates sections of a non...

Page 100: ...Mb 256 Mb and 512 Mb Micron MT25QU 128 Mb 256 Mb 512 Mb 1 Gb and 2 Gb Micron and Macronix both offer Quad SPI memories a density range of 128Mb 2Gb 3 2 8 AS_CLK The Intel Agilex device drives AS_CLK t...

Page 101: ...nfiguration scheme complete the following steps 1 On the Assignments menu click Device 2 In the Device and Pin Options select the Configuration category a Select Active Serial x4 from the Configuratio...

Page 102: ...acy Convert Programming Files dialog box does not support some advanced programming features for Intel Stratix 10 and later devices Note If you are generating an rpd for remote system update RSU you m...

Page 103: ...e jic and Programmer Object File pof you can turn on the Memory Map File map This option describes flash memory address locations The Input Files tab is now available 7 On the Input Files tab click Ad...

Page 104: ...ce list or define a custom device using the available menu options For more information about defining a custom configuration device refer to the Configuration Device Tab Settings Programming File Gen...

Page 105: ...Figure 45 Programming File Generator Input Files 3 Intel Agilex Configuration Schemes UG 20205 2019 10 09 Send Feedback Intel Agilex Configuration User Guide 105...

Page 106: ...e following steps 1 In the Programmer window click Hardware Setup and select the desired download cable 2 In the Mode list select Active Serial Programming 3 Click Auto Detect button on the left pane...

Page 107: ...tel Agilex device begins assessing the AS x4 device When using AS fast mode all power supplies to the Intel Agilex device must be fully ramped up to the recommended operating conditions before the SDM...

Page 108: ...ccess it Check endianness of the rpd if using a third party programmer to program Quad SPI device You should generate the rpd as big endian 3 2 12 QSF Assignments for AS You can specify many Intel Qua...

Page 109: ...RC_CHECK ON set_global_assignment name MINIMUM_SEU_INTERVAL 479 SmartVID feature PMBus settings Slave mode settings only set_global_assignment name VID_OPERATION_MODE PMBUS SLAVE set_global_assignment...

Page 110: ...tus Prime Software Related Information PMBus Master Mode In the Power Management User Guide Intel Quartus Prime Pro Settings File Reference Manual 3 Intel Agilex Configuration Schemes UG 20205 2019 10...

Page 111: ...nctions using the Device Configuration Device and Pin Options dialog box in the Intel Quartus Prime software Configuration Function Direction Powered by nSTATUS SDM I O Output VCCIO_SDM nCONFIG SDM I...

Page 112: ...ation Pins Configuration Control Signals Configuration Control Signals Optional Monitoring 10k MSEL VCCIO_SDM Optional 4 8 External Level Shifter SD MMC DAT CLK CMD SD Secure Digital 2 7 3 6 v 1 8 v M...

Page 113: ...omatically compress the configuration bitstream You cannot disable compression in Intel Agilex devices Table 31 Intel Agilex Configuration Data Width Clock Rates and Data Rates Mode Data Width bits Ma...

Page 114: ...device is fully in user mode Note Pin Out files are not yet available for Intel Agilex devices Intel Agilex Related Information Programming Support for Jam STAPL Language 3 4 1 JTAG Configuration Sche...

Page 115: ...To configure a single device in a JTAG chain the programming software sets the other devices to bypass mode A device in bypass mode transfers the programming data from the TDI pin to the TDO pin throu...

Page 116: ...TDI TMS Configuration Control Signals JTAG Configuration Pins Optional Monitoring To JTAG Header or JTAG Chain 10k MSEL VCCIO_SDM 3 Pin 1 Download cable 10 pin male header JTAG mode RUP RDN RUP TCK TD...

Page 117: ...a Microprocessor Pin 1 RUP RDN RUP TCK TDO TMS OPEN TDI GND VCCIO_SDM OPEN OPEN GND GND VCCIO_SDM Intel FPGA nCONFIG nSTATUS CONF_DONE INIT_DONE OSC_CLK_1 MSEL 2 0 TCK ADDR DATA Memory Micro Processor...

Page 118: ...vices in a JTAG chain The drive capability of the download cable is the only limit on the number of devices in the JTAG chain If you have four or more devices in a JTAG chain buffer the TCK TDI and TM...

Page 119: ...SDMthrough4 7k externalpull upresistor ForJTAGinconjunctionwithanotherconfigurationscheme ConnectMSEL 2 0 ofIntelFPGAdevicesbasedonthenon JTAGconfigurationscheme GND VCCIO_SDM VCCIO_SDM VCCIO_SDM VCCI...

Page 120: ...y to determine whether the device has exited the POR state is to use the Intel Quartus Prime Programmer to detect the device If the programmer can detect the Intel Agilex device it has exited the POR...

Page 121: ...ices HPS can drive the RSU process For passive configuration schemes an external host implements remote system update rather than the Intel Agilex device To learn more about remote system update for p...

Page 122: ...Remote Connection Remote Connection Data Data Intel FPGA Note An Intel Agilex version of the Intel Stratix 10 SoC Remote System Update RSU User Guide is not yet available The RSU SoC implementation in...

Page 123: ...gs for the external clock source This optional clock source drives OSC_CLK_1 For more information refer to OSC_CLK_1 Clock Input Quad SPI pins Configuration pointer block CPB A list of application ima...

Page 124: ...m update host require an Mailbox Client Intel FPGA IP as shown in the figure below The Mailbox Client sends and receives remote system update operation commands and responses such as QSPI_READ and QSP...

Page 125: ...image contains logic to implement the custom application The application image must also contain logic to obtain new application images and store the images in the flash memory Depending on the stora...

Page 126: ...Pin is asserted No Yes nCONFIG Asserted Decision Firmware Decision Firmware Decision Firmware Decision Firmware Sub Partition Table Configuration Pointer Block Remote Update to Factory Image Remote Up...

Page 127: ...DM traverses the pointer block in reverse order The SDM loads the highest priority image When image loading completes the device enters user mode 5 If loading the newest highest priority image is unsu...

Page 128: ...ity 1 Application Image3 highest priority 2 Application Image2 3 Application image1 4 Application image0 lowest priority Application Image3 Application Image2 and Application Image1 are corrupted RSU_...

Page 129: ...Address Offset M 64 KB Application Image2 Corrupt Address Offset O 64 KB Current Image Last Failing Image Highest Priority Failing Image Application Image3 Corrupt Address Offset P 64 KB Related Info...

Page 130: ...ge using the Programming File Generator The image contains the new factory Image decision firmware and decision firmware data 2 Program the factory update image rpd to an empty partition slot starting...

Page 131: ...JTAG to Avalon Master Bridge IP as a remote system update host controller The remote system update host controller controls the remote system update function by sending commands to and receiving respo...

Page 132: ...iguring the device with an application or factory image i From factory image to an application image or vice versa ii From an application image to another application image b Erasing the application i...

Page 133: ...n the command header must match the command length of corresponding command The following table describes the fields of the header command Your client must read all the response words even if your cli...

Page 134: ...r the factory or an application image This command takes an optional 64 bit argument that specifies the reconfiguration data address in the flash If you do not provide this argument its value is assum...

Page 135: ...1 Version The version of the RSU data structure 2 Pin status Bit 31 Current nSTATUS output value active low Bit 30 Detected nCONFIG input value active low Bit 29 3 Reserved Bit 2 0 The MSEL value at...

Page 136: ...ge The error field has two parts Upper 16 bits Major error code Lower 16 bits Minor error code Returns 0 for no failures Refer to the Table 36 on page 139 and Table 37 on page 140 for more information...

Page 137: ...he quad SPI until the active client relinquishes access using the QSPI_CLOSE command QSPI_CLOSE 33 0 1 Closes the exclusive access to the quad SPI interface QSPI_SET_CS 34 1 1 Specifies one of the att...

Page 138: ...ne word The address must be the start address of a sector within the flash memory consequently the address must be 64 KB aligned Returns an error for non 64 KB aligned addresses The number of words to...

Page 139: ...60000 Clear error status information All other values are reserved This command is not available before version 19 3 of the Intel Quartus Prime Pro Edition Software Table 36 CONFIG_STATUS and RSU_STAT...

Page 140: ...ntication failure for the firmware 0xD002 RSU_USER_AUTH_ERR Authentication failure for the design 0xD003 RSU_CMF_DESC_SHA_MISMATCH The SHA does not match for the firmware descriptor 0xD004 RSU_POINTER...

Page 141: ...te either an initialization or configuration problem 100 NOT_CONFIGURED Indicates that the device is not configured 1FF ALT_SDM_MBOX_RESP_DEVICE_BUSY Indicates that the device is busy 2FF ALT_SDM_MBOX...

Page 142: ...4 1 2 RSU Flash Layout SDM Perspective In the RSU case decision firmware replaces the standard firmware The decision firmware copies have pointers to the following structures in flash Decision data O...

Page 143: ...at connect to quad SPI flash memory The Direct to Factory Image pin that forces the SDM to load the factory image You can set this pin on the following menu Assignments Device Device and Pin Options C...

Page 144: ...tes the SPT when creating the initial manufacturing image To ensure reliable operation the Programming File Generator creates two copies sub partition table and the configuration pointer block SPT0 an...

Page 145: ...tten directly SDM does not use To summarize your view of flash memory is different from SDM view in two ways You do not need to know the addresses of the decision firmware decision firmware data and f...

Page 146: ...d Pointer block copy 1 CPB1 Next varies Application image 1 You assign Next varies Application image 2 You assign The Intel Quartus Prime Programming File Generator allows you to create many user part...

Page 147: ...partition name including a null string terminator 0x10 8 Sub partition start offset 0x18 4 Sub partition length 0x1C 4 Sub partition flags 4 4 2 3 Configuration Pointer Block Layout The configuration...

Page 148: ...k compression This procedure is safe There are two copies of pointer block The copies are in different flash erase sectors While one copy is being updated the other copy is still valid 4 4 2 4 Modifyi...

Page 149: ...Pointer Block Layout topic When compressing the client compresses erase and rewrite the primary CPB completely Once the primary CPB is valid it is safe to modify the secondary CPB When rewriting the m...

Page 150: ...ed at address zero then update the pointers to match the actual location Here is the procedure to update the pointers from a application image created for INITIAL_ADDRESS to NEW_ADDRESS 1 Create the a...

Page 151: ...pdate flash programming files 4 5 1 Generating the Initial RSU Image Note Program file generation is not available for Intel Agilex devices in the current release Follow these steps to generate the in...

Page 152: ...age 7 image is the lowest priority 13 For jic files Click Select at the Flash loader select your device family and device name and click OK 14 Click Generate to generate the remote system update progr...

Page 153: ...the RSU image from the command line directly by running the quartus_pfg with the following arguments quartus_pfg c fpga sof application rpd o mode ASX4 o start_address address o bitswap ON Alternative...

Page 154: ...ault the rpd file type is little endian if you are using a third party programmer that does not support the little endian format Set the Bit swap to On to generate the rpd file in big endian format 8...

Page 155: ...data and the factory image Note Starting with the Stratix 10 device family the rpd to program flash memory includes firmware pointer information for image addresses as shown in Table 1 You must use t...

Page 156: ...w Programming Data Specify Output Directory Specify Output File Name Specify Device Family Specify Start Address in Flash Edit 7 By default the rpd file type is little endian If you are using a third...

Page 157: ...Data Add Bitstream Input files to convert Generate 9 Select the sof and then click Properties Turn On Remote System Firmware Update 4 Remote System Update RSU UG 20205 2019 10 09 Send Feedback Intel A...

Page 158: ...Click Generate to generate the RSU programming files You can now update the Intel Agilex firmware You can save the configuration in a pfg file for later use 4 Remote System Update RSU UG 20205 2019 10...

Page 159: ...x4 interface QSPI_CLOSE 4 6 Remote System Update from FPGA Core Example This section presents a complete remote system update example including the following steps 1 Creating the initial remote syste...

Page 160: ...on Master Bridge as shown the Platform Designer system The JTAG to Avalon Master Bridge acts as the remote system update host controller for your factory and application images Figure 67 Required Comm...

Page 161: ...rent Intel Quartus Prime Software only supports remote system update feature in Active Serial x4 4 On the Output Files tab assign the output directory and file name 5 Select the output file type Selec...

Page 162: ...e Input Files tab click Add Bitstream select the factory and application image sof files and click Open 4 Remote System Update RSU UG 20205 2019 10 09 Intel Agilex Configuration User Guide Send Feedba...

Page 163: ...Bitstream_1 is the bitstream for factory image b Bitstream_2 is the bitstream for application image 4 Remote System Update RSU UG 20205 2019 10 09 Send Feedback Intel Agilex Configuration User Guide 1...

Page 164: ...emory and click Add Partition 11 In the Add Partition dialog box select Bitstream_2 for the application image sof in the Input file drop down list Assign Page 1 Keep the default settings for Address M...

Page 165: ...4 Remote System Update RSU UG 20205 2019 10 09 Send Feedback Intel Agilex Configuration User Guide 165...

Page 166: ...F SPT1 0x002DC000 0x002E3FFF CPB0 0x002E4000 0x002EBFFF CPB1 0x002EC000 0x002F3FFF Application Image 0x002F4000 0x004B7FFF Configuration device AFGA014R24A2 Configuration mode Active Serial x4 Quad Se...

Page 167: ...edure 1 open the Programmer and click Add File Select the generated jic file Initial_RSU_Image jic and click Open 2 Turn on the Program Configure for the attached jic file 3 To begin programming the f...

Page 168: ...4 Remote System Update RSU UG 20205 2019 10 09 Intel Agilex Configuration User Guide Send Feedback 168...

Page 169: ...Debugging Tools System Console to launch the system console b In the Tcl Console pane type source rsu1 tcl to open the example of Tcl script to perform the remote system update commands Refer to the R...

Page 170: ...4 Remote System Update RSU UG 20205 2019 10 09 Intel Agilex Configuration User Guide Send Feedback 170...

Page 171: ...e start address of the factory image as shown in the map file The JTAG host automatically disconnects from the System Console once the device reconfiguration is successful You must restart the System...

Page 172: ...nterface and flash until you relinquish access by running the QSPI_CLOSE command Write the new application image to the flash memory using the QSPI_WRITE command 2 Alternatively the rsu1 tcl script in...

Page 173: ...FFFFF before initiating the write Note You must update both copies CBP0 and CBP1 when editing the configuration firmware pointer block and sub partition table Refer to Table 1 for more details about t...

Page 174: ...F CPB1 0x20 0x002EC020 Current application image pointer entry highest priority 0x002F4000 CPB1 0x28 0x002EC028 Next image pointer entry 0xFFFFFFFF You can use the QSPI_read function verify that the n...

Page 175: ...write the new application image address to next image entry by using the QSPI_write_one_word function The QSPI_write_one_word function takes in two arguments 1 Address 2 The value of the word 4 Remot...

Page 176: ...an power cycle the PCB After reconfiguration check the current image address The expected address is 0x03ff0000 After adding a new image your application image list includes the newly added applicatio...

Page 177: ...plication image content in the flash memory using the QSPI_ERASE command 4 To remove a new application image add another new application image in the next or subsequent image pointer entry or allow th...

Page 178: ...The QSPI_write_one_word function takes address and data arguments Be sure to erase the application content that you just removed from flash memory You can use a QSPI_read to the image pointer entry a...

Page 179: ...has the highest priority if you power cycle the device or the host asserts the nCONFIG pin You can run the rsu_status report to check the status of the current image address 0x002f4000 4 Remote Syste...

Page 180: ...es the FPGA fabric through the PCI Express PCIe link and is available for Endpoint variants only UG 20205 2019 10 09 Send Feedback Intel Corporation All rights reserved Agilex Altera Arria Cyclone Enp...

Page 181: ...als Optional Monitoring 10k MSEL VCCIO_SDM AS x4 Flash Memory DATA 3 0 DCLK nCS0 PCIe Link Core Image Update via PCIe Link 3 4 Periphery Image jic PCIe Host Core Image rbf 1 2 3 n End Point Core Image...

Page 182: ...ration scheme that uses the PCIe link to deliver an updated bitstream to a target device after the device enters user mode The periphery images which includes the PCIe link remains active allowing CvP...

Page 183: ...Boot ROM code or configuration firmware Use the SDM Debug Toolkit to answer this question 10 Are the MSEL pins correctly connected on board Use the SDM Debug Toolkit to answer this question 11 For de...

Page 184: ...V I 0 verify that the transceiver tiles are powered up before configuration begins Related Information Intel Agilex Power Management User Guide 6 2 Intel Agilex Configuration Architecture Overview Int...

Page 185: ...ter the SDM boot ROM performs device consistency checks Figure 71 Example of an Intel Agilex Configuration Bitstream Structure Firmware Section Firmware section Quartus Prime version dependent Design...

Page 186: ...Transceivers May Fail To Configure Making the PRESERVE_UNUSED_XCVR_CHANNEL assignment to completely unused E tile transceivers may cause configuration failures in Intel Agilex devices The Intel Quart...

Page 187: ...us Prime Software and the clock source on your board Ensure a free running reference clock is present for designs using transceivers PCIe or HBM2 These reference clocks must be available until the dev...

Page 188: ...est The nSTATUS pin indicates device readiness to initiate FPGA configuration The configuration source can only change the state of the nCONFIG pin when it has the same value as nSTATUS When the Intel...

Page 189: ...ggestions Ensure nSTATUS acknowledges nCONFIG If nSTATUS is not following nCONFIG the FPGA may not have exited POR You may need to power cycle the PCB 6 7 3 CONF_DONE and INIT_DONE For Intel Agilex de...

Page 190: ...ions such as CONF_DONE and INIT_DONE The configuration bitstream controls the pin locations for the SDM_IO pins Internal Intel Agilex circuitry pulls SDM_IO0 SDM_IO8 and SDM_IO16 weakly low through a...

Page 191: ...Figure 72 Configuration Pin Selection in the Intel Quartus Prime Pro Edition Software 6 Intel Agilex Debugging Guide UG 20205 2019 10 09 Send Feedback Intel Agilex Configuration User Guide 191...

Page 192: ...rime Pro Edition Software version 18 1 an SDM Debug Toolkit is available through the System Console Tools System Debugging Tools System Console Intel Agilex SDM Debug Toolkit 6 Intel Agilex Debugging...

Page 193: ...other countries Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel s standard warranty but reserves the right to make changes to any...

Page 194: ...t configuration bitstream for the AS x4 configuration scheme in the Debugging Guidelines for the AS Configuration Scheme topic Corrected the signal name in The AVST_READY Signal topic The device can s...

Page 195: ...F Pointer Block Layout Modifying the List of Application Images Application Image Layout Command Sequence To Perform Quad SPI Operations The static firmware has been replaced by decision CMF The updat...

Page 196: ...e device reverts to the MSEL specified boot source nSTATUS must be stable during JTAG configuration In both sentence nSTATUS should be nCONFIG Removed pin assignments for CVP_CONFDONE for the Avalon S...

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