Intel AGIB027R29A1E2VR0 User Manual Download Page 44

Page: 44 / 63

Figure 31.

MCIO Connector Circuit

GND_A1

CXL_RX_P0

CXL_RX_N0
CXL_RX_P1

CXL_RX_N1

CXL_PRSNTx1_N

CXL_RX_P2

CXL_RX_P3

CXL_RX_N2

CXL_RX_N3
CXL_RX_P4

CXL_RX_N4
CXL_RX_P5

CXL_RX_P6

CXL_RX_N5

CXL_RX_N6

CXL_RX_P7

CXL_RX_N7

CXL_PERST1_N

CXL_PRSNTx4_N

0, DNI

R187

I2C2_SCL 27, 46, 50, 52

I2C2_SDA 27, 46, 50, 52

CXL_PERSTn 33, 48, 52

RX0_0P

RX0_0N

GND_A4

RX0_1P

RX0_1N

GND_A7

SMB0_SCL

SMB0_SDA

GND_A10

PERST0_N

PRSNT0_N

GND_A13

RX0_2P

RX0_2N

GND_A16

RX0_3P

RX0_3N

GND_A19

RX1_0P

RX1_0N

GND_A22

RX1_1P

RX1_1N

GND_A25

SMB1_SCL

SMB1_SDA

GND_A28

PERST1_N

PRSNT1_N

GND_A31

RX1_2P

RX1_2N

GND_A34

RX1_3P

RX1_3N

GND_A37

MH1

MH3

GND_B1

CXL_TX_C_P0

C354

0.22uF SMC0201IA

CXL_TX_P0

0.22uF SMC0201IA

49 CXL_SMB_ALERT_N

CXL_TX_N1

0.22uF SMC0201IA

CXL_TX_P1

0.22uF SMC0201IA

CXL_TX_N0

CXL_TX_C_N0

C355

CXL_TX_C_P1

C356

CXL_TX_C_N1

CLK_100M_CXL_CONN_C_P

R185

45 CLK_CXL_CONN_P

CLK_100M_CXL_CONN_C_N

R186

45 CLK_CXL_CONN_N

C357

0.22uF SMC0201IA

CXL_TX_P2

CXL_TX_C_P2

C358

0.22uF SMC0201IA

CXL_TX_P3

CXL_TX_C_P3

C360

0.22uF SMC0201IA

CXL_TX_N3

CXL_TX_C_P3

C361

0.22uF SMC0201IA

CXL_TX_P4

CXL_TX_C_P4

C362

0.22uF SMC0201IA

CXL_TX_N4

CXL_TX_C_N4

C363

0.22uF SMC0201IA

CXL_TX_P5

CXL_TX_C_P5

C364

0.22uF SMC0201IA

CXL_TX_N5

CXL_TX_C_N5

C365

0.22uF SMC0201IA

CXL_TX_P6

CXL_TX_C_P6

C366

0.22uF SMC0201IA

CXL_TX_N6

CXL_TX_C_N6

C367

0.22uF SMC0201IA

CXL_TX_P7

CXL_TX_C_P7

C368

0.22uF SMC0201IA

CXL_TX_N7

CXL_TX_C_N7

C369

0.22uF SMC0201IA

CXL_TX_N2

CXL_TX_C_N2

C359

TX0_0P

TX0_0N

GND_B4

TX0_1P

TX0_1N

GND_B7

NC_B8

SMB0_ALERT_N

GND_B10

CLK0_DP

CLK0_DN

GND_B13

TX0_2P

TX0_2N

GND_B16

TX0_3P

TX0_3N

GND_B19

TX1_0P

TX1_0N

GND_B22

TX1_1P

TX1_1N

GND_B25

NC_B26

SMB1_ALERT_N

GND_B28

CLK1_DP

CLK1_DN

GND_B31

TX1_2P

TX1_2N

GND_B34

TX1_3P

TX1_3N

GND_B37

MH2

MH4

MCIO_74P_G97V22312HR

K64129-002

GND_A1

RX0_0P

RX0_0N

GND_A4

RX0_1P

RX0_1N

GND_A7

SMB0_SCL

SMB0_SDA

GND_A10

PERST0_N

PRSNT0_N

GND_A13

RX0_2P

RX0_2N

GND_A16

RX0_3P

RX0_3N

GND_A19

RX1_0P

RX1_0N

GND_A22

RX1_1P

RX1_1N

GND_A25

SMB1_SCL

SMB1_SDA

GND_A28

PERST1_N

PRSNT1_N

GND_A31

RX1_2P

RX1_2N

GND_A34

RX1_3P

RX1_3N

GND_A37

MH1

MH3

GND_B1

TX0_0P

TX0_0N

GND_B4

TX0_1P

TX0_1N

GND_B7

NC_B8

SMB0_ALERT_N

GND_B10

CLK0_DP

CLK0_DN

GND_B13

TX0_2P

TX0_2N

GND_B16

TX0_3P

TX0_3N

GND_B19

TX1_0P

TX1_0N

GND_B22

TX1_1P

TX1_1N

GND_B25

NC_B26

SMB1_ALERT_N

GND_B28

CLK1_DP

CLK1_DN

GND_B31

TX1_2P

TX1_2N

GND_B34

TX1_3P

TX1_3N

GND_B37

MH2

MH4

MCIO_74P_G97V22312HR

K64129-002

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

MH1

MH3

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37
MH2

MH4

CXL_RX_P8

CXL_RX_N8
CXL_RX_P9

CXL_RX_N9

CXL_PRSNTx8_N

CXL_PERST2_N

CXL_RX_P10

CXL_RX_P11

CXL_RX_N10

CXL_RX_N11
CXL_RX_P12

CXL_RX_N12
CXL_RX_P13

CXL_RX_P14

CXL_RX_N13

CXL_RX_N14

CXL_RX_P15

CXL_RX_N15

CXL_PERST3_N

CXL_PRSNTx16_N

0, DNI

R189

R188

0, DNI

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

MH1

MH3

CXL_TX_C_P8

C373

0.22uF SMC0201IA

CXL_TX_P8

0.22uF SMC0201IA

CXL_TX_N9

Design Note:

Clock for RootPort mode.

0.22uF SMC0201IA

CXL_TX_P9

0.22uF SMC0201IA

CXL_TX_N8

CXL_TX_C_N8

C374

CXL_TX_C_P9

C375

CXL_TX_C_N9

44 REFCLK_CXL_RP_P1

44 REFCLK_CXL_RP_N1

C376

0.22uF SMC0201IA

CXL_TX_P10

CXL_TX_C_P10

C377

0.22uF SMC0201IA

CXL_TX_P11

CXL_TX_C_P11

C379

0.22uF SMC0201IA

CXL_TX_N11

CXL_TX_C_P11

C380

0.22uF SMC0201IA

CXL_TX_P12

CXL_TX_C_P12

C381

0.22uF SMC0201IA

CXL_TX_N12

CXL_TX_C_N12

C382

0.22uF SMC0201IA

CXL_TX_P13

CXL_TX_C_P13

C383

0.22uF SMC0201IA

CXL_TX_N13

CXL_TX_C_N13

C384

0.22uF SMC0201IA

CXL_TX_P14

CXL_TX_C_P6

C385

0.22uF SMC0201IA

CXL_TX_N14

CXL_TX_C_N6

C386

0.22uF SMC0201IA

CXL_TX_P15

CXL_TX_C_P7

C387

0.22uF SMC0201IA

CXL_TX_N15

CXL_TX_C_N7

C388

0.22uF SMC0201IA

CXL_TX_N10

CXL_TX_C_N10

C378

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37
MH2

MH4

Design Note:

Clock for RootPort mode.

44 REFCLK_CXL_RP_P0

44 REFCLK_CXL_RP_N0

A.5. MCIO Cable Assembly Information

The cable is not provided with the development kit. For more information, contact

Intel Premier Support and quote ID #14016163317.

A.6. Network Interfaces

The development kit supports two QSFPDD connectors each, connecting to the Intel

Agilex's F-tile (12A) transceivers. Each port can operate at 4x 58G or 8x 28G. These

two ports support ZQSFP56 SR optical modules as well as the 3M DAC electrical

cables. A Texas Instruments FPC202 dual-port controller serves as the low-speed

signal aggregator that makes up the Dual 100Gpbs Ethernet interfaces. The FPC202

aggregates all low speed and I2C signals across two ports and presents it as a single

management interface to the host.

A. Development Kits Components

683288 | 2022.09.22

Intel

Agilex

™

I-Series FPGA Development Kit User Guide

Send Feedback

Summary of Contents for AGIB027R29A1E2VR0

Page 1: ...Intel Agilex I Series FPGA Development Kit User Guide Online Version Send Feedback UG 20338 ID 683288 Version 2022 09 22...

Page 2: ...ing Environment 22 4 1 1 Download OpenJDK 23 4 1 2 Download OpenJFX 23 4 1 3 Install OpenJDK and OpenJFX 24 4 1 4 Run BTS GUI 24 4 2 Test the Functionality of the Development Kit 25 4 2 1 The Bottom I...

Page 3: ...wer Measurement 54 A 14 Temperature Monitoring 55 A 15 Mechanical Requirements 55 A 16 Board Thermal Requirements 56 A 17 Board Operating Conditions 57 A 18 Over Temperature Warning LED 57 B Additiona...

Page 4: ...and receive CXL soft R Tile Wrapper and Soft Support logic purchase or activation of a separate CXL IP license is required for proper use with the Intel Quartus Prime Design Software Contact your loc...

Page 5: ...with ECC Comp CH1 DDR4 x72 with ECC 12A F Tile x20 GPIO 3A 3B 3C 3D HPS USB PHY Feature Summary Intel Agilex I Series AGIB027 device in the 2957A BGA package 0 8 VID adjustable VCC core R tile transce...

Page 6: ...ons switches and LEDs System reset push button CPU reset push button PCIe reset push button Four dedicated user LEDs Link LED of each QSFP28 port to indicate the link and data transceiver Two dedicate...

Page 7: ...0 C to 35 C Maximum ICC load current 198 A Maximum ICC load transient percentage 30 Maximum FPGA power supported by the supplied heatsink fan 180 W Handling Precautions When handling the board observ...

Page 8: ...rtus Prime Standard Edition or Intel Quartus Prime Pro Edition you can use that license file with this kit If not follow these steps 1 Log on at the My Intel Account Sign In web page and click Sign In...

Page 9: ...e board before shipment Use this data to restore the board with its original factory content Related Information Intel Agilex I Series FPGA Development Kit 2 3 Installing the Intel FPGA Download Cable...

Page 10: ...can be damaged by power supplies with greater voltage 2 Set the power switch SW6 to the ON position When the board powers up the blue power LED illuminates and the board is ready for use The blue LED...

Page 11: ...1 Switch Default Position Function SW1 1 4 ON OFF OFF OFF PCIe PRSNT x1 x4 x8 x16 settings Default x16 PCIe PRSNT x16 PCIe PRSNT x8 PCIe PRSNT x4 PCIe PRSNT x1 ON OFF OFF OFF SW2 1 4 ON OFF OFF X Conf...

Page 12: ...JTAG Select Intel MAX 10 JTAG Enable Intel MAX 10 JTAG Disable 4 Not used X X SW6 ON OFF When the board is not in a PCIe slot it must be powered by an external power supply The SW6 switch turns on the...

Page 13: ...ure 4 SW2 1 4 Switch Setting Figure 5 SW3 1 4 Switch Setting Figure 6 SW4 Switch Setting 3 Development Board Setup 683288 2022 09 22 Send Feedback Intel Agilex I Series FPGA Development Kit User Guide...

Page 14: ...DRT Dual DIMM A J2 DIMM B connector DDR4 DDRT Dual DIMM B J5 PCIe x16 Gold Finger J6 J7 CXL PCIe connectors For connecting the external CXL PCIe MCIO cables J24 Fan connector For connecting to the hea...

Page 15: ...tem Intel MAX 10 pre programmed If you want to restore board QSPI flash with factory default image follow these steps 1 Connect the USB cable between J8 USB connector and your computer 2 Open Intel Qu...

Page 16: ...b to specify a sof that contains the configuration bitstream 6 Click on the Configuration Device Add Device to specify the flash device In the Device list of the pop up window select CFI_2Gb for the c...

Page 17: ...e to generate the pof file 3 4 How to Program the Generated POF Image To program the generated POF image follow these steps 1 Plug in the USB cable to the USB port J8 or J10 when using J10 DIPSWITCH S...

Page 18: ...to Detect to scan the JTAG devices 7 Right click the VTAP10 device Edit Change Device change it to MAX 10 10M50DAF256 3 Development Board Setup 683288 2022 09 22 Intel Agilex I Series FPGA Development...

Page 19: ...vice select Quad SPI Flash Memory QSPI_2Gb 9 In the Programmer page click QSPI_2Gb Change File to select the pof file 10 Start the Programmer 3 Development Board Setup 683288 2022 09 22 Send Feedback...

Page 20: ...FPGA development kit to configure successfully Before you add the following SmartVID setting into the Quartus settings file qsf you must change the configuration scheme to Avalon streaming interface x...

Page 21: ...nment name PWRMGT_SLAVE_DEVICE1_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE_DEVICE2_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE_DEVICE3_ADDRESS 00 set_global_assignment name PWRMGT_SLAVE...

Page 22: ...oad and install Java runtime including OpenJDK and OpenJFX on your systems and set up the running environment This is a one time procedure so if you have already completed it before you do not need to...

Page 23: ...se the JRE tar gz format file Note The JDK version can be updated download the latest version 4 1 2 Download OpenJFX To download the OpenJFX follow these steps 1 Download the OpenJFX using this link h...

Page 24: ...the files and rename the folders using the following commands unzip openjfx 17 0 2_linux x64_bin sdk zip d opt Java tar zxvf OpenJDK11U jre_x64_linux_hotspot_11 0 15_10 tar gz C opt Java cd opt Java...

Page 25: ...f the board is connected to the system The green sign turns gray if the board becomes disconnected Intel Quartus Prime Version Displays the current Intel Quartus Prime version installed and active on...

Page 26: ...3 When configuration finishes the design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled If you use the Intel Quartus Prime Programmer...

Page 27: ...in The JTAG chain control shows all the devices currently in the JTAG chain Note Change the settings of SW5 to bypass or enable power for Intel MAX 10 and Intel Agilex FPGA System Intel MAX 10 and FPG...

Page 28: ...Access Over MAX10 allows you to read and write the data at the address you specify Qsys Memory Map The Qsys Memory Map control shows the memory map of bts_config sof design running on your board 4 2 5...

Page 29: ...d or unlocked state Pattern Sync Shows the pattern synced or not state The pattern is considered synced when the start of the data sequence is detected Detail Shows the PLL lock and pattern sync statu...

Page 30: ...he transmitter buffer Post tap 1 Specifies the amount of pre emphasis on the post tap of the transmitter buffer Figure 20 QSFPDD PMA Setting Data Type The Data Type control specifies the type of data...

Page 31: ...ansmit data stream each time you click the button Insert error is only enabled during transaction performance analysis Clear Resets the Detected Errors counter and Inserted Errors counter to zeros Run...

Page 32: ...F tile performance the QSFPDD0 only reserves 4 channels 4 2 6 The RAM Tab This tab allows you to read and write DDR4 COMP0 DDR4 COMP1 and DDR4 RDIMM memory on your board Download DDR4 designs through...

Page 33: ...hieve Write MBps and Read MBps Show the number of bytes analyzed per second Data Bus 72 bits 8 bits ECC wide reference clock is 100 MHz and the frequency is 1066 MHz double data rate 2133 MT s Test Co...

Page 34: ...Bit Error Rate Calculates the bit error rate of the transmit data stream Insert Insert a one word error into the transaction stream each time you click the button Insert error is only enabled during t...

Page 35: ...lso be started with the BTS GUI icon Clock The Clock Controller communicates with the System Intel MAX 10 device through either USB port J8 or 10 pin JTAG header J10 Then System Intel MAX 10 controls...

Page 36: ...1 to update the settings of the NVM Register changes are volatile after power cycling Clockbuilder Pro Software on Skyworks website 4 4 Monitor On board Power Regulator through Power Monitor GUI The P...

Page 37: ...mp R Tile 15C Temp R Tile 15A Temp FPGA die internal temperature sense diodes 4 5 BTS Test Areas BTS checks for hardware fault before you can use the board If one or more BTS test items fail it implie...

Page 38: ...Plug QSFPDD0 QSFPDD1 loopback module in J3 J4 before you configure QSFPDD NRZ example build through BTS GUI 4 Board Test System 683288 2022 09 22 Intel Agilex I Series FPGA Development Kit User Guide...

Page 39: ...pdated Figure Windows Console Updated Figure Linux Console Updated Figure The Configure Menu Updated Figure The Sys Info Tab Updated Figure The QSFPDD NRZ Tab Updated Figure QSFPDD PMA Setting Updated...

Page 40: ...ing Added Figure SW5 1 4 Switch Setting Updated the PCIe and CXL Interfaces section Updated Figure Intel Agilex I Series FPGA Development Board Image Front Updated the header of Table Intel Agilex I S...

Page 41: ...back Intel Corporation All rights reserved Intel the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries Intel warrants performance of its FPGA and semiconductor p...

Page 42: ...ceive CXL soft R Tile Wrapper and Soft Support logic purchase or activation of a separate CXL IP license is required for proper use with the Intel Quartus Prime Design Software Contact your local Inte...

Page 43: ...Figure 30 MCIO Connector J7 J6 MCIO Connectors for CXL PCIe Interface A Development Kits Components 683288 2022 09 22 Send Feedback Intel Agilex I Series FPGA Development Kit User Guide 43...

Page 44: ...2HR K64129 002 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 MH1 MH3 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12...

Page 45: ...28 Gbps NRZ and 325 50 MHz clocks for the 56 Gbps PAM4 These clocks must have RPM jitter 250fs Figure 32 F Tile Bank 12A Circuit A 7 Port Controller A Texas Instrument FPC202 dual port controller ser...

Page 46: ...26 48 49 56 55 2 1 3 5 4 6 7 17 18 11 13 10 12 14 16 15 50 47 46 IO_3p3V R133 4 70k 0402 1 R132 4 70k 0402 1 C304 0 1uF 0402 25V X6S C303 1uF 0402 25V X6S C302 0 1uF 0402 25V X6S C300 0 1uF 0402 25V...

Page 47: ...faces to the Intel Agilex FPGA in the AVST x8 mode The Intel MAX 10 also interfaces to the QSPI flash in the active serial AS x4 mode For the AS x4 mode MSEL 2 0 configuration pin strapping SW2 must b...

Page 48: ...supported Two independent on board DDR4 and one dual DIMM sockets for DDR4 or DDR T The on board DDR4 uses five 16Gb DDR4 single rank devices connecting to Bank 2B 2E for memory component channel 0 an...

Page 49: ...42 EM2140P 0x45 EM2120L 0x46 EM2120L I2C2 0x1E FPC202 0x57 0x5F M24128 0x38 MAX31730 0x3A MAX31730 0xA0 QSFPDD_0 0xA0 QSFPDD_1 I2C3 0xA0 DDR4_DIMM0 PCIE_EP_3V3_I2C 0xA2 DDR4_DIMM1 Intel MAX 10 I2C Add...

Page 50: ...re 36 Clock Connection Diagram 2B 2E 2F 2C 3A SDM 12A F Tile 14C R Tile Si53307 Mux_buffer 15C R Tile 3B 3C 3D Intel Agilex FPGA CXL CONN Si510 Si52204 Outputs x4 Si5391 Outputs x12 Intel MAX 10 Downl...

Page 51: ...this mode plug the board into an available PCI Express slot and connect the standard 2x4 power cords available from the PC s ATX power supply to J11 on the board The PCIe slot together with the auxili...

Page 52: ...ply A 13 2 Power Distribution System The following figure below shows the power distribution system on the Intel Agilex I Series FPGA development board A Development Kits Components 683288 2022 09 22...

Page 53: ...48 POWER_ON 12V_G2 3p3V_EN IO_3p3V_EN LTC4365 Selew Rate Ctlr 0 02A FB29 VCC 174A VCCP 21 34A VCCPLLDIG_SDM 0 02A VCCRT_FGT_GXF_EN VCCR_CORE VCCE_PLL_EN VCCE_PLL_DTS_GXR 2p5V VTT_DDR4_CH01_EN 0p6V_VRE...

Page 54: ...AT VCCFUSEWR_SDM IO_3p3V QSFPDD0_VCC VCCT VCCR QSFPDD1_VCC VCCT VCCR 1p2V_DDR4_CH01 1p2V_DDR4_CH02 0p6V_VREF_DDR4_CH01 0p6V_VREF_DDR4_CH02 0p6V_VTT_DDR4_CH01 0p6V_VTT_DDR4_CH02 VCCPIO VCCR_CORE VCCA_P...

Page 55: ...ard Temperature Measurement Circuit DXP1 EU1 DXN1 DXP2 DXN2 DXP3 DXN3 SDA SCL VDD 1 2 3 4 5 6 7 11 12 9 10 8 13 3p3V_STBY 3p3V_STBY THERM ADD GND GND_EP MAX31730ATC C570 0 1 F I2C ADDR 3A TEMP2_THERMn...

Page 56: ...signed to cool up to 250W total power of the board An active cooling design is used The heatsink is designed to meet the height constraints of a 2 slot PCIe card form factor as defined by the PCIe CEM...

Page 57: ...ing Conditions Operating Condition Range Maximum power dissipation 250W Maximum ambient temperature 0 C to 35 C FPGA junction temperature 85 C A 18 Over Temperature Warning LED A red colored LED D9 is...

Page 58: ...tle 47 the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47 Safety Assessment an...

Page 59: ...emove all DC power from the board system The socket outlet must be installed near the equipment and must be readily accessible System Grounding Earthing To avoid shock you must ensure that the power c...

Page 60: ...tenance of this product during an electrical storm Risk of Fire To reduce the risk of fire keep all flammable materials a safe distance away from the boards and power supply You must configure the dev...

Page 61: ...interference to radio communications If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment on and off you are required to...

Page 62: ...e Risk of fire explosion or chemical burn if the battery is mistreated punctured or crushed Do not attempt to disassemble Do not incinerate Observe proper polarity when replacing battery Do not dispos...

Page 63: ...tandards mandated by Directive 2014 30 EU Because of the nature of programmable logic devices it is possible for the user to modify the development kit in such a way as to generate electromagnetic int...

Search results

Summary of Contents for AGIB027R29A1E2VR0

Reviews:

Related manuals for AGIB027R29A1E2VR0

Brands by name

Popular brands

Intel AGIB027R29A1E2VR0, User Manual

Search results

Summary of Contents for AGIB027R29A1E2VR0

Reviews:

Related manuals for AGIB027R29A1E2VR0

Brands by name

Popular brands